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nrf: Replace custom-HAL with nrfx-HAL

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Summarized this squashed PR replaces the hal/ folder in the port. This has been replaced the official
HAL layer from Nordic Semiconductor; https://github.com/NordicSemiconductor/nrfx.

A Git submodule has been added under lib/nrfx, for the nrfx dependency.

The drivers / modules has been updated to use this new HAL layer; nrfx at v1.0.0.

Also, header files and system files for nrf51/nrf52x chip variants has been deleted from the device/ folder, only keeping back the startup files written in C. All other files are now fetched from nrfx.

3 new header files in the ports/nrf/ folder has been added to configure nrfx (nrfx_config.h), logging (nrfx_log.h) and glue nrfx together with the drivers and modules from micropython (nrfx_glue.h).

The PR has been a joint effort from @aykevl (Ayke van Laethem) and @glennrub.

For reference, the commit log will be kept to get an overview of the changes done:

* ports/nrf: Initial commit for moving hal to Nordic Semiconductor BSD-3 licensed nrfx-hal.

* ports/nrf: Adding nrfx, Nordic Semiconductor BSD-3 hal layer, as git submodule checked out at lib/nrfx.

* ports/nrf/modules/machine/uart: Fixing bug which set hwfc to parity excluded, always resulting in no flow control, hence corrupted output. Also adding an extra loop on uart_tx_char to prevent any tx when any ongoing tx is in progress.

* ports/nrf/i2c: Moving I2C over to nrfx driver.

* ports/nrf/modules/machine/i2c: Alignment. Renaming print function param 'o' to 'self_in'

* ports/nrf/spi: Updating SPI machine module to use nrfx drivers.

* ports/nrf: Renaming modules/machine/rtc.c/.h to rtcounter.c/.h to not confuse the peripheral with Real-Time Clock:

* ports/nrf: Updating various files after renaming machine module RTC to RTCounter.

* ports/nrf: Renaming RTC to RTCounter in modmachine globals dict table. Also updating object type name to reflect new module name.

* ports/nrf: Fixing leftovers after renaming rtc to rtcounter.

* ports/nrf: Early untested adoption of nrfx_rtc in RTCounter. Untested.

* nrf/modules/machine/i2c: Improve keyword argument handling

* ports/nrf/modules/temp: Updating Temp machine module to use nrfx defined hal nrf_temp.h. Moving logic of BLE stack awareness to machine module.

* ports/nrf/boards/pca10040: Enable machine Temp module.

* nrf/modules/machine/rtcounter: Remove magic constants.

* ports/nrf: Adding base support for nrfx module logging. Adding option to disable logging of UART as it might log its own setup over UART while the peripheral is not yet set up. Logging of UART could make sense if other transport of log is used.

* ports/nrf: updating nrfx_log.h with more correct parenthisis on macro grouping.

* ports/nrf: Updating nrfx logging with configuration to disable logging of UART module. The pattern can be used to turn off other modules as well. However, for now UART is the only module locking itself by logging before the peripheral is configured. Logging is turned off by default, can be enabled in nrfx_config.h by setting NRFX_LOG_ENABLED=1.

* ports/nrf/modules/random: Updating modrandom to use nrfx hal for rng. Not using nrfx-driver for this peripheral as its blocking mode would do the trick on RNG. Moving softdevice aware code from legacy hal to modrandom.c.

* nrf: Enable Peripheral Resource Sharing.

This enables TWI and SPI to be enabled at the same time.

* nrf/Makefile: Define MCU sub variant (e.g. NRF51822/NRF51422)

* nrf: Port TIMER peripheral to nrfx HAL.

* nrf/modules/machine/uart: Optimize UART module

For a nRF51, this results in a size reduction of:
.text: -68 bytes
.data: -56 bytes

* nrf/modules/machine/uart: Don't use magic index numbers.

* nrf/modules/machine/uart: Fix off-by-one error.

For nrf51:
.text: -40 bytes

* nrf/modules/machine/rtcounter: Update for nrfx HAL.

* nrf/modules/machine/i2c: Reduce RAM consumption.

Reductions for the nrf51:
flash: -108 bytes
RAM:   -72 bytes

* nrf/mpconfigport: Avoid unnecessary root pointers.

This saves 92 bytes of RAM.

* nrf: Support SoftDevice with nrfx HAL.

* nrf: Add NVMC peripheral (microbitfs) support.

There is no support yet for a SoftDevice.

It also fixes a potentially serious bug in start_index generation.

* nrf/modules/machine/spi: Optimize SPI peripheral.

nrf51:
text: -340 bytes
data: -72  bytes

nrf52:
text: -352 bytes
data: -108 bytes

* nrf/modules/random: Forgot to commit header file.

* nrf: Make nrfx_config.h universal for all boards.

* nrf: Use SoftDevice API for flash access when built for SD

* nrf/drivers/bluetooth: Remove legacy HAL driver includes.

These were not used anymore so can be removed.

* ports/nrf/microbit: Port microbit targets to nrfx HAL

Initial port of microbit modules to use nrfx HAL layer.
Tested display/image and modmusic on micro:bit to verify that
softpwm and ticker for nrf51 is working as expected.

Changing IRQ priority on timer to priority 2, as 1 might collide if
used side by side of SD110 BLE stack.

The patch reserves Timer1 peripheral compile time. This is not ideal
and should be resolved in seperate task.

* nrf/boards/microbit: Remove custom nrfx_config.h from microbit target, adding disablement of timer1 if softpwm is enabled.

* nrf/adc: Update ADC module to use nrfx

* nrf/modules/machine/pwm: Updating machine PWM module to use nrfx HAL driver.

examples/nrf52_pwm.py and examples/nrf52_servo.py tested on pca10040.

* nrf: Removing hal folder and boards nrf5x_hal_conf.h headers.

* nrf/nrfx_glue: Adding direct NVIC access for S110 BLE stack

If SoftDevice s110 has not yet been initialized, the IRQ will not be forwarded to
the application using the sd_nvic* function calls. Hence, direct access to cmsi
nvic functions are used instead if SoftDevice is not enabled.

* nrf/drivers/ticker: Setting IRQ priority 3 on Timer1

SoftDevice fails to initilize if Timer1 has been configured to priority
level 2 before enabling the SD. The timer is set to priority 1, higher than BLE
stack in order to provide better quality of music rendering when used with the
music module. This might be too high, time will show.

* nrf/examples: Updating ubluepy_temp after moving RTCounter to nrfx.

* nrf: delete duplicate files from device folder which can be located in nrfx/mdk.

* nrf/Makefile: Fetch system files from nrfx.

Testing on each device sub-variant to figure out which system file to
use. Reason for this is that nrf52.c is actually defining nrf52832.

Removing NRF_DEFINES parameter setting the device in use into the
same sub-variant test, as NRF52 is unique to nrf52832 when using nrfx.
Without this exclusion of -DNRF52 in compilation for nrf52840, the
device will be interpreted as a nrf52, hence nrf52832.

Also, changing name on variable SRC_NRF_HAL to SRC_NRFX_HAL to
explicitly tell the origin of the file.

* nrf: Updating device #ifdefs to be more open to non-nrf51 targets.

* nrf/modules/machine/uart: Removing second instance of UART for nrf52840 as it only has one non-DMA variant.

* nrf/device: Removing system files as these are now used from nrfx/mdk

* nrf: Moving startup files in device one level up as there is no need for deep hierarchy.

* nrf: Use NRF52_SERIES defined in nrfx/mdk/nrf.h as define value when testing for both nrf52(832) and nrf52840 variants.

* nrf/modules/machine/uart: Enable UART RX by default

Enable rx by default after intiialization of the peripheral.
Else, the nrfx driver will re-enable rx for each byte read
on uart REPL, clearing the EVENT_RXDRDY before second byte,
which again will make second byte get lost and read will get stuck.

This happens if the bytes are transmitted nrf(51) while still
processing the previous byte. Not seen on nrf52, but should
also become an issue at higher speeds.

This patch sets rx to always be enabled. Hence, not clearing the event
between read bytes, and it will be able to detect next byte recieved
upon finishing the first.

* nrf/modules/machine/timer: Fixing defines excluding Timer1 if ticker/softpwm is used.

* nrf: Switching import form mpconfigboard.h to mpconfigport.h in nrfx_config.h as mpconfigboard.h might define default values for defines not set by board specific header.

* nrf/modules/machine/i2c: nrfx integration fixes

Increasing speed to 400K.

Returning Address NACK's as MP error code; MP_ENODEV.

Returning MP_ETIMEOUT on all other error codes from TWI nrfx driver
except the ANACK.

Enabling and disabling the TWI peripheral before and after each transaction.

* nrf/examples: Updating ssd1306_mod.py to split framebuffer transfer into multiple chunks

* nrf/modules/machine/i2c: Return MP_EIO error if Data NACK occurs.

* nrf: Addressing review comments.

* nrf: Updating git submodule and users to nrfx v1.0.0.

* nrf/modules/machine/adc: Update adc module to follow v1.0.0 nrfx API.

* nrf/modules/machine/spi: Implement init and deinit functions

Extending SPI objects with a config member such that
configuration can be kept between new() and init().

Moving initialization done in new() to common init
function shared between the module functions.

If SPI is already configured, the SPI peripheral will
be uninitialized before initalized again.

Adding logic to handle initialization of polarity and
phase. As well, updating default speed to 1M from 500K.

* nrf/modules/machine: Removing unused nrfx includes in machine module header files
This commit is contained in:
glennrub 2018-03-28 00:35:14 +02:00 committed by Damien George
parent 62931398d7
commit 002f7d1ad7
119 changed files with 1865 additions and 46658 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
.gitmodules vendored
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@ -15,3 +15,6 @@
path = lib/stm32lib
url = https://github.com/micropython/stm32lib
branch = work-F4-1.13.1+F7-1.5.0+L4-1.3.0
[submodule "lib/nrfx"]
path = lib/nrfx
url = https://github.com/NordicSemiconductor/nrfx.git

1
lib/nrfx Submodule

@ -0,0 +1 @@
Subproject commit cf78ebfea1719d85cf4018fe6c08cc73fe5ec719

73
ports/nrf/Makefile
View File

@ -41,16 +41,10 @@ MPY_TOOL = ../../tools/mpy-tool.py
CROSS_COMPILE = arm-none-eabi-
MCU_VARIANT_UPPER = $(shell echo $(MCU_VARIANT) | tr '[:lower:]' '[:upper:]')
INC += -I.
INC += -I../..
INC += -I$(BUILD)
INC += -I./../../lib/cmsis/inc
INC += -I./device
INC += -I./device/$(MCU_VARIANT)
INC += -I./hal
INC += -I./hal/$(MCU_VARIANT)
INC += -I./modules/machine
INC += -I./modules/ubluepy
INC += -I./modules/music
@ -59,8 +53,29 @@ INC += -I./modules/ble
INC += -I../../lib/mp-readline
INC += -I./drivers/bluetooth
INC += -I./drivers
INC += -I../../lib/nrfx/
INC += -I../../lib/nrfx/drivers
INC += -I../../lib/nrfx/drivers/include
INC += -I../../lib/nrfx/mdk
INC += -I../../lib/nrfx/hal
NRF_DEFINES += -D$(MCU_VARIANT_UPPER)
MCU_VARIANT_UPPER = $(shell echo $(MCU_VARIANT) | tr '[:lower:]' '[:upper:]')
MCU_SUB_VARIANT_UPPER = $(shell echo $(MCU_SUB_VARIANT) | tr '[:lower:]' '[:upper:]')
# Figure out correct system file to use base on chip sub-variant name.
SYSTEM_C_SRC :=
ifeq ($(MCU_SUB_VARIANT),nrf51822)
SYSTEM_C_SRC += $(addprefix lib/nrfx/mdk/, system_nrf51.c)
NRF_DEFINES += -D$(MCU_VARIANT_UPPER)
else ifeq ($(MCU_SUB_VARIANT),nrf52832)
SYSTEM_C_SRC += $(addprefix lib/nrfx/mdk/, system_nrf52.c)
NRF_DEFINES += -D$(MCU_VARIANT_UPPER)
else ifeq ($(MCU_SUB_VARIANT),nrf52840)
SYSTEM_C_SRC += $(addprefix lib/nrfx/mdk/, system_nrf52840.c)
# Do not pass MCU_VARIANT_UPPER flag, as NRF52 defines NRF52832 only.
endif
NRF_DEFINES += -D$(MCU_SUB_VARIANT_UPPER)
NRF_DEFINES += -DCONFIG_GPIO_AS_PINRESET
CFLAGS_CORTEX_M = -mthumb -mabi=aapcs -fsingle-precision-constant -Wdouble-promotion
@ -140,28 +155,22 @@ SRC_LIB += $(addprefix lib/,\
oofatfs/option/unicode.c \
)
SRC_HAL = $(addprefix hal/,\
hal_uart.c \
hal_uarte.c \
hal_spi.c \
hal_spie.c \
hal_time.c \
hal_rtc.c \
hal_timer.c \
hal_twi.c \
hal_adc.c \
hal_adce.c \
hal_temp.c \
hal_gpio.c \
hal_rng.c \
hal_nvmc.c \
SRC_NRFX += $(addprefix lib/nrfx/drivers/src/,\
prs/nrfx_prs.c \
nrfx_uart.c \
nrfx_adc.c \
nrfx_saadc.c \
nrfx_rng.c \
nrfx_twi.c \
nrfx_spi.c \
nrfx_rtc.c \
nrfx_timer.c \
nrfx_pwm.c \
)
ifeq ($(MCU_VARIANT), nrf52)
SRC_HAL += $(addprefix hal/,\
hal_pwm.c \
SRC_NRFX_HAL += $(addprefix lib/nrfx/hal/,\
nrf_nvmc.c \
)
endif
SRC_C += \
main.c \
@ -170,6 +179,7 @@ SRC_C += \
gccollect.c \
pin_named_pins.c \
fatfs_port.c \
drivers/flash.c \
drivers/softpwm.c \
drivers/ticker.c \
drivers/bluetooth/ble_drv.c \
@ -183,7 +193,7 @@ DRIVERS_SRC_C += $(addprefix modules/,\
machine/adc.c \
machine/pin.c \
machine/timer.c \
machine/rtc.c \
machine/rtcounter.c \
machine/pwm.c \
machine/led.c \
machine/temp.c \
@ -207,9 +217,10 @@ DRIVERS_SRC_C += $(addprefix modules/,\
random/modrandom.c \
)
# Custom micropython startup file with smaller interrupt vector table
# than the file provided in nrfx.
SRC_C += \
device/$(MCU_VARIANT)/system_$(MCU_SUB_VARIANT).c \
device/$(MCU_VARIANT)/startup_$(MCU_SUB_VARIANT).c \
device/startup_$(MCU_SUB_VARIANT).c \
ifneq ($(FROZEN_MPY_DIR),)
FROZEN_MPY_PY_FILES := $(shell find -L $(FROZEN_MPY_DIR) -type f -name '*.py')
@ -218,8 +229,10 @@ endif
OBJ += $(PY_O) $(addprefix $(BUILD)/, $(SRC_C:.c=.o))
OBJ += $(addprefix $(BUILD)/, $(SRC_LIB:.c=.o))
OBJ += $(addprefix $(BUILD)/, $(SRC_HAL:.c=.o))
OBJ += $(addprefix $(BUILD)/, $(SRC_NRFX:.c=.o))
OBJ += $(addprefix $(BUILD)/, $(SRC_NRFX_HAL:.c=.o))
OBJ += $(addprefix $(BUILD)/, $(DRIVERS_SRC_C:.c=.o))
OBJ += $(addprefix $(BUILD)/, $(SYSTEM_C_SRC:.c=.o))
OBJ += $(BUILD)/pins_gen.o
$(BUILD)/$(FATFS_DIR)/ff.o: COPT += -Os

2
ports/nrf/boards/arduino_primo/mpconfigboard.h
View File

@ -35,7 +35,7 @@
#define MICROPY_PY_MACHINE_HW_PWM (1)
#define MICROPY_PY_MACHINE_HW_SPI (1)
#define MICROPY_PY_MACHINE_TIMER (1)
#define MICROPY_PY_MACHINE_RTC (1)
#define MICROPY_PY_MACHINE_RTCOUNTER (1)
#define MICROPY_PY_MACHINE_I2C (1)
#define MICROPY_PY_MACHINE_ADC (1)
#define MICROPY_PY_MACHINE_TEMP (1)

18
ports/nrf/boards/arduino_primo/nrf52_hal_conf.h
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@ -1,18 +0,0 @@
#ifndef NRF52_HAL_CONF_H__
#define NRF52_HAL_CONF_H__
#define HAL_UART_MODULE_ENABLED
#define HAL_SPI_MODULE_ENABLED
#define HAL_TIME_MODULE_ENABLED
#define HAL_PWM_MODULE_ENABLED
#define HAL_RTC_MODULE_ENABLED
#define HAL_TIMER_MODULE_ENABLED
#define HAL_TWI_MODULE_ENABLED
#define HAL_ADCE_MODULE_ENABLED
#define HAL_TEMP_MODULE_ENABLED
#define HAL_RNG_MODULE_ENABLED
// #define HAL_UARTE_MODULE_ENABLED
// #define HAL_SPIE_MODULE_ENABLED
// #define HAL_TWIE_MODULE_ENABLED
#endif // NRF52_HAL_CONF_H__

2
ports/nrf/boards/dvk_bl652/mpconfigboard.h
View File

@ -34,7 +34,7 @@
#define MICROPY_PY_MACHINE_PWM (1)
#define MICROPY_PY_MACHINE_HW_SPI (1)
#define MICROPY_PY_MACHINE_TIMER (1)
#define MICROPY_PY_MACHINE_RTC (1)
#define MICROPY_PY_MACHINE_RTCOUNTER (1)
#define MICROPY_PY_MACHINE_I2C (1)
#define MICROPY_PY_MACHINE_ADC (1)
#define MICROPY_PY_MACHINE_TEMP (1)

18
ports/nrf/boards/dvk_bl652/nrf52_hal_conf.h
View File

@ -1,18 +0,0 @@
#ifndef NRF52_HAL_CONF_H__
#define NRF52_HAL_CONF_H__
#define HAL_UART_MODULE_ENABLED
#define HAL_SPI_MODULE_ENABLED
#define HAL_TIME_MODULE_ENABLED
#define HAL_PWM_MODULE_ENABLED
#define HAL_RTC_MODULE_ENABLED
#define HAL_TIMER_MODULE_ENABLED
#define HAL_TWI_MODULE_ENABLED
#define HAL_ADCE_MODULE_ENABLED
#define HAL_TEMP_MODULE_ENABLED
#define HAL_RNG_MODULE_ENABLED
// #define HAL_UARTE_MODULE_ENABLED
// #define HAL_SPIE_MODULE_ENABLED
// #define HAL_TWIE_MODULE_ENABLED
#endif // NRF52_HAL_CONF_H__

2
ports/nrf/boards/feather52/mpconfigboard.h
View File

@ -34,7 +34,7 @@
#define MICROPY_PY_MACHINE_HW_PWM (1)
#define MICROPY_PY_MACHINE_HW_SPI (1)
#define MICROPY_PY_MACHINE_TIMER (1)
#define MICROPY_PY_MACHINE_RTC (1)
#define MICROPY_PY_MACHINE_RTCOUNTER (1)
#define MICROPY_PY_MACHINE_I2C (1)
#define MICROPY_PY_MACHINE_ADC (1)
#define MICROPY_PY_MACHINE_TEMP (1)

18
ports/nrf/boards/feather52/nrf52_hal_conf.h
View File

@ -1,18 +0,0 @@
#ifndef NRF52_HAL_CONF_H__
#define NRF52_HAL_CONF_H__
#define HAL_UART_MODULE_ENABLED
#define HAL_SPI_MODULE_ENABLED
#define HAL_TIME_MODULE_ENABLED
#define HAL_PWM_MODULE_ENABLED
#define HAL_RTC_MODULE_ENABLED
#define HAL_TIMER_MODULE_ENABLED
#define HAL_TWI_MODULE_ENABLED
#define HAL_ADCE_MODULE_ENABLED
#define HAL_TEMP_MODULE_ENABLED
#define HAL_RNG_MODULE_ENABLED
// #define HAL_UARTE_MODULE_ENABLED
// #define HAL_SPIE_MODULE_ENABLED
// #define HAL_TWIE_MODULE_ENABLED
#endif // NRF52_HAL_CONF_H__

18
ports/nrf/boards/microbit/modules/microbitdisplay.c
View File

@ -25,10 +25,10 @@
*/
#include <string.h>
#include "hal_gpio.h"
#include "py/obj.h"
#include "py/runtime.h"
#include "py/gc.h"
#include "nrf_gpio.h"
#include "microbitimage.h"
#include "microbitdisplay.h"
#include "iters.h"
@ -188,9 +188,9 @@ static const DisplayPoint display_map[COLUMN_COUNT][ROW_COUNT] = {
static inline void displaySetPinsForRow(microbit_display_obj_t * p_display, uint8_t brightness) {
if (brightness == 0) {
hal_gpio_out_clear(0, COLUMN_PINS_MASK & ~p_display->pins_for_brightness[brightness]);
nrf_gpio_port_out_clear(NRF_GPIO, COLUMN_PINS_MASK & ~p_display->pins_for_brightness[brightness]);
} else {
hal_gpio_out_set(0, p_display->pins_for_brightness[brightness]);
nrf_gpio_pin_set(p_display->pins_for_brightness[brightness]);
}
}
@ -219,9 +219,9 @@ static inline void displaySetPinsForRow(microbit_display_obj_t * p_display, uint
*/
static void displayAdvanceRow(microbit_display_obj_t * p_display) {
/* Clear all of the column bits */
hal_gpio_out_set(0, COLUMN_PINS_MASK);
nrf_gpio_port_out_set(NRF_GPIO, COLUMN_PINS_MASK);
/* Clear the strobe bit for this row */
hal_gpio_pin_clear(0, p_display->strobe_row + MIN_ROW_PIN);
nrf_gpio_pin_clear(p_display->strobe_row + MIN_ROW_PIN);
/* Move to the next row. Before this, "this row" refers to the row
* manipulated by the previous invocation of this function. After this,
@ -247,9 +247,9 @@ static void displayAdvanceRow(microbit_display_obj_t * p_display) {
(void)brightness;
}
/* Enable the strobe bit for this row */
hal_gpio_pin_set(0, p_display->strobe_row + MIN_ROW_PIN);
nrf_gpio_pin_set(p_display->strobe_row + MIN_ROW_PIN);
/* Enable the column bits for all pins that need to be on. */
hal_gpio_out_clear(0, p_display->pins_for_brightness[MAX_BRIGHTNESS]);
nrf_gpio_port_out_clear(NRF_GPIO, p_display->pins_for_brightness[MAX_BRIGHTNESS]);
}
static const uint16_t render_timings[] =
@ -458,7 +458,7 @@ mp_obj_t microbit_display_off_func(mp_obj_t obj) {
self->active = false;
/* Disable the row strobes, allowing the columns to be used freely for
* GPIO. */
hal_gpio_out_clear(0, ROW_PINS_MASK);
nrf_gpio_port_out_clear(0, ROW_PINS_MASK);
/* Free pins for other uses */
/*
microbit_obj_pin_free(&microbit_p3_obj);
@ -571,6 +571,6 @@ microbit_display_obj_t microbit_display_obj = {
void microbit_display_init(void) {
// Set pins as output.
for (int i = MIN_COLUMN_PIN; i <= MAX_ROW_PIN; i++) {
hal_gpio_cfg_pin(0, i, HAL_GPIO_MODE_OUTPUT, HAL_GPIO_PULL_DOWN);
nrf_gpio_cfg_output(i);
}
}

8
ports/nrf/boards/microbit/modules/modmicrobit.c
View File

@ -32,7 +32,7 @@
#include "microbitimage.h"
#include "softpwm.h"
#include "ticker.h"
#include "hal_temp.h"
#include "nrf_temp.h"
extern uint32_t ticks;
@ -97,11 +97,11 @@ STATIC mp_obj_t microbit_panic(mp_uint_t n_args, const mp_obj_t *args) {
MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(microbit_panic_obj, 0, 1, microbit_panic);
STATIC mp_obj_t microbit_temperature(void) {
int temp = hal_temp_read();
int temp = nrf_temp_read();
#if MICROPY_FLOAT_IMPL == MICROPY_FLOAT_IMPL_FLOAT
return mp_obj_new_float(temp);
return mp_obj_new_float(temp / 4);
#else
return mp_obj_new_int(temp);
return mp_obj_new_int(temp / 4);
#endif
}
MP_DEFINE_CONST_FUN_OBJ_0(microbit_temperature_obj, microbit_temperature);

3
ports/nrf/boards/microbit/mpconfigboard.h
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@ -35,10 +35,11 @@
#define MICROPY_PY_MACHINE_SOFT_PWM (1)
#define MICROPY_PY_MACHINE_HW_SPI (1)
#define MICROPY_PY_MACHINE_TIMER (1)
#define MICROPY_PY_MACHINE_RTC (1)
#define MICROPY_PY_MACHINE_RTCOUNTER (1)
#define MICROPY_PY_MACHINE_I2C (1)
#define MICROPY_PY_MACHINE_ADC (1)
#define MICROPY_PY_MACHINE_TEMP (1)
#define MICROPY_PY_HW_RNG (1)
#define MICROPY_HW_HAS_LED (0)
#define MICROPY_HW_HAS_SWITCH (0)

14
ports/nrf/boards/microbit/nrf51_hal_conf.h
View File

@ -1,14 +0,0 @@
#ifndef NRF51_HAL_CONF_H__
#define NRF51_HAL_CONF_H__
#define HAL_UART_MODULE_ENABLED
#define HAL_SPI_MODULE_ENABLED
#define HAL_TIME_MODULE_ENABLED
#define HAL_RTC_MODULE_ENABLED
#define HAL_TIMER_MODULE_ENABLED
#define HAL_TWI_MODULE_ENABLED
#define HAL_ADC_MODULE_ENABLED
#define HAL_TEMP_MODULE_ENABLED
#define HAL_RNG_MODULE_ENABLED
#endif // NRF51_HAL_CONF_H__

2
ports/nrf/boards/pca10000/mpconfigboard.h
View File

@ -33,7 +33,7 @@
#define MICROPY_PY_MACHINE_UART (1)
#define MICROPY_PY_MACHINE_HW_SPI (0)
#define MICROPY_PY_MACHINE_TIMER (1)
#define MICROPY_PY_MACHINE_RTC (1)
#define MICROPY_PY_MACHINE_RTCOUNTER (1)
#define MICROPY_PY_MACHINE_I2C (0)
#define MICROPY_PY_MACHINE_ADC (0)
#define MICROPY_PY_MACHINE_TEMP (1)

11
ports/nrf/boards/pca10000/nrf51_hal_conf.h
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@ -1,11 +0,0 @@
#ifndef NRF51_HAL_CONF_H__
#define NRF51_HAL_CONF_H__
#define HAL_UART_MODULE_ENABLED
#define HAL_RTC_MODULE_ENABLED
#define HAL_TIMER_MODULE_ENABLED
#define HAL_TIME_MODULE_ENABLED
#define HAL_TEMP_MODULE_ENABLED
#define HAL_RNG_MODULE_ENABLED
#endif // NRF51_HAL_CONF_H__

2
ports/nrf/boards/pca10001/mpconfigboard.h
View File

@ -33,7 +33,7 @@
#define MICROPY_PY_MACHINE_UART (1)
#define MICROPY_PY_MACHINE_HW_SPI (0)
#define MICROPY_PY_MACHINE_TIMER (1)
#define MICROPY_PY_MACHINE_RTC (1)
#define MICROPY_PY_MACHINE_RTCOUNTER (1)
#define MICROPY_PY_MACHINE_I2C (1)
#define MICROPY_PY_MACHINE_ADC (1)
#define MICROPY_PY_MACHINE_TEMP (1)

14
ports/nrf/boards/pca10001/nrf51_hal_conf.h
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@ -1,14 +0,0 @@
#ifndef NRF51_HAL_CONF_H__
#define NRF51_HAL_CONF_H__
#define HAL_UART_MODULE_ENABLED
#define HAL_SPI_MODULE_ENABLED
#define HAL_TIME_MODULE_ENABLED
#define HAL_RTC_MODULE_ENABLED
#define HAL_TIMER_MODULE_ENABLED
#define HAL_TWI_MODULE_ENABLED
#define HAL_ADC_MODULE_ENABLED
#define HAL_TEMP_MODULE_ENABLED
#define HAL_RNG_MODULE_ENABLED
#endif // NRF51_HAL_CONF_H__

2
ports/nrf/boards/pca10028/mpconfigboard.h
View File

@ -33,7 +33,7 @@
#define MICROPY_PY_MACHINE_UART (1)
#define MICROPY_PY_MACHINE_HW_SPI (1)
#define MICROPY_PY_MACHINE_TIMER (1)
#define MICROPY_PY_MACHINE_RTC (1)
#define MICROPY_PY_MACHINE_RTCOUNTER (1)
#define MICROPY_PY_MACHINE_I2C (1)
#define MICROPY_PY_MACHINE_ADC (1)
#define MICROPY_PY_MACHINE_TEMP (1)

14
ports/nrf/boards/pca10028/nrf51_hal_conf.h
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@ -1,14 +0,0 @@
#ifndef NRF51_HAL_CONF_H__
#define NRF51_HAL_CONF_H__
#define HAL_UART_MODULE_ENABLED
#define HAL_SPI_MODULE_ENABLED
#define HAL_TIME_MODULE_ENABLED
#define HAL_RTC_MODULE_ENABLED
#define HAL_TIMER_MODULE_ENABLED
#define HAL_TWI_MODULE_ENABLED
#define HAL_ADC_MODULE_ENABLED
#define HAL_TEMP_MODULE_ENABLED
#define HAL_RNG_MODULE_ENABLED
#endif // NRF51_HAL_CONF_H__

2
ports/nrf/boards/pca10031/mpconfigboard.h
View File

@ -33,7 +33,7 @@
#define MICROPY_PY_MACHINE_UART (1)
#define MICROPY_PY_MACHINE_HW_SPI (1)
#define MICROPY_PY_MACHINE_TIMER (1)
#define MICROPY_PY_MACHINE_RTC (1)
#define MICROPY_PY_MACHINE_RTCOUNTER (1)
#define MICROPY_PY_MACHINE_I2C (1)
#define MICROPY_PY_MACHINE_ADC (1)
#define MICROPY_PY_MACHINE_TEMP (1)

14
ports/nrf/boards/pca10031/nrf51_hal_conf.h
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@ -1,14 +0,0 @@
#ifndef NRF51_HAL_CONF_H__
#define NRF51_HAL_CONF_H__
#define HAL_UART_MODULE_ENABLED
#define HAL_SPI_MODULE_ENABLED
#define HAL_TIME_MODULE_ENABLED
#define HAL_RTC_MODULE_ENABLED
#define HAL_TIMER_MODULE_ENABLED
#define HAL_TWI_MODULE_ENABLED
#define HAL_ADC_MODULE_ENABLED
#define HAL_TEMP_MODULE_ENABLED
#define HAL_RNG_MODULE_ENABLED
#endif // NRF51_HAL_CONF_H__

3
ports/nrf/boards/pca10040/mpconfigboard.h
View File

@ -34,10 +34,11 @@
#define MICROPY_PY_MACHINE_HW_PWM (1)
#define MICROPY_PY_MACHINE_HW_SPI (1)
#define MICROPY_PY_MACHINE_TIMER (1)
#define MICROPY_PY_MACHINE_RTC (1)
#define MICROPY_PY_MACHINE_RTCOUNTER (1)
#define MICROPY_PY_MACHINE_I2C (1)
#define MICROPY_PY_MACHINE_ADC (1)
#define MICROPY_PY_MACHINE_TEMP (1)
#define MICROPY_PY_HW_RNG (1)
#define MICROPY_HW_HAS_LED (1)
#define MICROPY_HW_HAS_SWITCH (0)

18
ports/nrf/boards/pca10040/nrf52_hal_conf.h
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@ -1,18 +0,0 @@
#ifndef NRF52_HAL_CONF_H__
#define NRF52_HAL_CONF_H__
#define HAL_UART_MODULE_ENABLED
#define HAL_SPI_MODULE_ENABLED
#define HAL_TIME_MODULE_ENABLED
#define HAL_PWM_MODULE_ENABLED
#define HAL_RTC_MODULE_ENABLED
#define HAL_TIMER_MODULE_ENABLED
#define HAL_TWI_MODULE_ENABLED
#define HAL_ADCE_MODULE_ENABLED
#define HAL_TEMP_MODULE_ENABLED
#define HAL_RNG_MODULE_ENABLED
// #define HAL_UARTE_MODULE_ENABLED
// #define HAL_SPIE_MODULE_ENABLED
// #define HAL_TWIE_MODULE_ENABLED
#endif // NRF52_HAL_CONF_H__

2
ports/nrf/boards/pca10056/mpconfigboard.h
View File

@ -34,7 +34,7 @@
#define MICROPY_PY_MACHINE_HW_PWM (1)
#define MICROPY_PY_MACHINE_HW_SPI (1)
#define MICROPY_PY_MACHINE_TIMER (1)
#define MICROPY_PY_MACHINE_RTC (1)
#define MICROPY_PY_MACHINE_RTCOUNTER (1)
#define MICROPY_PY_MACHINE_I2C (1)
#define MICROPY_PY_MACHINE_ADC (1)
#define MICROPY_PY_MACHINE_TEMP (1)

18
ports/nrf/boards/pca10056/nrf52_hal_conf.h
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@ -1,18 +0,0 @@
#ifndef NRF52_HAL_CONF_H__
#define NRF52_HAL_CONF_H__
// #define HAL_UART_MODULE_ENABLED
#define HAL_SPI_MODULE_ENABLED
#define HAL_TIME_MODULE_ENABLED
#define HAL_PWM_MODULE_ENABLED
#define HAL_RTC_MODULE_ENABLED
#define HAL_TIMER_MODULE_ENABLED
#define HAL_TWI_MODULE_ENABLED
#define HAL_ADCE_MODULE_ENABLED
#define HAL_TEMP_MODULE_ENABLED
#define HAL_RNG_MODULE_ENABLED
#define HAL_UARTE_MODULE_ENABLED
// #define HAL_SPIE_MODULE_ENABLED
// #define HAL_TWIE_MODULE_ENABLED
#endif // NRF52_HAL_CONF_H__

2
ports/nrf/boards/wt51822_s4at/mpconfigboard.h
View File

@ -35,7 +35,7 @@
#define MICROPY_PY_MACHINE_UART (1)
#define MICROPY_PY_MACHINE_HW_SPI (1)
#define MICROPY_PY_MACHINE_TIMER (1)
#define MICROPY_PY_MACHINE_RTC (1)
#define MICROPY_PY_MACHINE_RTCOUNTER (1)
#define MICROPY_PY_MACHINE_I2C (1)
#define MICROPY_PY_MACHINE_ADC (1)
#define MICROPY_PY_MACHINE_TEMP (1)

144
ports/nrf/device/compiler_abstraction.h
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@ -1,144 +0,0 @@
/* Copyright (c) 2016, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* * Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* * Neither the name of Nordic Semiconductor ASA nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifndef _COMPILER_ABSTRACTION_H
#define _COMPILER_ABSTRACTION_H
/*lint ++flb "Enter library region" */
#if defined ( __CC_ARM )
#ifndef __ASM
#define __ASM __asm
#endif
#ifndef __INLINE
#define __INLINE __inline
#endif
#ifndef __WEAK
#define __WEAK __weak
#endif
#ifndef __ALIGN
#define __ALIGN(n) __align(n)
#endif
#ifndef __PACKED
#define __PACKED __packed
#endif
#define GET_SP() __current_sp()
#elif defined ( __ICCARM__ )
#ifndef __ASM
#define __ASM __asm
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __WEAK
#define __WEAK __weak
#endif
#ifndef __ALIGN
#define STRING_PRAGMA(x) _Pragma(#x)
#define __ALIGN(n) STRING_PRAGMA(data_alignment = n)
#endif
#ifndef __PACKED
#define __PACKED __packed
#endif
#define GET_SP() __get_SP()
#elif defined ( __GNUC__ )
#ifndef __ASM
#define __ASM __asm
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __WEAK
#define __WEAK __attribute__((weak))
#endif
#ifndef __ALIGN
#define __ALIGN(n) __attribute__((aligned(n)))
#endif
#ifndef __PACKED
#define __PACKED __attribute__((packed))
#endif
#define GET_SP() gcc_current_sp()
static inline unsigned int gcc_current_sp(void)
{
register unsigned sp __ASM("sp");
return sp;
}
#elif defined ( __TASKING__ )
#ifndef __ASM
#define __ASM __asm
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __WEAK
#define __WEAK __attribute__((weak))
#endif
#ifndef __ALIGN
#define __ALIGN(n) __align(n)
#endif
/* Not defined for TASKING. */
#ifndef __PACKED
#define __PACKED
#endif
#define GET_SP() __get_MSP()
#endif
/*lint --flb "Leave library region" */
#endif

77
ports/nrf/device/nrf.h
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@ -1,77 +0,0 @@
/* Copyright (c) 2016, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* * Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* * Neither the name of Nordic Semiconductor ASA nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifndef NRF_H
#define NRF_H
/* MDK version */
#define MDK_MAJOR_VERSION 8
#define MDK_MINOR_VERSION 11
#define MDK_MICRO_VERSION 1
/* Define NRF52_SERIES for common use in nRF52 series devices. */
#if defined (NRF52832_XXAA) || defined (NRF52840_XXAA)
#define NRF52_SERIES
#endif
#if defined(_WIN32)
/* Do not include nrf specific files when building for PC host */
#elif defined(__unix)
/* Do not include nrf specific files when building for PC host */
#elif defined(__APPLE__)
/* Do not include nrf specific files when building for PC host */
#else
/* Device selection for device includes. */
#if defined (NRF51)
#include "nrf51.h"
#include "nrf51_bitfields.h"
#include "nrf51_deprecated.h"
#elif defined (NRF52840_XXAA)
#include "nrf52840.h"
#include "nrf52840_bitfields.h"
#include "nrf51_to_nrf52840.h"
#include "nrf52_to_nrf52840.h"
#elif defined (NRF52832_XXAA)
#include "nrf52.h"
#include "nrf52_bitfields.h"
#include "nrf51_to_nrf52.h"
#include "nrf52_name_change.h"
#else
#error "Device must be defined. See nrf.h."
#endif /* NRF51, NRF52832_XXAA, NRF52840_XXAA */
#include "compiler_abstraction.h"
#endif /* _WIN32 || __unix || __APPLE__ */
#endif /* NRF_H */

1193
ports/nrf/device/nrf51/nrf51.h
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6129
ports/nrf/device/nrf51/nrf51_bitfields.h
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File diff suppressed because it is too large Load Diff

440
ports/nrf/device/nrf51/nrf51_deprecated.h
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@ -1,440 +0,0 @@
/* Copyright (c) 2016, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* * Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* * Neither the name of Nordic Semiconductor ASA nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifndef NRF51_DEPRECATED_H
#define NRF51_DEPRECATED_H
/*lint ++flb "Enter library region */
/* This file is given to prevent your SW from not compiling with the updates made to nrf51.h and
* nrf51_bitfields.h. The macros defined in this file were available previously. Do not use these
* macros on purpose. Use the ones defined in nrf51.h and nrf51_bitfields.h instead.
*/
/* NVMC */
/* The register ERASEPROTECTEDPAGE is called ERASEPCR0 in the documentation. */
#define ERASEPROTECTEDPAGE ERASEPCR0
/* LPCOMP */
/* The interrupt ISR was renamed. Adding old name to the macros. */
#define LPCOMP_COMP_IRQHandler LPCOMP_IRQHandler
#define LPCOMP_COMP_IRQn LPCOMP_IRQn
/* Corrected typo in RESULT register. */
#define LPCOMP_RESULT_RESULT_Bellow LPCOMP_RESULT_RESULT_Below
/* MPU */
/* The field MPU.PERR0.LPCOMP_COMP was renamed. Added into deprecated in case somebody was using the macros defined for it. */
#define MPU_PERR0_LPCOMP_COMP_Pos MPU_PERR0_LPCOMP_Pos
#define MPU_PERR0_LPCOMP_COMP_Msk MPU_PERR0_LPCOMP_Msk
#define MPU_PERR0_LPCOMP_COMP_InRegion1 MPU_PERR0_LPCOMP_InRegion1
#define MPU_PERR0_LPCOMP_COMP_InRegion0 MPU_PERR0_LPCOMP_InRegion0
/* POWER */
/* The field POWER.RAMON.OFFRAM3 was eliminated. Added into deprecated in case somebody was using the macros defined for it. */
#define POWER_RAMON_OFFRAM3_Pos (19UL)
#define POWER_RAMON_OFFRAM3_Msk (0x1UL << POWER_RAMON_OFFRAM3_Pos)
#define POWER_RAMON_OFFRAM3_RAM3Off (0UL)
#define POWER_RAMON_OFFRAM3_RAM3On (1UL)
/* The field POWER.RAMON.OFFRAM2 was eliminated. Added into deprecated in case somebody was using the macros defined for it. */
#define POWER_RAMON_OFFRAM2_Pos (18UL)
#define POWER_RAMON_OFFRAM2_Msk (0x1UL << POWER_RAMON_OFFRAM2_Pos)
#define POWER_RAMON_OFFRAM2_RAM2Off (0UL)
#define POWER_RAMON_OFFRAM2_RAM2On (1UL)
/* The field POWER.RAMON.ONRAM3 was eliminated. Added into deprecated in case somebody was using the macros defined for it. */
#define POWER_RAMON_ONRAM3_Pos (3UL)
#define POWER_RAMON_ONRAM3_Msk (0x1UL << POWER_RAMON_ONRAM3_Pos)
#define POWER_RAMON_ONRAM3_RAM3Off (0UL)
#define POWER_RAMON_ONRAM3_RAM3On (1UL)
/* The field POWER.RAMON.ONRAM2 was eliminated. Added into deprecated in case somebody was using the macros defined for it. */
#define POWER_RAMON_ONRAM2_Pos (2UL)
#define POWER_RAMON_ONRAM2_Msk (0x1UL << POWER_RAMON_ONRAM2_Pos)
#define POWER_RAMON_ONRAM2_RAM2Off (0UL)
#define POWER_RAMON_ONRAM2_RAM2On (1UL)
/* RADIO */
/* The enumerated value RADIO.TXPOWER.TXPOWER.Neg40dBm was renamed. Added into deprecated with the new macro name. */
#define RADIO_TXPOWER_TXPOWER_Neg40dBm RADIO_TXPOWER_TXPOWER_Neg30dBm
/* The name of the field SKIPADDR was corrected. Old macros added for compatibility. */
#define RADIO_CRCCNF_SKIP_ADDR_Pos RADIO_CRCCNF_SKIPADDR_Pos
#define RADIO_CRCCNF_SKIP_ADDR_Msk RADIO_CRCCNF_SKIPADDR_Msk
#define RADIO_CRCCNF_SKIP_ADDR_Include RADIO_CRCCNF_SKIPADDR_Include
#define RADIO_CRCCNF_SKIP_ADDR_Skip RADIO_CRCCNF_SKIPADDR_Skip
/* The name of the field PLLLOCK was corrected. Old macros added for compatibility. */
#define RADIO_TEST_PLL_LOCK_Pos RADIO_TEST_PLLLOCK_Pos
#define RADIO_TEST_PLL_LOCK_Msk RADIO_TEST_PLLLOCK_Msk
#define RADIO_TEST_PLL_LOCK_Disabled RADIO_TEST_PLLLOCK_Disabled
#define RADIO_TEST_PLL_LOCK_Enabled RADIO_TEST_PLLLOCK_Enabled
/* The name of the field CONSTCARRIER was corrected. Old macros added for compatibility. */
#define RADIO_TEST_CONST_CARRIER_Pos RADIO_TEST_CONSTCARRIER_Pos
#define RADIO_TEST_CONST_CARRIER_Msk RADIO_TEST_CONSTCARRIER_Msk
#define RADIO_TEST_CONST_CARRIER_Disabled RADIO_TEST_CONSTCARRIER_Disabled
#define RADIO_TEST_CONST_CARRIER_Enabled RADIO_TEST_CONSTCARRIER_Enabled
/* FICR */
/* The registers FICR.SIZERAMBLOCK0, FICR.SIZERAMBLOCK1, FICR.SIZERAMBLOCK2 and FICR.SIZERAMBLOCK3 were renamed into an array. */
#define SIZERAMBLOCK0 SIZERAMBLOCKS
#define SIZERAMBLOCK1 SIZERAMBLOCKS
#define SIZERAMBLOCK2 SIZERAMBLOCK[2] /*!< Note that this macro will disapear when SIZERAMBLOCK array is eliminated. SIZERAMBLOCK is a deprecated array. */
#define SIZERAMBLOCK3 SIZERAMBLOCK[3] /*!< Note that this macro will disapear when SIZERAMBLOCK array is eliminated. SIZERAMBLOCK is a deprecated array. */
/* The registers FICR.DEVICEID0 and FICR.DEVICEID1 were renamed into an array. */
#define DEVICEID0 DEVICEID[0]
#define DEVICEID1 DEVICEID[1]
/* The registers FICR.ER0, FICR.ER1, FICR.ER2 and FICR.ER3 were renamed into an array. */
#define ER0 ER[0]
#define ER1 ER[1]
#define ER2 ER[2]
#define ER3 ER[3]
/* The registers FICR.IR0, FICR.IR1, FICR.IR2 and FICR.IR3 were renamed into an array. */
#define IR0 IR[0]
#define IR1 IR[1]
#define IR2 IR[2]
#define IR3 IR[3]
/* The registers FICR.DEVICEADDR0 and FICR.DEVICEADDR1 were renamed into an array. */
#define DEVICEADDR0 DEVICEADDR[0]
#define DEVICEADDR1 DEVICEADDR[1]
/* PPI */
/* The tasks PPI.TASKS_CHGxEN and PPI.TASKS_CHGxDIS were renamed into an array of structs. */
#define TASKS_CHG0EN TASKS_CHG[0].EN
#define TASKS_CHG0DIS TASKS_CHG[0].DIS
#define TASKS_CHG1EN TASKS_CHG[1].EN
#define TASKS_CHG1DIS TASKS_CHG[1].DIS
#define TASKS_CHG2EN TASKS_CHG[2].EN
#define TASKS_CHG2DIS TASKS_CHG[2].DIS
#define TASKS_CHG3EN TASKS_CHG[3].EN
#define TASKS_CHG3DIS TASKS_CHG[3].DIS
/* The registers PPI.CHx_EEP and PPI.CHx_TEP were renamed into an array of structs. */
#define CH0_EEP CH[0].EEP
#define CH0_TEP CH[0].TEP
#define CH1_EEP CH[1].EEP
#define CH1_TEP CH[1].TEP
#define CH2_EEP CH[2].EEP
#define CH2_TEP CH[2].TEP
#define CH3_EEP CH[3].EEP
#define CH3_TEP CH[3].TEP
#define CH4_EEP CH[4].EEP
#define CH4_TEP CH[4].TEP
#define CH5_EEP CH[5].EEP
#define CH5_TEP CH[5].TEP
#define CH6_EEP CH[6].EEP
#define CH6_TEP CH[6].TEP
#define CH7_EEP CH[7].EEP
#define CH7_TEP CH[7].TEP
#define CH8_EEP CH[8].EEP
#define CH8_TEP CH[8].TEP
#define CH9_EEP CH[9].EEP
#define CH9_TEP CH[9].TEP
#define CH10_EEP CH[10].EEP
#define CH10_TEP CH[10].TEP
#define CH11_EEP CH[11].EEP
#define CH11_TEP CH[11].TEP
#define CH12_EEP CH[12].EEP
#define CH12_TEP CH[12].TEP
#define CH13_EEP CH[13].EEP
#define CH13_TEP CH[13].TEP
#define CH14_EEP CH[14].EEP
#define CH14_TEP CH[14].TEP
#define CH15_EEP CH[15].EEP
#define CH15_TEP CH[15].TEP
/* The registers PPI.CHG0, PPI.CHG1, PPI.CHG2 and PPI.CHG3 were renamed into an array. */
#define CHG0 CHG[0]
#define CHG1 CHG[1]
#define CHG2 CHG[2]
#define CHG3 CHG[3]
/* All bitfield macros for the CHGx registers therefore changed name. */
#define PPI_CHG0_CH15_Pos PPI_CHG_CH15_Pos
#define PPI_CHG0_CH15_Msk PPI_CHG_CH15_Msk
#define PPI_CHG0_CH15_Excluded PPI_CHG_CH15_Excluded
#define PPI_CHG0_CH15_Included PPI_CHG_CH15_Included
#define PPI_CHG0_CH14_Pos PPI_CHG_CH14_Pos
#define PPI_CHG0_CH14_Msk PPI_CHG_CH14_Msk
#define PPI_CHG0_CH14_Excluded PPI_CHG_CH14_Excluded
#define PPI_CHG0_CH14_Included PPI_CHG_CH14_Included
#define PPI_CHG0_CH13_Pos PPI_CHG_CH13_Pos
#define PPI_CHG0_CH13_Msk PPI_CHG_CH13_Msk
#define PPI_CHG0_CH13_Excluded PPI_CHG_CH13_Excluded
#define PPI_CHG0_CH13_Included PPI_CHG_CH13_Included
#define PPI_CHG0_CH12_Pos PPI_CHG_CH12_Pos
#define PPI_CHG0_CH12_Msk PPI_CHG_CH12_Msk
#define PPI_CHG0_CH12_Excluded PPI_CHG_CH12_Excluded
#define PPI_CHG0_CH12_Included PPI_CHG_CH12_Included
#define PPI_CHG0_CH11_Pos PPI_CHG_CH11_Pos
#define PPI_CHG0_CH11_Msk PPI_CHG_CH11_Msk
#define PPI_CHG0_CH11_Excluded PPI_CHG_CH11_Excluded
#define PPI_CHG0_CH11_Included PPI_CHG_CH11_Included
#define PPI_CHG0_CH10_Pos PPI_CHG_CH10_Pos
#define PPI_CHG0_CH10_Msk PPI_CHG_CH10_Msk
#define PPI_CHG0_CH10_Excluded PPI_CHG_CH10_Excluded
#define PPI_CHG0_CH10_Included PPI_CHG_CH10_Included
#define PPI_CHG0_CH9_Pos PPI_CHG_CH9_Pos
#define PPI_CHG0_CH9_Msk PPI_CHG_CH9_Msk
#define PPI_CHG0_CH9_Excluded PPI_CHG_CH9_Excluded
#define PPI_CHG0_CH9_Included PPI_CHG_CH9_Included
#define PPI_CHG0_CH8_Pos PPI_CHG_CH8_Pos
#define PPI_CHG0_CH8_Msk PPI_CHG_CH8_Msk
#define PPI_CHG0_CH8_Excluded PPI_CHG_CH8_Excluded
#define PPI_CHG0_CH8_Included PPI_CHG_CH8_Included
#define PPI_CHG0_CH7_Pos PPI_CHG_CH7_Pos
#define PPI_CHG0_CH7_Msk PPI_CHG_CH7_Msk
#define PPI_CHG0_CH7_Excluded PPI_CHG_CH7_Excluded
#define PPI_CHG0_CH7_Included PPI_CHG_CH7_Included
#define PPI_CHG0_CH6_Pos PPI_CHG_CH6_Pos
#define PPI_CHG0_CH6_Msk PPI_CHG_CH6_Msk
#define PPI_CHG0_CH6_Excluded PPI_CHG_CH6_Excluded
#define PPI_CHG0_CH6_Included PPI_CHG_CH6_Included
#define PPI_CHG0_CH5_Pos PPI_CHG_CH5_Pos
#define PPI_CHG0_CH5_Msk PPI_CHG_CH5_Msk
#define PPI_CHG0_CH5_Excluded PPI_CHG_CH5_Excluded
#define PPI_CHG0_CH5_Included PPI_CHG_CH5_Included
#define PPI_CHG0_CH4_Pos PPI_CHG_CH4_Pos
#define PPI_CHG0_CH4_Msk PPI_CHG_CH4_Msk
#define PPI_CHG0_CH4_Excluded PPI_CHG_CH4_Excluded
#define PPI_CHG0_CH4_Included PPI_CHG_CH4_Included
#define PPI_CHG0_CH3_Pos PPI_CHG_CH3_Pos
#define PPI_CHG0_CH3_Msk PPI_CHG_CH3_Msk
#define PPI_CHG0_CH3_Excluded PPI_CHG_CH3_Excluded
#define PPI_CHG0_CH3_Included PPI_CHG_CH3_Included
#define PPI_CHG0_CH2_Pos PPI_CHG_CH2_Pos
#define PPI_CHG0_CH2_Msk PPI_CHG_CH2_Msk
#define PPI_CHG0_CH2_Excluded PPI_CHG_CH2_Excluded
#define PPI_CHG0_CH2_Included PPI_CHG_CH2_Included
#define PPI_CHG0_CH1_Pos PPI_CHG_CH1_Pos
#define PPI_CHG0_CH1_Msk PPI_CHG_CH1_Msk
#define PPI_CHG0_CH1_Excluded PPI_CHG_CH1_Excluded
#define PPI_CHG0_CH1_Included PPI_CHG_CH1_Included
#define PPI_CHG0_CH0_Pos PPI_CHG_CH0_Pos
#define PPI_CHG0_CH0_Msk PPI_CHG_CH0_Msk
#define PPI_CHG0_CH0_Excluded PPI_CHG_CH0_Excluded
#define PPI_CHG0_CH0_Included PPI_CHG_CH0_Included
#define PPI_CHG1_CH15_Pos PPI_CHG_CH15_Pos
#define PPI_CHG1_CH15_Msk PPI_CHG_CH15_Msk
#define PPI_CHG1_CH15_Excluded PPI_CHG_CH15_Excluded
#define PPI_CHG1_CH15_Included PPI_CHG_CH15_Included
#define PPI_CHG1_CH14_Pos PPI_CHG_CH14_Pos
#define PPI_CHG1_CH14_Msk PPI_CHG_CH14_Msk
#define PPI_CHG1_CH14_Excluded PPI_CHG_CH14_Excluded
#define PPI_CHG1_CH14_Included PPI_CHG_CH14_Included
#define PPI_CHG1_CH13_Pos PPI_CHG_CH13_Pos
#define PPI_CHG1_CH13_Msk PPI_CHG_CH13_Msk
#define PPI_CHG1_CH13_Excluded PPI_CHG_CH13_Excluded
#define PPI_CHG1_CH13_Included PPI_CHG_CH13_Included
#define PPI_CHG1_CH12_Pos PPI_CHG_CH12_Pos
#define PPI_CHG1_CH12_Msk PPI_CHG_CH12_Msk
#define PPI_CHG1_CH12_Excluded PPI_CHG_CH12_Excluded
#define PPI_CHG1_CH12_Included PPI_CHG_CH12_Included
#define PPI_CHG1_CH11_Pos PPI_CHG_CH11_Pos
#define PPI_CHG1_CH11_Msk PPI_CHG_CH11_Msk
#define PPI_CHG1_CH11_Excluded PPI_CHG_CH11_Excluded
#define PPI_CHG1_CH11_Included PPI_CHG_CH11_Included
#define PPI_CHG1_CH10_Pos PPI_CHG_CH10_Pos
#define PPI_CHG1_CH10_Msk PPI_CHG_CH10_Msk
#define PPI_CHG1_CH10_Excluded PPI_CHG_CH10_Excluded
#define PPI_CHG1_CH10_Included PPI_CHG_CH10_Included
#define PPI_CHG1_CH9_Pos PPI_CHG_CH9_Pos
#define PPI_CHG1_CH9_Msk PPI_CHG_CH9_Msk
#define PPI_CHG1_CH9_Excluded PPI_CHG_CH9_Excluded
#define PPI_CHG1_CH9_Included PPI_CHG_CH9_Included
#define PPI_CHG1_CH8_Pos PPI_CHG_CH8_Pos
#define PPI_CHG1_CH8_Msk PPI_CHG_CH8_Msk
#define PPI_CHG1_CH8_Excluded PPI_CHG_CH8_Excluded
#define PPI_CHG1_CH8_Included PPI_CHG_CH8_Included
#define PPI_CHG1_CH7_Pos PPI_CHG_CH7_Pos
#define PPI_CHG1_CH7_Msk PPI_CHG_CH7_Msk
#define PPI_CHG1_CH7_Excluded PPI_CHG_CH7_Excluded
#define PPI_CHG1_CH7_Included PPI_CHG_CH7_Included
#define PPI_CHG1_CH6_Pos PPI_CHG_CH6_Pos
#define PPI_CHG1_CH6_Msk PPI_CHG_CH6_Msk
#define PPI_CHG1_CH6_Excluded PPI_CHG_CH6_Excluded
#define PPI_CHG1_CH6_Included PPI_CHG_CH6_Included
#define PPI_CHG1_CH5_Pos PPI_CHG_CH5_Pos
#define PPI_CHG1_CH5_Msk PPI_CHG_CH5_Msk
#define PPI_CHG1_CH5_Excluded PPI_CHG_CH5_Excluded
#define PPI_CHG1_CH5_Included PPI_CHG_CH5_Included
#define PPI_CHG1_CH4_Pos PPI_CHG_CH4_Pos
#define PPI_CHG1_CH4_Msk PPI_CHG_CH4_Msk
#define PPI_CHG1_CH4_Excluded PPI_CHG_CH4_Excluded
#define PPI_CHG1_CH4_Included PPI_CHG_CH4_Included
#define PPI_CHG1_CH3_Pos PPI_CHG_CH3_Pos
#define PPI_CHG1_CH3_Msk PPI_CHG_CH3_Msk
#define PPI_CHG1_CH3_Excluded PPI_CHG_CH3_Excluded
#define PPI_CHG1_CH3_Included PPI_CHG_CH3_Included
#define PPI_CHG1_CH2_Pos PPI_CHG_CH2_Pos
#define PPI_CHG1_CH2_Msk PPI_CHG_CH2_Msk
#define PPI_CHG1_CH2_Excluded PPI_CHG_CH2_Excluded
#define PPI_CHG1_CH2_Included PPI_CHG_CH2_Included
#define PPI_CHG1_CH1_Pos PPI_CHG_CH1_Pos
#define PPI_CHG1_CH1_Msk PPI_CHG_CH1_Msk
#define PPI_CHG1_CH1_Excluded PPI_CHG_CH1_Excluded
#define PPI_CHG1_CH1_Included PPI_CHG_CH1_Included
#define PPI_CHG1_CH0_Pos PPI_CHG_CH0_Pos
#define PPI_CHG1_CH0_Msk PPI_CHG_CH0_Msk
#define PPI_CHG1_CH0_Excluded PPI_CHG_CH0_Excluded
#define PPI_CHG1_CH0_Included PPI_CHG_CH0_Included
#define PPI_CHG2_CH15_Pos PPI_CHG_CH15_Pos
#define PPI_CHG2_CH15_Msk PPI_CHG_CH15_Msk
#define PPI_CHG2_CH15_Excluded PPI_CHG_CH15_Excluded
#define PPI_CHG2_CH15_Included PPI_CHG_CH15_Included
#define PPI_CHG2_CH14_Pos PPI_CHG_CH14_Pos
#define PPI_CHG2_CH14_Msk PPI_CHG_CH14_Msk
#define PPI_CHG2_CH14_Excluded PPI_CHG_CH14_Excluded
#define PPI_CHG2_CH14_Included PPI_CHG_CH14_Included
#define PPI_CHG2_CH13_Pos PPI_CHG_CH13_Pos
#define PPI_CHG2_CH13_Msk PPI_CHG_CH13_Msk
#define PPI_CHG2_CH13_Excluded PPI_CHG_CH13_Excluded
#define PPI_CHG2_CH13_Included PPI_CHG_CH13_Included
#define PPI_CHG2_CH12_Pos PPI_CHG_CH12_Pos
#define PPI_CHG2_CH12_Msk PPI_CHG_CH12_Msk
#define PPI_CHG2_CH12_Excluded PPI_CHG_CH12_Excluded
#define PPI_CHG2_CH12_Included PPI_CHG_CH12_Included
#define PPI_CHG2_CH11_Pos PPI_CHG_CH11_Pos
#define PPI_CHG2_CH11_Msk PPI_CHG_CH11_Msk
#define PPI_CHG2_CH11_Excluded PPI_CHG_CH11_Excluded
#define PPI_CHG2_CH11_Included PPI_CHG_CH11_Included
#define PPI_CHG2_CH10_Pos PPI_CHG_CH10_Pos
#define PPI_CHG2_CH10_Msk PPI_CHG_CH10_Msk
#define PPI_CHG2_CH10_Excluded PPI_CHG_CH10_Excluded
#define PPI_CHG2_CH10_Included PPI_CHG_CH10_Included
#define PPI_CHG2_CH9_Pos PPI_CHG_CH9_Pos
#define PPI_CHG2_CH9_Msk PPI_CHG_CH9_Msk
#define PPI_CHG2_CH9_Excluded PPI_CHG_CH9_Excluded
#define PPI_CHG2_CH9_Included PPI_CHG_CH9_Included
#define PPI_CHG2_CH8_Pos PPI_CHG_CH8_Pos
#define PPI_CHG2_CH8_Msk PPI_CHG_CH8_Msk
#define PPI_CHG2_CH8_Excluded PPI_CHG_CH8_Excluded
#define PPI_CHG2_CH8_Included PPI_CHG_CH8_Included
#define PPI_CHG2_CH7_Pos PPI_CHG_CH7_Pos
#define PPI_CHG2_CH7_Msk PPI_CHG_CH7_Msk
#define PPI_CHG2_CH7_Excluded PPI_CHG_CH7_Excluded
#define PPI_CHG2_CH7_Included PPI_CHG_CH7_Included
#define PPI_CHG2_CH6_Pos PPI_CHG_CH6_Pos
#define PPI_CHG2_CH6_Msk PPI_CHG_CH6_Msk
#define PPI_CHG2_CH6_Excluded PPI_CHG_CH6_Excluded
#define PPI_CHG2_CH6_Included PPI_CHG_CH6_Included
#define PPI_CHG2_CH5_Pos PPI_CHG_CH5_Pos
#define PPI_CHG2_CH5_Msk PPI_CHG_CH5_Msk
#define PPI_CHG2_CH5_Excluded PPI_CHG_CH5_Excluded
#define PPI_CHG2_CH5_Included PPI_CHG_CH5_Included
#define PPI_CHG2_CH4_Pos PPI_CHG_CH4_Pos
#define PPI_CHG2_CH4_Msk PPI_CHG_CH4_Msk
#define PPI_CHG2_CH4_Excluded PPI_CHG_CH4_Excluded
#define PPI_CHG2_CH4_Included PPI_CHG_CH4_Included
#define PPI_CHG2_CH3_Pos PPI_CHG_CH3_Pos
#define PPI_CHG2_CH3_Msk PPI_CHG_CH3_Msk
#define PPI_CHG2_CH3_Excluded PPI_CHG_CH3_Excluded
#define PPI_CHG2_CH3_Included PPI_CHG_CH3_Included
#define PPI_CHG2_CH2_Pos PPI_CHG_CH2_Pos
#define PPI_CHG2_CH2_Msk PPI_CHG_CH2_Msk
#define PPI_CHG2_CH2_Excluded PPI_CHG_CH2_Excluded
#define PPI_CHG2_CH2_Included PPI_CHG_CH2_Included
#define PPI_CHG2_CH1_Pos PPI_CHG_CH1_Pos
#define PPI_CHG2_CH1_Msk PPI_CHG_CH1_Msk
#define PPI_CHG2_CH1_Excluded PPI_CHG_CH1_Excluded
#define PPI_CHG2_CH1_Included PPI_CHG_CH1_Included
#define PPI_CHG2_CH0_Pos PPI_CHG_CH0_Pos
#define PPI_CHG2_CH0_Msk PPI_CHG_CH0_Msk
#define PPI_CHG2_CH0_Excluded PPI_CHG_CH0_Excluded
#define PPI_CHG2_CH0_Included PPI_CHG_CH0_Included
#define PPI_CHG3_CH15_Pos PPI_CHG_CH15_Pos
#define PPI_CHG3_CH15_Msk PPI_CHG_CH15_Msk
#define PPI_CHG3_CH15_Excluded PPI_CHG_CH15_Excluded
#define PPI_CHG3_CH15_Included PPI_CHG_CH15_Included
#define PPI_CHG3_CH14_Pos PPI_CHG_CH14_Pos
#define PPI_CHG3_CH14_Msk PPI_CHG_CH14_Msk
#define PPI_CHG3_CH14_Excluded PPI_CHG_CH14_Excluded
#define PPI_CHG3_CH14_Included PPI_CHG_CH14_Included
#define PPI_CHG3_CH13_Pos PPI_CHG_CH13_Pos
#define PPI_CHG3_CH13_Msk PPI_CHG_CH13_Msk
#define PPI_CHG3_CH13_Excluded PPI_CHG_CH13_Excluded
#define PPI_CHG3_CH13_Included PPI_CHG_CH13_Included
#define PPI_CHG3_CH12_Pos PPI_CHG_CH12_Pos
#define PPI_CHG3_CH12_Msk PPI_CHG_CH12_Msk
#define PPI_CHG3_CH12_Excluded PPI_CHG_CH12_Excluded
#define PPI_CHG3_CH12_Included PPI_CHG_CH12_Included
#define PPI_CHG3_CH11_Pos PPI_CHG_CH11_Pos
#define PPI_CHG3_CH11_Msk PPI_CHG_CH11_Msk
#define PPI_CHG3_CH11_Excluded PPI_CHG_CH11_Excluded
#define PPI_CHG3_CH11_Included PPI_CHG_CH11_Included
#define PPI_CHG3_CH10_Pos PPI_CHG_CH10_Pos
#define PPI_CHG3_CH10_Msk PPI_CHG_CH10_Msk
#define PPI_CHG3_CH10_Excluded PPI_CHG_CH10_Excluded
#define PPI_CHG3_CH10_Included PPI_CHG_CH10_Included
#define PPI_CHG3_CH9_Pos PPI_CHG_CH9_Pos
#define PPI_CHG3_CH9_Msk PPI_CHG_CH9_Msk
#define PPI_CHG3_CH9_Excluded PPI_CHG_CH9_Excluded
#define PPI_CHG3_CH9_Included PPI_CHG_CH9_Included
#define PPI_CHG3_CH8_Pos PPI_CHG_CH8_Pos
#define PPI_CHG3_CH8_Msk PPI_CHG_CH8_Msk
#define PPI_CHG3_CH8_Excluded PPI_CHG_CH8_Excluded
#define PPI_CHG3_CH8_Included PPI_CHG_CH8_Included
#define PPI_CHG3_CH7_Pos PPI_CHG_CH7_Pos
#define PPI_CHG3_CH7_Msk PPI_CHG_CH7_Msk
#define PPI_CHG3_CH7_Excluded PPI_CHG_CH7_Excluded
#define PPI_CHG3_CH7_Included PPI_CHG_CH7_Included
#define PPI_CHG3_CH6_Pos PPI_CHG_CH6_Pos
#define PPI_CHG3_CH6_Msk PPI_CHG_CH6_Msk
#define PPI_CHG3_CH6_Excluded PPI_CHG_CH6_Excluded
#define PPI_CHG3_CH6_Included PPI_CHG_CH6_Included
#define PPI_CHG3_CH5_Pos PPI_CHG_CH5_Pos
#define PPI_CHG3_CH5_Msk PPI_CHG_CH5_Msk
#define PPI_CHG3_CH5_Excluded PPI_CHG_CH5_Excluded
#define PPI_CHG3_CH5_Included PPI_CHG_CH5_Included
#define PPI_CHG3_CH4_Pos PPI_CHG_CH4_Pos
#define PPI_CHG3_CH4_Msk PPI_CHG_CH4_Msk
#define PPI_CHG3_CH4_Excluded PPI_CHG_CH4_Excluded
#define PPI_CHG3_CH4_Included PPI_CHG_CH4_Included
#define PPI_CHG3_CH3_Pos PPI_CHG_CH3_Pos
#define PPI_CHG3_CH3_Msk PPI_CHG_CH3_Msk
#define PPI_CHG3_CH3_Excluded PPI_CHG_CH3_Excluded
#define PPI_CHG3_CH3_Included PPI_CHG_CH3_Included
#define PPI_CHG3_CH2_Pos PPI_CHG_CH2_Pos
#define PPI_CHG3_CH2_Msk PPI_CHG_CH2_Msk
#define PPI_CHG3_CH2_Excluded PPI_CHG_CH2_Excluded
#define PPI_CHG3_CH2_Included PPI_CHG_CH2_Included
#define PPI_CHG3_CH1_Pos PPI_CHG_CH1_Pos
#define PPI_CHG3_CH1_Msk PPI_CHG_CH1_Msk
#define PPI_CHG3_CH1_Excluded PPI_CHG_CH1_Excluded
#define PPI_CHG3_CH1_Included PPI_CHG_CH1_Included
#define PPI_CHG3_CH0_Pos PPI_CHG_CH0_Pos
#define PPI_CHG3_CH0_Msk PPI_CHG_CH0_Msk
#define PPI_CHG3_CH0_Excluded PPI_CHG_CH0_Excluded
#define PPI_CHG3_CH0_Included PPI_CHG_CH0_Included
/*lint --flb "Leave library region" */
#endif /* NRF51_DEPRECATED_H */

69
ports/nrf/device/nrf51/system_nrf51.h
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@ -1,69 +0,0 @@
/* Copyright (c) 2012 ARM LIMITED
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* * Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* * Neither the name of ARM nor the names of its contributors may be used to
* endorse or promote products derived from this software without specific
* prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifndef SYSTEM_NRF51_H
#define SYSTEM_NRF51_H
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
/**
* Initialize the system
*
* @param none
* @return none
*
* @brief Setup the microcontroller system.
* Initialize the System and update the SystemCoreClock variable.
*/
extern void SystemInit (void);
/**
* Update SystemCoreClock variable
*
* @param none
* @return none
*
* @brief Updates the SystemCoreClock with current core Clock
* retrieved from cpu registers.
*/
extern void SystemCoreClockUpdate (void);
#ifdef __cplusplus
}
#endif
#endif /* SYSTEM_NRF51_H */

151
ports/nrf/device/nrf51/system_nrf51822.c
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@ -1,151 +0,0 @@
/* Copyright (c) 2012 ARM LIMITED
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* * Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* * Neither the name of ARM nor the names of its contributors may be used to
* endorse or promote products derived from this software without specific
* prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
/* NOTE: Template files (including this one) are application specific and therefore expected to
be copied into the application project folder prior to its use! */
#include <stdint.h>
#include <stdbool.h>
#include "nrf.h"
#include "system_nrf51.h"
/*lint ++flb "Enter library region" */
#define __SYSTEM_CLOCK (16000000UL) /*!< nRF51 devices use a fixed System Clock Frequency of 16MHz */
static bool is_manual_peripheral_setup_needed(void);
static bool is_disabled_in_debug_needed(void);
static bool is_peripheral_domain_setup_needed(void);
#if defined ( __CC_ARM )
uint32_t SystemCoreClock __attribute__((used)) = __SYSTEM_CLOCK;
#elif defined ( __ICCARM__ )
__root uint32_t SystemCoreClock = __SYSTEM_CLOCK;
#elif defined ( __GNUC__ )
uint32_t SystemCoreClock __attribute__((used)) = __SYSTEM_CLOCK;
#endif
void SystemCoreClockUpdate(void)
{
SystemCoreClock = __SYSTEM_CLOCK;
}
void SystemInit(void)
{
/* If desired, switch off the unused RAM to lower consumption by the use of RAMON register.
It can also be done in the application main() function. */
/* Prepare the peripherals for use as indicated by the PAN 26 "System: Manual setup is required
to enable the use of peripherals" found at Product Anomaly document for your device found at
https://www.nordicsemi.com/. The side effect of executing these instructions in the devices
that do not need it is that the new peripherals in the second generation devices (LPCOMP for
example) will not be available. */
if (is_manual_peripheral_setup_needed())
{
*(uint32_t volatile *)0x40000504 = 0xC007FFDF;
*(uint32_t volatile *)0x40006C18 = 0x00008000;
}
/* Disable PROTENSET registers under debug, as indicated by PAN 59 "MPU: Reset value of DISABLEINDEBUG
register is incorrect" found at Product Anomaly document for your device found at
https://www.nordicsemi.com/. There is no side effect of using these instruction if not needed. */
if (is_disabled_in_debug_needed())
{
NRF_MPU->DISABLEINDEBUG = MPU_DISABLEINDEBUG_DISABLEINDEBUG_Disabled << MPU_DISABLEINDEBUG_DISABLEINDEBUG_Pos;
}
/* Execute the following code to eliminate excessive current in sleep mode with RAM retention in nRF51802 devices,
as indicated by PAN 76 "System: Excessive current in sleep mode with retention" found at Product Anomaly document
for your device found at https://www.nordicsemi.com/. */
if (is_peripheral_domain_setup_needed()){
if (*(uint32_t volatile *)0x4006EC00 != 1){
*(uint32_t volatile *)0x4006EC00 = 0x9375;
while (*(uint32_t volatile *)0x4006EC00 != 1){
}
}
*(uint32_t volatile *)0x4006EC14 = 0xC0;
}
}
static bool is_manual_peripheral_setup_needed(void)
{
if ((((*(uint32_t *)0xF0000FE0) & 0x000000FF) == 0x1) && (((*(uint32_t *)0xF0000FE4) & 0x0000000F) == 0x0))
{
if ((((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x00) && (((*(uint32_t *)0xF0000FEC) & 0x000000F0) == 0x0))
{
return true;
}
if ((((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x10) && (((*(uint32_t *)0xF0000FEC) & 0x000000F0) == 0x0))
{
return true;
}
if ((((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x30) && (((*(uint32_t *)0xF0000FEC) & 0x000000F0) == 0x0))
{
return true;
}
}
return false;
}
static bool is_disabled_in_debug_needed(void)
{
if ((((*(uint32_t *)0xF0000FE0) & 0x000000FF) == 0x1) && (((*(uint32_t *)0xF0000FE4) & 0x0000000F) == 0x0))
{
if ((((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x40) && (((*(uint32_t *)0xF0000FEC) & 0x000000F0) == 0x0))
{
return true;
}
}
return false;
}
static bool is_peripheral_domain_setup_needed(void)
{
if ((((*(uint32_t *)0xF0000FE0) & 0x000000FF) == 0x1) && (((*(uint32_t *)0xF0000FE4) & 0x0000000F) == 0x0))
{
if ((((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0xA0) && (((*(uint32_t *)0xF0000FEC) & 0x000000F0) == 0x0))
{
return true;
}
if ((((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0xD0) && (((*(uint32_t *)0xF0000FEC) & 0x000000F0) == 0x0))
{
return true;
}
}
return false;
}
/*lint --flb "Leave library region" */

952
ports/nrf/device/nrf52/nrf51_to_nrf52.h
View File

@ -1,952 +0,0 @@
/* Copyright (c) 2016, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* * Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* * Neither the name of Nordic Semiconductor ASA nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifndef NRF51_TO_NRF52_H
#define NRF51_TO_NRF52_H
/*lint ++flb "Enter library region */
/* This file is given to prevent your SW from not compiling with the name changes between nRF51 and nRF52 devices.
* It redefines the old nRF51 names into the new ones as long as the functionality is still supported. If the
* functionality is gone, there old names are not defined, so compilation will fail. Note that also includes macros
* from the nrf51_deprecated.h file. */
/* IRQ */
/* Several peripherals have been added to several indexes. Names of IRQ handlers and IRQ numbers have changed. */
#define UART0_IRQHandler UARTE0_UART0_IRQHandler
#define SPI0_TWI0_IRQHandler SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler
#define SPI1_TWI1_IRQHandler SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler
#define ADC_IRQHandler SAADC_IRQHandler
#define LPCOMP_IRQHandler COMP_LPCOMP_IRQHandler
#define SWI0_IRQHandler SWI0_EGU0_IRQHandler
#define SWI1_IRQHandler SWI1_EGU1_IRQHandler
#define SWI2_IRQHandler SWI2_EGU2_IRQHandler
#define SWI3_IRQHandler SWI3_EGU3_IRQHandler
#define SWI4_IRQHandler SWI4_EGU4_IRQHandler
#define SWI5_IRQHandler SWI5_EGU5_IRQHandler
#define UART0_IRQn UARTE0_UART0_IRQn
#define SPI0_TWI0_IRQn SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQn
#define SPI1_TWI1_IRQn SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQn
#define ADC_IRQn SAADC_IRQn
#define LPCOMP_IRQn COMP_LPCOMP_IRQn
#define SWI0_IRQn SWI0_EGU0_IRQn
#define SWI1_IRQn SWI1_EGU1_IRQn
#define SWI2_IRQn SWI2_EGU2_IRQn
#define SWI3_IRQn SWI3_EGU3_IRQn
#define SWI4_IRQn SWI4_EGU4_IRQn
#define SWI5_IRQn SWI5_EGU5_IRQn
/* UICR */
/* Register RBPCONF was renamed to APPROTECT. */
#define RBPCONF APPROTECT
#define UICR_RBPCONF_PALL_Pos UICR_APPROTECT_PALL_Pos
#define UICR_RBPCONF_PALL_Msk UICR_APPROTECT_PALL_Msk
#define UICR_RBPCONF_PALL_Enabled UICR_APPROTECT_PALL_Enabled
#define UICR_RBPCONF_PALL_Disabled UICR_APPROTECT_PALL_Disabled
/* GPIO */
/* GPIO port was renamed to P0. */
#define NRF_GPIO NRF_P0
#define NRF_GPIO_BASE NRF_P0_BASE
/* QDEC */
/* The registers PSELA, PSELB and PSELLED were restructured into a struct. */
#define PSELLED PSEL.LED
#define PSELA PSEL.A
#define PSELB PSEL.B
/* SPIS */
/* The registers PSELSCK, PSELMISO, PSELMOSI, PSELCSN were restructured into a struct. */
#define PSELSCK PSEL.SCK
#define PSELMISO PSEL.MISO
#define PSELMOSI PSEL.MOSI
#define PSELCSN PSEL.CSN
/* The registers RXDPTR, MAXRX, AMOUNTRX were restructured into a struct */
#define RXDPTR RXD.PTR
#define MAXRX RXD.MAXCNT
#define AMOUNTRX RXD.AMOUNT
#define SPIS_MAXRX_MAXRX_Pos SPIS_RXD_MAXCNT_MAXCNT_Pos
#define SPIS_MAXRX_MAXRX_Msk SPIS_RXD_MAXCNT_MAXCNT_Msk
#define SPIS_AMOUNTRX_AMOUNTRX_Pos SPIS_RXD_AMOUNT_AMOUNT_Pos
#define SPIS_AMOUNTRX_AMOUNTRX_Msk SPIS_RXD_AMOUNT_AMOUNT_Msk
/* The registers TXDPTR, MAXTX, AMOUNTTX were restructured into a struct */
#define TXDPTR TXD.PTR
#define MAXTX TXD.MAXCNT
#define AMOUNTTX TXD.AMOUNT
#define SPIS_MAXTX_MAXTX_Pos SPIS_TXD_MAXCNT_MAXCNT_Pos
#define SPIS_MAXTX_MAXTX_Msk SPIS_TXD_MAXCNT_MAXCNT_Msk
#define SPIS_AMOUNTTX_AMOUNTTX_Pos SPIS_TXD_AMOUNT_AMOUNT_Pos
#define SPIS_AMOUNTTX_AMOUNTTX_Msk SPIS_TXD_AMOUNT_AMOUNT_Msk
/* MPU */
/* Part of MPU module was renamed BPROT, while the rest was eliminated. */
#define NRF_MPU NRF_BPROT
/* Register DISABLEINDEBUG macros were affected. */
#define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Pos BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Pos
#define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Msk BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Msk
#define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Enabled BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Enabled
#define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Disabled BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Disabled
/* Registers PROTENSET0 and PROTENSET1 were affected and renamed as CONFIG0 and CONFIG1. */
#define PROTENSET0 CONFIG0
#define PROTENSET1 CONFIG1
#define MPU_PROTENSET1_PROTREG63_Pos BPROT_CONFIG1_REGION63_Pos
#define MPU_PROTENSET1_PROTREG63_Msk BPROT_CONFIG1_REGION63_Msk
#define MPU_PROTENSET1_PROTREG63_Disabled BPROT_CONFIG1_REGION63_Disabled
#define MPU_PROTENSET1_PROTREG63_Enabled BPROT_CONFIG1_REGION63_Enabled
#define MPU_PROTENSET1_PROTREG63_Set BPROT_CONFIG1_REGION63_Enabled
#define MPU_PROTENSET1_PROTREG62_Pos BPROT_CONFIG1_REGION62_Pos
#define MPU_PROTENSET1_PROTREG62_Msk BPROT_CONFIG1_REGION62_Msk
#define MPU_PROTENSET1_PROTREG62_Disabled BPROT_CONFIG1_REGION62_Disabled
#define MPU_PROTENSET1_PROTREG62_Enabled BPROT_CONFIG1_REGION62_Enabled
#define MPU_PROTENSET1_PROTREG62_Set BPROT_CONFIG1_REGION62_Enabled
#define MPU_PROTENSET1_PROTREG61_Pos BPROT_CONFIG1_REGION61_Pos
#define MPU_PROTENSET1_PROTREG61_Msk BPROT_CONFIG1_REGION61_Msk
#define MPU_PROTENSET1_PROTREG61_Disabled BPROT_CONFIG1_REGION61_Disabled
#define MPU_PROTENSET1_PROTREG61_Enabled BPROT_CONFIG1_REGION61_Enabled
#define MPU_PROTENSET1_PROTREG61_Set BPROT_CONFIG1_REGION61_Enabled
#define MPU_PROTENSET1_PROTREG60_Pos BPROT_CONFIG1_REGION60_Pos
#define MPU_PROTENSET1_PROTREG60_Msk BPROT_CONFIG1_REGION60_Msk
#define MPU_PROTENSET1_PROTREG60_Disabled BPROT_CONFIG1_REGION60_Disabled
#define MPU_PROTENSET1_PROTREG60_Enabled BPROT_CONFIG1_REGION60_Enabled
#define MPU_PROTENSET1_PROTREG60_Set BPROT_CONFIG1_REGION60_Enabled
#define MPU_PROTENSET1_PROTREG59_Pos BPROT_CONFIG1_REGION59_Pos
#define MPU_PROTENSET1_PROTREG59_Msk BPROT_CONFIG1_REGION59_Msk
#define MPU_PROTENSET1_PROTREG59_Disabled BPROT_CONFIG1_REGION59_Disabled
#define MPU_PROTENSET1_PROTREG59_Enabled BPROT_CONFIG1_REGION59_Enabled
#define MPU_PROTENSET1_PROTREG59_Set BPROT_CONFIG1_REGION59_Enabled
#define MPU_PROTENSET1_PROTREG58_Pos BPROT_CONFIG1_REGION58_Pos
#define MPU_PROTENSET1_PROTREG58_Msk BPROT_CONFIG1_REGION58_Msk
#define MPU_PROTENSET1_PROTREG58_Disabled BPROT_CONFIG1_REGION58_Disabled
#define MPU_PROTENSET1_PROTREG58_Enabled BPROT_CONFIG1_REGION58_Enabled
#define MPU_PROTENSET1_PROTREG58_Set BPROT_CONFIG1_REGION58_Enabled
#define MPU_PROTENSET1_PROTREG57_Pos BPROT_CONFIG1_REGION57_Pos
#define MPU_PROTENSET1_PROTREG57_Msk BPROT_CONFIG1_REGION57_Msk
#define MPU_PROTENSET1_PROTREG57_Disabled BPROT_CONFIG1_REGION57_Disabled
#define MPU_PROTENSET1_PROTREG57_Enabled BPROT_CONFIG1_REGION57_Enabled
#define MPU_PROTENSET1_PROTREG57_Set BPROT_CONFIG1_REGION57_Enabled
#define MPU_PROTENSET1_PROTREG56_Pos BPROT_CONFIG1_REGION56_Pos
#define MPU_PROTENSET1_PROTREG56_Msk BPROT_CONFIG1_REGION56_Msk
#define MPU_PROTENSET1_PROTREG56_Disabled BPROT_CONFIG1_REGION56_Disabled
#define MPU_PROTENSET1_PROTREG56_Enabled BPROT_CONFIG1_REGION56_Enabled
#define MPU_PROTENSET1_PROTREG56_Set BPROT_CONFIG1_REGION56_Enabled
#define MPU_PROTENSET1_PROTREG55_Pos BPROT_CONFIG1_REGION55_Pos
#define MPU_PROTENSET1_PROTREG55_Msk BPROT_CONFIG1_REGION55_Msk
#define MPU_PROTENSET1_PROTREG55_Disabled BPROT_CONFIG1_REGION55_Disabled
#define MPU_PROTENSET1_PROTREG55_Enabled BPROT_CONFIG1_REGION55_Enabled
#define MPU_PROTENSET1_PROTREG55_Set BPROT_CONFIG1_REGION55_Enabled
#define MPU_PROTENSET1_PROTREG54_Pos BPROT_CONFIG1_REGION54_Pos
#define MPU_PROTENSET1_PROTREG54_Msk BPROT_CONFIG1_REGION54_Msk
#define MPU_PROTENSET1_PROTREG54_Disabled BPROT_CONFIG1_REGION54_Disabled
#define MPU_PROTENSET1_PROTREG54_Enabled BPROT_CONFIG1_REGION54_Enabled
#define MPU_PROTENSET1_PROTREG54_Set BPROT_CONFIG1_REGION54_Enabled
#define MPU_PROTENSET1_PROTREG53_Pos BPROT_CONFIG1_REGION53_Pos
#define MPU_PROTENSET1_PROTREG53_Msk BPROT_CONFIG1_REGION53_Msk
#define MPU_PROTENSET1_PROTREG53_Disabled BPROT_CONFIG1_REGION53_Disabled
#define MPU_PROTENSET1_PROTREG53_Enabled BPROT_CONFIG1_REGION53_Enabled
#define MPU_PROTENSET1_PROTREG53_Set BPROT_CONFIG1_REGION53_Enabled
#define MPU_PROTENSET1_PROTREG52_Pos BPROT_CONFIG1_REGION52_Pos
#define MPU_PROTENSET1_PROTREG52_Msk BPROT_CONFIG1_REGION52_Msk
#define MPU_PROTENSET1_PROTREG52_Disabled BPROT_CONFIG1_REGION52_Disabled
#define MPU_PROTENSET1_PROTREG52_Enabled BPROT_CONFIG1_REGION52_Enabled
#define MPU_PROTENSET1_PROTREG52_Set BPROT_CONFIG1_REGION52_Enabled
#define MPU_PROTENSET1_PROTREG51_Pos BPROT_CONFIG1_REGION51_Pos
#define MPU_PROTENSET1_PROTREG51_Msk BPROT_CONFIG1_REGION51_Msk
#define MPU_PROTENSET1_PROTREG51_Disabled BPROT_CONFIG1_REGION51_Disabled
#define MPU_PROTENSET1_PROTREG51_Enabled BPROT_CONFIG1_REGION51_Enabled
#define MPU_PROTENSET1_PROTREG51_Set BPROT_CONFIG1_REGION51_Enabled
#define MPU_PROTENSET1_PROTREG50_Pos BPROT_CONFIG1_REGION50_Pos
#define MPU_PROTENSET1_PROTREG50_Msk BPROT_CONFIG1_REGION50_Msk
#define MPU_PROTENSET1_PROTREG50_Disabled BPROT_CONFIG1_REGION50_Disabled
#define MPU_PROTENSET1_PROTREG50_Enabled BPROT_CONFIG1_REGION50_Enabled
#define MPU_PROTENSET1_PROTREG50_Set BPROT_CONFIG1_REGION50_Enabled
#define MPU_PROTENSET1_PROTREG49_Pos BPROT_CONFIG1_REGION49_Pos
#define MPU_PROTENSET1_PROTREG49_Msk BPROT_CONFIG1_REGION49_Msk
#define MPU_PROTENSET1_PROTREG49_Disabled BPROT_CONFIG1_REGION49_Disabled
#define MPU_PROTENSET1_PROTREG49_Enabled BPROT_CONFIG1_REGION49_Enabled
#define MPU_PROTENSET1_PROTREG49_Set BPROT_CONFIG1_REGION49_Enabled
#define MPU_PROTENSET1_PROTREG48_Pos BPROT_CONFIG1_REGION48_Pos
#define MPU_PROTENSET1_PROTREG48_Msk BPROT_CONFIG1_REGION48_Msk
#define MPU_PROTENSET1_PROTREG48_Disabled BPROT_CONFIG1_REGION48_Disabled
#define MPU_PROTENSET1_PROTREG48_Enabled BPROT_CONFIG1_REGION48_Enabled
#define MPU_PROTENSET1_PROTREG48_Set BPROT_CONFIG1_REGION48_Enabled
#define MPU_PROTENSET1_PROTREG47_Pos BPROT_CONFIG1_REGION47_Pos
#define MPU_PROTENSET1_PROTREG47_Msk BPROT_CONFIG1_REGION47_Msk
#define MPU_PROTENSET1_PROTREG47_Disabled BPROT_CONFIG1_REGION47_Disabled
#define MPU_PROTENSET1_PROTREG47_Enabled BPROT_CONFIG1_REGION47_Enabled
#define MPU_PROTENSET1_PROTREG47_Set BPROT_CONFIG1_REGION47_Enabled
#define MPU_PROTENSET1_PROTREG46_Pos BPROT_CONFIG1_REGION46_Pos
#define MPU_PROTENSET1_PROTREG46_Msk BPROT_CONFIG1_REGION46_Msk
#define MPU_PROTENSET1_PROTREG46_Disabled BPROT_CONFIG1_REGION46_Disabled
#define MPU_PROTENSET1_PROTREG46_Enabled BPROT_CONFIG1_REGION46_Enabled
#define MPU_PROTENSET1_PROTREG46_Set BPROT_CONFIG1_REGION46_Enabled
#define MPU_PROTENSET1_PROTREG45_Pos BPROT_CONFIG1_REGION45_Pos
#define MPU_PROTENSET1_PROTREG45_Msk BPROT_CONFIG1_REGION45_Msk
#define MPU_PROTENSET1_PROTREG45_Disabled BPROT_CONFIG1_REGION45_Disabled
#define MPU_PROTENSET1_PROTREG45_Enabled BPROT_CONFIG1_REGION45_Enabled
#define MPU_PROTENSET1_PROTREG45_Set BPROT_CONFIG1_REGION45_Enabled
#define MPU_PROTENSET1_PROTREG44_Pos BPROT_CONFIG1_REGION44_Pos
#define MPU_PROTENSET1_PROTREG44_Msk BPROT_CONFIG1_REGION44_Msk
#define MPU_PROTENSET1_PROTREG44_Disabled BPROT_CONFIG1_REGION44_Disabled
#define MPU_PROTENSET1_PROTREG44_Enabled BPROT_CONFIG1_REGION44_Enabled
#define MPU_PROTENSET1_PROTREG44_Set BPROT_CONFIG1_REGION44_Enabled
#define MPU_PROTENSET1_PROTREG43_Pos BPROT_CONFIG1_REGION43_Pos
#define MPU_PROTENSET1_PROTREG43_Msk BPROT_CONFIG1_REGION43_Msk
#define MPU_PROTENSET1_PROTREG43_Disabled BPROT_CONFIG1_REGION43_Disabled
#define MPU_PROTENSET1_PROTREG43_Enabled BPROT_CONFIG1_REGION43_Enabled
#define MPU_PROTENSET1_PROTREG43_Set BPROT_CONFIG1_REGION43_Enabled
#define MPU_PROTENSET1_PROTREG42_Pos BPROT_CONFIG1_REGION42_Pos
#define MPU_PROTENSET1_PROTREG42_Msk BPROT_CONFIG1_REGION42_Msk
#define MPU_PROTENSET1_PROTREG42_Disabled BPROT_CONFIG1_REGION42_Disabled
#define MPU_PROTENSET1_PROTREG42_Enabled BPROT_CONFIG1_REGION42_Enabled
#define MPU_PROTENSET1_PROTREG42_Set BPROT_CONFIG1_REGION42_Enabled
#define MPU_PROTENSET1_PROTREG41_Pos BPROT_CONFIG1_REGION41_Pos
#define MPU_PROTENSET1_PROTREG41_Msk BPROT_CONFIG1_REGION41_Msk
#define MPU_PROTENSET1_PROTREG41_Disabled BPROT_CONFIG1_REGION41_Disabled
#define MPU_PROTENSET1_PROTREG41_Enabled BPROT_CONFIG1_REGION41_Enabled
#define MPU_PROTENSET1_PROTREG41_Set BPROT_CONFIG1_REGION41_Enabled
#define MPU_PROTENSET1_PROTREG40_Pos BPROT_CONFIG1_REGION40_Pos
#define MPU_PROTENSET1_PROTREG40_Msk BPROT_CONFIG1_REGION40_Msk
#define MPU_PROTENSET1_PROTREG40_Disabled BPROT_CONFIG1_REGION40_Disabled
#define MPU_PROTENSET1_PROTREG40_Enabled BPROT_CONFIG1_REGION40_Enabled
#define MPU_PROTENSET1_PROTREG40_Set BPROT_CONFIG1_REGION40_Enabled
#define MPU_PROTENSET1_PROTREG39_Pos BPROT_CONFIG1_REGION39_Pos
#define MPU_PROTENSET1_PROTREG39_Msk BPROT_CONFIG1_REGION39_Msk
#define MPU_PROTENSET1_PROTREG39_Disabled BPROT_CONFIG1_REGION39_Disabled
#define MPU_PROTENSET1_PROTREG39_Enabled BPROT_CONFIG1_REGION39_Enabled
#define MPU_PROTENSET1_PROTREG39_Set BPROT_CONFIG1_REGION39_Enabled
#define MPU_PROTENSET1_PROTREG38_Pos BPROT_CONFIG1_REGION38_Pos
#define MPU_PROTENSET1_PROTREG38_Msk BPROT_CONFIG1_REGION38_Msk
#define MPU_PROTENSET1_PROTREG38_Disabled BPROT_CONFIG1_REGION38_Disabled
#define MPU_PROTENSET1_PROTREG38_Enabled BPROT_CONFIG1_REGION38_Enabled
#define MPU_PROTENSET1_PROTREG38_Set BPROT_CONFIG1_REGION38_Enabled
#define MPU_PROTENSET1_PROTREG37_Pos BPROT_CONFIG1_REGION37_Pos
#define MPU_PROTENSET1_PROTREG37_Msk BPROT_CONFIG1_REGION37_Msk
#define MPU_PROTENSET1_PROTREG37_Disabled BPROT_CONFIG1_REGION37_Disabled
#define MPU_PROTENSET1_PROTREG37_Enabled BPROT_CONFIG1_REGION37_Enabled
#define MPU_PROTENSET1_PROTREG37_Set BPROT_CONFIG1_REGION37_Enabled
#define MPU_PROTENSET1_PROTREG36_Pos BPROT_CONFIG1_REGION36_Pos
#define MPU_PROTENSET1_PROTREG36_Msk BPROT_CONFIG1_REGION36_Msk
#define MPU_PROTENSET1_PROTREG36_Disabled BPROT_CONFIG1_REGION36_Disabled
#define MPU_PROTENSET1_PROTREG36_Enabled BPROT_CONFIG1_REGION36_Enabled
#define MPU_PROTENSET1_PROTREG36_Set BPROT_CONFIG1_REGION36_Enabled
#define MPU_PROTENSET1_PROTREG35_Pos BPROT_CONFIG1_REGION35_Pos
#define MPU_PROTENSET1_PROTREG35_Msk BPROT_CONFIG1_REGION35_Msk
#define MPU_PROTENSET1_PROTREG35_Disabled BPROT_CONFIG1_REGION35_Disabled
#define MPU_PROTENSET1_PROTREG35_Enabled BPROT_CONFIG1_REGION35_Enabled
#define MPU_PROTENSET1_PROTREG35_Set BPROT_CONFIG1_REGION35_Enabled
#define MPU_PROTENSET1_PROTREG34_Pos BPROT_CONFIG1_REGION34_Pos
#define MPU_PROTENSET1_PROTREG34_Msk BPROT_CONFIG1_REGION34_Msk
#define MPU_PROTENSET1_PROTREG34_Disabled BPROT_CONFIG1_REGION34_Disabled
#define MPU_PROTENSET1_PROTREG34_Enabled BPROT_CONFIG1_REGION34_Enabled
#define MPU_PROTENSET1_PROTREG34_Set BPROT_CONFIG1_REGION34_Enabled
#define MPU_PROTENSET1_PROTREG33_Pos BPROT_CONFIG1_REGION33_Pos
#define MPU_PROTENSET1_PROTREG33_Msk BPROT_CONFIG1_REGION33_Msk
#define MPU_PROTENSET1_PROTREG33_Disabled BPROT_CONFIG1_REGION33_Disabled
#define MPU_PROTENSET1_PROTREG33_Enabled BPROT_CONFIG1_REGION33_Enabled
#define MPU_PROTENSET1_PROTREG33_Set BPROT_CONFIG1_REGION33_Enabled
#define MPU_PROTENSET1_PROTREG32_Pos BPROT_CONFIG1_REGION32_Pos
#define MPU_PROTENSET1_PROTREG32_Msk BPROT_CONFIG1_REGION32_Msk
#define MPU_PROTENSET1_PROTREG32_Disabled BPROT_CONFIG1_REGION32_Disabled
#define MPU_PROTENSET1_PROTREG32_Enabled BPROT_CONFIG1_REGION32_Enabled
#define MPU_PROTENSET1_PROTREG32_Set BPROT_CONFIG1_REGION32_Enabled
#define MPU_PROTENSET0_PROTREG31_Pos BPROT_CONFIG0_REGION31_Pos
#define MPU_PROTENSET0_PROTREG31_Msk BPROT_CONFIG0_REGION31_Msk
#define MPU_PROTENSET0_PROTREG31_Disabled BPROT_CONFIG0_REGION31_Disabled
#define MPU_PROTENSET0_PROTREG31_Enabled BPROT_CONFIG0_REGION31_Enabled
#define MPU_PROTENSET0_PROTREG31_Set BPROT_CONFIG0_REGION31_Enabled
#define MPU_PROTENSET0_PROTREG30_Pos BPROT_CONFIG0_REGION30_Pos
#define MPU_PROTENSET0_PROTREG30_Msk BPROT_CONFIG0_REGION30_Msk
#define MPU_PROTENSET0_PROTREG30_Disabled BPROT_CONFIG0_REGION30_Disabled
#define MPU_PROTENSET0_PROTREG30_Enabled BPROT_CONFIG0_REGION30_Enabled
#define MPU_PROTENSET0_PROTREG30_Set BPROT_CONFIG0_REGION30_Enabled
#define MPU_PROTENSET0_PROTREG29_Pos BPROT_CONFIG0_REGION29_Pos
#define MPU_PROTENSET0_PROTREG29_Msk BPROT_CONFIG0_REGION29_Msk
#define MPU_PROTENSET0_PROTREG29_Disabled BPROT_CONFIG0_REGION29_Disabled
#define MPU_PROTENSET0_PROTREG29_Enabled BPROT_CONFIG0_REGION29_Enabled
#define MPU_PROTENSET0_PROTREG29_Set BPROT_CONFIG0_REGION29_Enabled
#define MPU_PROTENSET0_PROTREG28_Pos BPROT_CONFIG0_REGION28_Pos
#define MPU_PROTENSET0_PROTREG28_Msk BPROT_CONFIG0_REGION28_Msk
#define MPU_PROTENSET0_PROTREG28_Disabled BPROT_CONFIG0_REGION28_Disabled
#define MPU_PROTENSET0_PROTREG28_Enabled BPROT_CONFIG0_REGION28_Enabled
#define MPU_PROTENSET0_PROTREG28_Set BPROT_CONFIG0_REGION28_Enabled
#define MPU_PROTENSET0_PROTREG27_Pos BPROT_CONFIG0_REGION27_Pos
#define MPU_PROTENSET0_PROTREG27_Msk BPROT_CONFIG0_REGION27_Msk
#define MPU_PROTENSET0_PROTREG27_Disabled BPROT_CONFIG0_REGION27_Disabled
#define MPU_PROTENSET0_PROTREG27_Enabled BPROT_CONFIG0_REGION27_Enabled
#define MPU_PROTENSET0_PROTREG27_Set BPROT_CONFIG0_REGION27_Enabled
#define MPU_PROTENSET0_PROTREG26_Pos BPROT_CONFIG0_REGION26_Pos
#define MPU_PROTENSET0_PROTREG26_Msk BPROT_CONFIG0_REGION26_Msk
#define MPU_PROTENSET0_PROTREG26_Disabled BPROT_CONFIG0_REGION26_Disabled
#define MPU_PROTENSET0_PROTREG26_Enabled BPROT_CONFIG0_REGION26_Enabled
#define MPU_PROTENSET0_PROTREG26_Set BPROT_CONFIG0_REGION26_Enabled
#define MPU_PROTENSET0_PROTREG25_Pos BPROT_CONFIG0_REGION25_Pos
#define MPU_PROTENSET0_PROTREG25_Msk BPROT_CONFIG0_REGION25_Msk
#define MPU_PROTENSET0_PROTREG25_Disabled BPROT_CONFIG0_REGION25_Disabled
#define MPU_PROTENSET0_PROTREG25_Enabled BPROT_CONFIG0_REGION25_Enabled
#define MPU_PROTENSET0_PROTREG25_Set BPROT_CONFIG0_REGION25_Enabled
#define MPU_PROTENSET0_PROTREG24_Pos BPROT_CONFIG0_REGION24_Pos
#define MPU_PROTENSET0_PROTREG24_Msk BPROT_CONFIG0_REGION24_Msk
#define MPU_PROTENSET0_PROTREG24_Disabled BPROT_CONFIG0_REGION24_Disabled
#define MPU_PROTENSET0_PROTREG24_Enabled BPROT_CONFIG0_REGION24_Enabled
#define MPU_PROTENSET0_PROTREG24_Set BPROT_CONFIG0_REGION24_Enabled
#define MPU_PROTENSET0_PROTREG23_Pos BPROT_CONFIG0_REGION23_Pos
#define MPU_PROTENSET0_PROTREG23_Msk BPROT_CONFIG0_REGION23_Msk
#define MPU_PROTENSET0_PROTREG23_Disabled BPROT_CONFIG0_REGION23_Disabled
#define MPU_PROTENSET0_PROTREG23_Enabled BPROT_CONFIG0_REGION23_Enabled
#define MPU_PROTENSET0_PROTREG23_Set BPROT_CONFIG0_REGION23_Enabled
#define MPU_PROTENSET0_PROTREG22_Pos BPROT_CONFIG0_REGION22_Pos
#define MPU_PROTENSET0_PROTREG22_Msk BPROT_CONFIG0_REGION22_Msk
#define MPU_PROTENSET0_PROTREG22_Disabled BPROT_CONFIG0_REGION22_Disabled
#define MPU_PROTENSET0_PROTREG22_Enabled BPROT_CONFIG0_REGION22_Enabled
#define MPU_PROTENSET0_PROTREG22_Set BPROT_CONFIG0_REGION22_Enabled
#define MPU_PROTENSET0_PROTREG21_Pos BPROT_CONFIG0_REGION21_Pos
#define MPU_PROTENSET0_PROTREG21_Msk BPROT_CONFIG0_REGION21_Msk
#define MPU_PROTENSET0_PROTREG21_Disabled BPROT_CONFIG0_REGION21_Disabled
#define MPU_PROTENSET0_PROTREG21_Enabled BPROT_CONFIG0_REGION21_Enabled
#define MPU_PROTENSET0_PROTREG21_Set BPROT_CONFIG0_REGION21_Enabled
#define MPU_PROTENSET0_PROTREG20_Pos BPROT_CONFIG0_REGION20_Pos
#define MPU_PROTENSET0_PROTREG20_Msk BPROT_CONFIG0_REGION20_Msk
#define MPU_PROTENSET0_PROTREG20_Disabled BPROT_CONFIG0_REGION20_Disabled
#define MPU_PROTENSET0_PROTREG20_Enabled BPROT_CONFIG0_REGION20_Enabled
#define MPU_PROTENSET0_PROTREG20_Set BPROT_CONFIG0_REGION20_Enabled
#define MPU_PROTENSET0_PROTREG19_Pos BPROT_CONFIG0_REGION19_Pos
#define MPU_PROTENSET0_PROTREG19_Msk BPROT_CONFIG0_REGION19_Msk
#define MPU_PROTENSET0_PROTREG19_Disabled BPROT_CONFIG0_REGION19_Disabled
#define MPU_PROTENSET0_PROTREG19_Enabled BPROT_CONFIG0_REGION19_Enabled
#define MPU_PROTENSET0_PROTREG19_Set BPROT_CONFIG0_REGION19_Enabled
#define MPU_PROTENSET0_PROTREG18_Pos BPROT_CONFIG0_REGION18_Pos
#define MPU_PROTENSET0_PROTREG18_Msk BPROT_CONFIG0_REGION18_Msk
#define MPU_PROTENSET0_PROTREG18_Disabled BPROT_CONFIG0_REGION18_Disabled
#define MPU_PROTENSET0_PROTREG18_Enabled BPROT_CONFIG0_REGION18_Enabled
#define MPU_PROTENSET0_PROTREG18_Set BPROT_CONFIG0_REGION18_Enabled
#define MPU_PROTENSET0_PROTREG17_Pos BPROT_CONFIG0_REGION17_Pos
#define MPU_PROTENSET0_PROTREG17_Msk BPROT_CONFIG0_REGION17_Msk
#define MPU_PROTENSET0_PROTREG17_Disabled BPROT_CONFIG0_REGION17_Disabled
#define MPU_PROTENSET0_PROTREG17_Enabled BPROT_CONFIG0_REGION17_Enabled
#define MPU_PROTENSET0_PROTREG17_Set BPROT_CONFIG0_REGION17_Enabled
#define MPU_PROTENSET0_PROTREG16_Pos BPROT_CONFIG0_REGION16_Pos
#define MPU_PROTENSET0_PROTREG16_Msk BPROT_CONFIG0_REGION16_Msk
#define MPU_PROTENSET0_PROTREG16_Disabled BPROT_CONFIG0_REGION16_Disabled
#define MPU_PROTENSET0_PROTREG16_Enabled BPROT_CONFIG0_REGION16_Enabled
#define MPU_PROTENSET0_PROTREG16_Set BPROT_CONFIG0_REGION16_Enabled
#define MPU_PROTENSET0_PROTREG15_Pos BPROT_CONFIG0_REGION15_Pos
#define MPU_PROTENSET0_PROTREG15_Msk BPROT_CONFIG0_REGION15_Msk
#define MPU_PROTENSET0_PROTREG15_Disabled BPROT_CONFIG0_REGION15_Disabled
#define MPU_PROTENSET0_PROTREG15_Enabled BPROT_CONFIG0_REGION15_Enabled
#define MPU_PROTENSET0_PROTREG15_Set BPROT_CONFIG0_REGION15_Enabled
#define MPU_PROTENSET0_PROTREG14_Pos BPROT_CONFIG0_REGION14_Pos
#define MPU_PROTENSET0_PROTREG14_Msk BPROT_CONFIG0_REGION14_Msk
#define MPU_PROTENSET0_PROTREG14_Disabled BPROT_CONFIG0_REGION14_Disabled
#define MPU_PROTENSET0_PROTREG14_Enabled BPROT_CONFIG0_REGION14_Enabled
#define MPU_PROTENSET0_PROTREG14_Set BPROT_CONFIG0_REGION14_Enabled
#define MPU_PROTENSET0_PROTREG13_Pos BPROT_CONFIG0_REGION13_Pos
#define MPU_PROTENSET0_PROTREG13_Msk BPROT_CONFIG0_REGION13_Msk
#define MPU_PROTENSET0_PROTREG13_Disabled BPROT_CONFIG0_REGION13_Disabled
#define MPU_PROTENSET0_PROTREG13_Enabled BPROT_CONFIG0_REGION13_Enabled
#define MPU_PROTENSET0_PROTREG13_Set BPROT_CONFIG0_REGION13_Enabled
#define MPU_PROTENSET0_PROTREG12_Pos BPROT_CONFIG0_REGION12_Pos
#define MPU_PROTENSET0_PROTREG12_Msk BPROT_CONFIG0_REGION12_Msk
#define MPU_PROTENSET0_PROTREG12_Disabled BPROT_CONFIG0_REGION12_Disabled
#define MPU_PROTENSET0_PROTREG12_Enabled BPROT_CONFIG0_REGION12_Enabled
#define MPU_PROTENSET0_PROTREG12_Set BPROT_CONFIG0_REGION12_Enabled
#define MPU_PROTENSET0_PROTREG11_Pos BPROT_CONFIG0_REGION11_Pos
#define MPU_PROTENSET0_PROTREG11_Msk BPROT_CONFIG0_REGION11_Msk
#define MPU_PROTENSET0_PROTREG11_Disabled BPROT_CONFIG0_REGION11_Disabled
#define MPU_PROTENSET0_PROTREG11_Enabled BPROT_CONFIG0_REGION11_Enabled
#define MPU_PROTENSET0_PROTREG11_Set BPROT_CONFIG0_REGION11_Enabled
#define MPU_PROTENSET0_PROTREG10_Pos BPROT_CONFIG0_REGION10_Pos
#define MPU_PROTENSET0_PROTREG10_Msk BPROT_CONFIG0_REGION10_Msk
#define MPU_PROTENSET0_PROTREG10_Disabled BPROT_CONFIG0_REGION10_Disabled
#define MPU_PROTENSET0_PROTREG10_Enabled BPROT_CONFIG0_REGION10_Enabled
#define MPU_PROTENSET0_PROTREG10_Set BPROT_CONFIG0_REGION10_Enabled
#define MPU_PROTENSET0_PROTREG9_Pos BPROT_CONFIG0_REGION9_Pos
#define MPU_PROTENSET0_PROTREG9_Msk BPROT_CONFIG0_REGION9_Msk
#define MPU_PROTENSET0_PROTREG9_Disabled BPROT_CONFIG0_REGION9_Disabled
#define MPU_PROTENSET0_PROTREG9_Enabled BPROT_CONFIG0_REGION9_Enabled
#define MPU_PROTENSET0_PROTREG9_Set BPROT_CONFIG0_REGION9_Enabled
#define MPU_PROTENSET0_PROTREG8_Pos BPROT_CONFIG0_REGION8_Pos
#define MPU_PROTENSET0_PROTREG8_Msk BPROT_CONFIG0_REGION8_Msk
#define MPU_PROTENSET0_PROTREG8_Disabled BPROT_CONFIG0_REGION8_Disabled
#define MPU_PROTENSET0_PROTREG8_Enabled BPROT_CONFIG0_REGION8_Enabled
#define MPU_PROTENSET0_PROTREG8_Set BPROT_CONFIG0_REGION8_Enabled
#define MPU_PROTENSET0_PROTREG7_Pos BPROT_CONFIG0_REGION7_Pos
#define MPU_PROTENSET0_PROTREG7_Msk BPROT_CONFIG0_REGION7_Msk
#define MPU_PROTENSET0_PROTREG7_Disabled BPROT_CONFIG0_REGION7_Disabled
#define MPU_PROTENSET0_PROTREG7_Enabled BPROT_CONFIG0_REGION7_Enabled
#define MPU_PROTENSET0_PROTREG7_Set BPROT_CONFIG0_REGION7_Enabled
#define MPU_PROTENSET0_PROTREG6_Pos BPROT_CONFIG0_REGION6_Pos
#define MPU_PROTENSET0_PROTREG6_Msk BPROT_CONFIG0_REGION6_Msk
#define MPU_PROTENSET0_PROTREG6_Disabled BPROT_CONFIG0_REGION6_Disabled
#define MPU_PROTENSET0_PROTREG6_Enabled BPROT_CONFIG0_REGION6_Enabled
#define MPU_PROTENSET0_PROTREG6_Set BPROT_CONFIG0_REGION6_Enabled
#define MPU_PROTENSET0_PROTREG5_Pos BPROT_CONFIG0_REGION5_Pos
#define MPU_PROTENSET0_PROTREG5_Msk BPROT_CONFIG0_REGION5_Msk
#define MPU_PROTENSET0_PROTREG5_Disabled BPROT_CONFIG0_REGION5_Disabled
#define MPU_PROTENSET0_PROTREG5_Enabled BPROT_CONFIG0_REGION5_Enabled
#define MPU_PROTENSET0_PROTREG5_Set BPROT_CONFIG0_REGION5_Enabled
#define MPU_PROTENSET0_PROTREG4_Pos BPROT_CONFIG0_REGION4_Pos
#define MPU_PROTENSET0_PROTREG4_Msk BPROT_CONFIG0_REGION4_Msk
#define MPU_PROTENSET0_PROTREG4_Disabled BPROT_CONFIG0_REGION4_Disabled
#define MPU_PROTENSET0_PROTREG4_Enabled BPROT_CONFIG0_REGION4_Enabled
#define MPU_PROTENSET0_PROTREG4_Set BPROT_CONFIG0_REGION4_Enabled
#define MPU_PROTENSET0_PROTREG3_Pos BPROT_CONFIG0_REGION3_Pos
#define MPU_PROTENSET0_PROTREG3_Msk BPROT_CONFIG0_REGION3_Msk
#define MPU_PROTENSET0_PROTREG3_Disabled BPROT_CONFIG0_REGION3_Disabled
#define MPU_PROTENSET0_PROTREG3_Enabled BPROT_CONFIG0_REGION3_Enabled
#define MPU_PROTENSET0_PROTREG3_Set BPROT_CONFIG0_REGION3_Enabled
#define MPU_PROTENSET0_PROTREG2_Pos BPROT_CONFIG0_REGION2_Pos
#define MPU_PROTENSET0_PROTREG2_Msk BPROT_CONFIG0_REGION2_Msk
#define MPU_PROTENSET0_PROTREG2_Disabled BPROT_CONFIG0_REGION2_Disabled
#define MPU_PROTENSET0_PROTREG2_Enabled BPROT_CONFIG0_REGION2_Enabled
#define MPU_PROTENSET0_PROTREG2_Set BPROT_CONFIG0_REGION2_Enabled
#define MPU_PROTENSET0_PROTREG1_Pos BPROT_CONFIG0_REGION1_Pos
#define MPU_PROTENSET0_PROTREG1_Msk BPROT_CONFIG0_REGION1_Msk
#define MPU_PROTENSET0_PROTREG1_Disabled BPROT_CONFIG0_REGION1_Disabled
#define MPU_PROTENSET0_PROTREG1_Enabled BPROT_CONFIG0_REGION1_Enabled
#define MPU_PROTENSET0_PROTREG1_Set BPROT_CONFIG0_REGION1_Enabled
#define MPU_PROTENSET0_PROTREG0_Pos BPROT_CONFIG0_REGION0_Pos
#define MPU_PROTENSET0_PROTREG0_Msk BPROT_CONFIG0_REGION0_Msk
#define MPU_PROTENSET0_PROTREG0_Disabled BPROT_CONFIG0_REGION0_Disabled
#define MPU_PROTENSET0_PROTREG0_Enabled BPROT_CONFIG0_REGION0_Enabled
#define MPU_PROTENSET0_PROTREG0_Set BPROT_CONFIG0_REGION0_Enabled
/* From nrf51_deprecated.h */
/* NVMC */
/* The register ERASEPROTECTEDPAGE changed name to ERASEPCR0 in the documentation. */
#define ERASEPROTECTEDPAGE ERASEPCR0
/* IRQ */
/* COMP module was eliminated. Adapted to nrf52 headers. */
#define LPCOMP_COMP_IRQHandler COMP_LPCOMP_IRQHandler
#define LPCOMP_COMP_IRQn COMP_LPCOMP_IRQn
/* REFSEL register redefined enumerated values and added some more. */
#define LPCOMP_REFSEL_REFSEL_SupplyOneEighthPrescaling LPCOMP_REFSEL_REFSEL_Ref1_8Vdd
#define LPCOMP_REFSEL_REFSEL_SupplyTwoEighthsPrescaling LPCOMP_REFSEL_REFSEL_Ref2_8Vdd
#define LPCOMP_REFSEL_REFSEL_SupplyThreeEighthsPrescaling LPCOMP_REFSEL_REFSEL_Ref3_8Vdd
#define LPCOMP_REFSEL_REFSEL_SupplyFourEighthsPrescaling LPCOMP_REFSEL_REFSEL_Ref4_8Vdd
#define LPCOMP_REFSEL_REFSEL_SupplyFiveEighthsPrescaling LPCOMP_REFSEL_REFSEL_Ref5_8Vdd
#define LPCOMP_REFSEL_REFSEL_SupplySixEighthsPrescaling LPCOMP_REFSEL_REFSEL_Ref6_8Vdd
#define LPCOMP_REFSEL_REFSEL_SupplySevenEighthsPrescaling LPCOMP_REFSEL_REFSEL_Ref7_8Vdd
/* RADIO */
/* The name of the field SKIPADDR was corrected. Old macros added for compatibility. */
#define RADIO_CRCCNF_SKIP_ADDR_Pos RADIO_CRCCNF_SKIPADDR_Pos
#define RADIO_CRCCNF_SKIP_ADDR_Msk RADIO_CRCCNF_SKIPADDR_Msk
#define RADIO_CRCCNF_SKIP_ADDR_Include RADIO_CRCCNF_SKIPADDR_Include
#define RADIO_CRCCNF_SKIP_ADDR_Skip RADIO_CRCCNF_SKIPADDR_Skip
/* FICR */
/* The registers FICR.DEVICEID0 and FICR.DEVICEID1 were renamed into an array. */
#define DEVICEID0 DEVICEID[0]
#define DEVICEID1 DEVICEID[1]
/* The registers FICR.ER0, FICR.ER1, FICR.ER2 and FICR.ER3 were renamed into an array. */
#define ER0 ER[0]
#define ER1 ER[1]
#define ER2 ER[2]
#define ER3 ER[3]
/* The registers FICR.IR0, FICR.IR1, FICR.IR2 and FICR.IR3 were renamed into an array. */
#define IR0 IR[0]
#define IR1 IR[1]
#define IR2 IR[2]
#define IR3 IR[3]
/* The registers FICR.DEVICEADDR0 and FICR.DEVICEADDR1 were renamed into an array. */
#define DEVICEADDR0 DEVICEADDR[0]
#define DEVICEADDR1 DEVICEADDR[1]
/* PPI */
/* The tasks PPI.TASKS_CHGxEN and PPI.TASKS_CHGxDIS were renamed into an array of structs. */
#define TASKS_CHG0EN TASKS_CHG[0].EN
#define TASKS_CHG0DIS TASKS_CHG[0].DIS
#define TASKS_CHG1EN TASKS_CHG[1].EN
#define TASKS_CHG1DIS TASKS_CHG[1].DIS
#define TASKS_CHG2EN TASKS_CHG[2].EN
#define TASKS_CHG2DIS TASKS_CHG[2].DIS
#define TASKS_CHG3EN TASKS_CHG[3].EN
#define TASKS_CHG3DIS TASKS_CHG[3].DIS
/* The registers PPI.CHx_EEP and PPI.CHx_TEP were renamed into an array of structs. */
#define CH0_EEP CH[0].EEP
#define CH0_TEP CH[0].TEP
#define CH1_EEP CH[1].EEP
#define CH1_TEP CH[1].TEP
#define CH2_EEP CH[2].EEP
#define CH2_TEP CH[2].TEP
#define CH3_EEP CH[3].EEP
#define CH3_TEP CH[3].TEP
#define CH4_EEP CH[4].EEP
#define CH4_TEP CH[4].TEP
#define CH5_EEP CH[5].EEP
#define CH5_TEP CH[5].TEP
#define CH6_EEP CH[6].EEP
#define CH6_TEP CH[6].TEP
#define CH7_EEP CH[7].EEP
#define CH7_TEP CH[7].TEP
#define CH8_EEP CH[8].EEP
#define CH8_TEP CH[8].TEP
#define CH9_EEP CH[9].EEP
#define CH9_TEP CH[9].TEP
#define CH10_EEP CH[10].EEP
#define CH10_TEP CH[10].TEP
#define CH11_EEP CH[11].EEP
#define CH11_TEP CH[11].TEP
#define CH12_EEP CH[12].EEP
#define CH12_TEP CH[12].TEP
#define CH13_EEP CH[13].EEP
#define CH13_TEP CH[13].TEP
#define CH14_EEP CH[14].EEP
#define CH14_TEP CH[14].TEP
#define CH15_EEP CH[15].EEP
#define CH15_TEP CH[15].TEP
/* The registers PPI.CHG0, PPI.CHG1, PPI.CHG2 and PPI.CHG3 were renamed into an array. */
#define CHG0 CHG[0]
#define CHG1 CHG[1]
#define CHG2 CHG[2]
#define CHG3 CHG[3]
/* All bitfield macros for the CHGx registers therefore changed name. */
#define PPI_CHG0_CH15_Pos PPI_CHG_CH15_Pos
#define PPI_CHG0_CH15_Msk PPI_CHG_CH15_Msk
#define PPI_CHG0_CH15_Excluded PPI_CHG_CH15_Excluded
#define PPI_CHG0_CH15_Included PPI_CHG_CH15_Included
#define PPI_CHG0_CH14_Pos PPI_CHG_CH14_Pos
#define PPI_CHG0_CH14_Msk PPI_CHG_CH14_Msk
#define PPI_CHG0_CH14_Excluded PPI_CHG_CH14_Excluded
#define PPI_CHG0_CH14_Included PPI_CHG_CH14_Included
#define PPI_CHG0_CH13_Pos PPI_CHG_CH13_Pos
#define PPI_CHG0_CH13_Msk PPI_CHG_CH13_Msk
#define PPI_CHG0_CH13_Excluded PPI_CHG_CH13_Excluded
#define PPI_CHG0_CH13_Included PPI_CHG_CH13_Included
#define PPI_CHG0_CH12_Pos PPI_CHG_CH12_Pos
#define PPI_CHG0_CH12_Msk PPI_CHG_CH12_Msk
#define PPI_CHG0_CH12_Excluded PPI_CHG_CH12_Excluded
#define PPI_CHG0_CH12_Included PPI_CHG_CH12_Included
#define PPI_CHG0_CH11_Pos PPI_CHG_CH11_Pos
#define PPI_CHG0_CH11_Msk PPI_CHG_CH11_Msk
#define PPI_CHG0_CH11_Excluded PPI_CHG_CH11_Excluded
#define PPI_CHG0_CH11_Included PPI_CHG_CH11_Included
#define PPI_CHG0_CH10_Pos PPI_CHG_CH10_Pos
#define PPI_CHG0_CH10_Msk PPI_CHG_CH10_Msk
#define PPI_CHG0_CH10_Excluded PPI_CHG_CH10_Excluded
#define PPI_CHG0_CH10_Included PPI_CHG_CH10_Included
#define PPI_CHG0_CH9_Pos PPI_CHG_CH9_Pos
#define PPI_CHG0_CH9_Msk PPI_CHG_CH9_Msk
#define PPI_CHG0_CH9_Excluded PPI_CHG_CH9_Excluded
#define PPI_CHG0_CH9_Included PPI_CHG_CH9_Included
#define PPI_CHG0_CH8_Pos PPI_CHG_CH8_Pos
#define PPI_CHG0_CH8_Msk PPI_CHG_CH8_Msk
#define PPI_CHG0_CH8_Excluded PPI_CHG_CH8_Excluded
#define PPI_CHG0_CH8_Included PPI_CHG_CH8_Included
#define PPI_CHG0_CH7_Pos PPI_CHG_CH7_Pos
#define PPI_CHG0_CH7_Msk PPI_CHG_CH7_Msk
#define PPI_CHG0_CH7_Excluded PPI_CHG_CH7_Excluded
#define PPI_CHG0_CH7_Included PPI_CHG_CH7_Included
#define PPI_CHG0_CH6_Pos PPI_CHG_CH6_Pos
#define PPI_CHG0_CH6_Msk PPI_CHG_CH6_Msk
#define PPI_CHG0_CH6_Excluded PPI_CHG_CH6_Excluded
#define PPI_CHG0_CH6_Included PPI_CHG_CH6_Included
#define PPI_CHG0_CH5_Pos PPI_CHG_CH5_Pos
#define PPI_CHG0_CH5_Msk PPI_CHG_CH5_Msk
#define PPI_CHG0_CH5_Excluded PPI_CHG_CH5_Excluded
#define PPI_CHG0_CH5_Included PPI_CHG_CH5_Included
#define PPI_CHG0_CH4_Pos PPI_CHG_CH4_Pos
#define PPI_CHG0_CH4_Msk PPI_CHG_CH4_Msk
#define PPI_CHG0_CH4_Excluded PPI_CHG_CH4_Excluded
#define PPI_CHG0_CH4_Included PPI_CHG_CH4_Included
#define PPI_CHG0_CH3_Pos PPI_CHG_CH3_Pos
#define PPI_CHG0_CH3_Msk PPI_CHG_CH3_Msk
#define PPI_CHG0_CH3_Excluded PPI_CHG_CH3_Excluded
#define PPI_CHG0_CH3_Included PPI_CHG_CH3_Included
#define PPI_CHG0_CH2_Pos PPI_CHG_CH2_Pos
#define PPI_CHG0_CH2_Msk PPI_CHG_CH2_Msk
#define PPI_CHG0_CH2_Excluded PPI_CHG_CH2_Excluded
#define PPI_CHG0_CH2_Included PPI_CHG_CH2_Included
#define PPI_CHG0_CH1_Pos PPI_CHG_CH1_Pos
#define PPI_CHG0_CH1_Msk PPI_CHG_CH1_Msk
#define PPI_CHG0_CH1_Excluded PPI_CHG_CH1_Excluded
#define PPI_CHG0_CH1_Included PPI_CHG_CH1_Included
#define PPI_CHG0_CH0_Pos PPI_CHG_CH0_Pos
#define PPI_CHG0_CH0_Msk PPI_CHG_CH0_Msk
#define PPI_CHG0_CH0_Excluded PPI_CHG_CH0_Excluded
#define PPI_CHG0_CH0_Included PPI_CHG_CH0_Included
#define PPI_CHG1_CH15_Pos PPI_CHG_CH15_Pos
#define PPI_CHG1_CH15_Msk PPI_CHG_CH15_Msk
#define PPI_CHG1_CH15_Excluded PPI_CHG_CH15_Excluded
#define PPI_CHG1_CH15_Included PPI_CHG_CH15_Included
#define PPI_CHG1_CH14_Pos PPI_CHG_CH14_Pos
#define PPI_CHG1_CH14_Msk PPI_CHG_CH14_Msk
#define PPI_CHG1_CH14_Excluded PPI_CHG_CH14_Excluded
#define PPI_CHG1_CH14_Included PPI_CHG_CH14_Included
#define PPI_CHG1_CH13_Pos PPI_CHG_CH13_Pos
#define PPI_CHG1_CH13_Msk PPI_CHG_CH13_Msk
#define PPI_CHG1_CH13_Excluded PPI_CHG_CH13_Excluded
#define PPI_CHG1_CH13_Included PPI_CHG_CH13_Included
#define PPI_CHG1_CH12_Pos PPI_CHG_CH12_Pos
#define PPI_CHG1_CH12_Msk PPI_CHG_CH12_Msk
#define PPI_CHG1_CH12_Excluded PPI_CHG_CH12_Excluded
#define PPI_CHG1_CH12_Included PPI_CHG_CH12_Included
#define PPI_CHG1_CH11_Pos PPI_CHG_CH11_Pos
#define PPI_CHG1_CH11_Msk PPI_CHG_CH11_Msk
#define PPI_CHG1_CH11_Excluded PPI_CHG_CH11_Excluded
#define PPI_CHG1_CH11_Included PPI_CHG_CH11_Included
#define PPI_CHG1_CH10_Pos PPI_CHG_CH10_Pos
#define PPI_CHG1_CH10_Msk PPI_CHG_CH10_Msk
#define PPI_CHG1_CH10_Excluded PPI_CHG_CH10_Excluded
#define PPI_CHG1_CH10_Included PPI_CHG_CH10_Included
#define PPI_CHG1_CH9_Pos PPI_CHG_CH9_Pos
#define PPI_CHG1_CH9_Msk PPI_CHG_CH9_Msk
#define PPI_CHG1_CH9_Excluded PPI_CHG_CH9_Excluded
#define PPI_CHG1_CH9_Included PPI_CHG_CH9_Included
#define PPI_CHG1_CH8_Pos PPI_CHG_CH8_Pos
#define PPI_CHG1_CH8_Msk PPI_CHG_CH8_Msk
#define PPI_CHG1_CH8_Excluded PPI_CHG_CH8_Excluded
#define PPI_CHG1_CH8_Included PPI_CHG_CH8_Included
#define PPI_CHG1_CH7_Pos PPI_CHG_CH7_Pos
#define PPI_CHG1_CH7_Msk PPI_CHG_CH7_Msk
#define PPI_CHG1_CH7_Excluded PPI_CHG_CH7_Excluded
#define PPI_CHG1_CH7_Included PPI_CHG_CH7_Included
#define PPI_CHG1_CH6_Pos PPI_CHG_CH6_Pos
#define PPI_CHG1_CH6_Msk PPI_CHG_CH6_Msk
#define PPI_CHG1_CH6_Excluded PPI_CHG_CH6_Excluded
#define PPI_CHG1_CH6_Included PPI_CHG_CH6_Included
#define PPI_CHG1_CH5_Pos PPI_CHG_CH5_Pos
#define PPI_CHG1_CH5_Msk PPI_CHG_CH5_Msk
#define PPI_CHG1_CH5_Excluded PPI_CHG_CH5_Excluded
#define PPI_CHG1_CH5_Included PPI_CHG_CH5_Included
#define PPI_CHG1_CH4_Pos PPI_CHG_CH4_Pos
#define PPI_CHG1_CH4_Msk PPI_CHG_CH4_Msk
#define PPI_CHG1_CH4_Excluded PPI_CHG_CH4_Excluded
#define PPI_CHG1_CH4_Included PPI_CHG_CH4_Included
#define PPI_CHG1_CH3_Pos PPI_CHG_CH3_Pos
#define PPI_CHG1_CH3_Msk PPI_CHG_CH3_Msk
#define PPI_CHG1_CH3_Excluded PPI_CHG_CH3_Excluded
#define PPI_CHG1_CH3_Included PPI_CHG_CH3_Included
#define PPI_CHG1_CH2_Pos PPI_CHG_CH2_Pos
#define PPI_CHG1_CH2_Msk PPI_CHG_CH2_Msk
#define PPI_CHG1_CH2_Excluded PPI_CHG_CH2_Excluded
#define PPI_CHG1_CH2_Included PPI_CHG_CH2_Included
#define PPI_CHG1_CH1_Pos PPI_CHG_CH1_Pos
#define PPI_CHG1_CH1_Msk PPI_CHG_CH1_Msk
#define PPI_CHG1_CH1_Excluded PPI_CHG_CH1_Excluded
#define PPI_CHG1_CH1_Included PPI_CHG_CH1_Included
#define PPI_CHG1_CH0_Pos PPI_CHG_CH0_Pos
#define PPI_CHG1_CH0_Msk PPI_CHG_CH0_Msk
#define PPI_CHG1_CH0_Excluded PPI_CHG_CH0_Excluded
#define PPI_CHG1_CH0_Included PPI_CHG_CH0_Included
#define PPI_CHG2_CH15_Pos PPI_CHG_CH15_Pos
#define PPI_CHG2_CH15_Msk PPI_CHG_CH15_Msk
#define PPI_CHG2_CH15_Excluded PPI_CHG_CH15_Excluded
#define PPI_CHG2_CH15_Included PPI_CHG_CH15_Included
#define PPI_CHG2_CH14_Pos PPI_CHG_CH14_Pos
#define PPI_CHG2_CH14_Msk PPI_CHG_CH14_Msk
#define PPI_CHG2_CH14_Excluded PPI_CHG_CH14_Excluded
#define PPI_CHG2_CH14_Included PPI_CHG_CH14_Included
#define PPI_CHG2_CH13_Pos PPI_CHG_CH13_Pos
#define PPI_CHG2_CH13_Msk PPI_CHG_CH13_Msk
#define PPI_CHG2_CH13_Excluded PPI_CHG_CH13_Excluded
#define PPI_CHG2_CH13_Included PPI_CHG_CH13_Included
#define PPI_CHG2_CH12_Pos PPI_CHG_CH12_Pos
#define PPI_CHG2_CH12_Msk PPI_CHG_CH12_Msk
#define PPI_CHG2_CH12_Excluded PPI_CHG_CH12_Excluded
#define PPI_CHG2_CH12_Included PPI_CHG_CH12_Included
#define PPI_CHG2_CH11_Pos PPI_CHG_CH11_Pos
#define PPI_CHG2_CH11_Msk PPI_CHG_CH11_Msk
#define PPI_CHG2_CH11_Excluded PPI_CHG_CH11_Excluded
#define PPI_CHG2_CH11_Included PPI_CHG_CH11_Included
#define PPI_CHG2_CH10_Pos PPI_CHG_CH10_Pos
#define PPI_CHG2_CH10_Msk PPI_CHG_CH10_Msk
#define PPI_CHG2_CH10_Excluded PPI_CHG_CH10_Excluded
#define PPI_CHG2_CH10_Included PPI_CHG_CH10_Included
#define PPI_CHG2_CH9_Pos PPI_CHG_CH9_Pos
#define PPI_CHG2_CH9_Msk PPI_CHG_CH9_Msk
#define PPI_CHG2_CH9_Excluded PPI_CHG_CH9_Excluded
#define PPI_CHG2_CH9_Included PPI_CHG_CH9_Included
#define PPI_CHG2_CH8_Pos PPI_CHG_CH8_Pos
#define PPI_CHG2_CH8_Msk PPI_CHG_CH8_Msk
#define PPI_CHG2_CH8_Excluded PPI_CHG_CH8_Excluded
#define PPI_CHG2_CH8_Included PPI_CHG_CH8_Included
#define PPI_CHG2_CH7_Pos PPI_CHG_CH7_Pos
#define PPI_CHG2_CH7_Msk PPI_CHG_CH7_Msk
#define PPI_CHG2_CH7_Excluded PPI_CHG_CH7_Excluded
#define PPI_CHG2_CH7_Included PPI_CHG_CH7_Included
#define PPI_CHG2_CH6_Pos PPI_CHG_CH6_Pos
#define PPI_CHG2_CH6_Msk PPI_CHG_CH6_Msk
#define PPI_CHG2_CH6_Excluded PPI_CHG_CH6_Excluded
#define PPI_CHG2_CH6_Included PPI_CHG_CH6_Included
#define PPI_CHG2_CH5_Pos PPI_CHG_CH5_Pos
#define PPI_CHG2_CH5_Msk PPI_CHG_CH5_Msk
#define PPI_CHG2_CH5_Excluded PPI_CHG_CH5_Excluded
#define PPI_CHG2_CH5_Included PPI_CHG_CH5_Included
#define PPI_CHG2_CH4_Pos PPI_CHG_CH4_Pos
#define PPI_CHG2_CH4_Msk PPI_CHG_CH4_Msk
#define PPI_CHG2_CH4_Excluded PPI_CHG_CH4_Excluded
#define PPI_CHG2_CH4_Included PPI_CHG_CH4_Included
#define PPI_CHG2_CH3_Pos PPI_CHG_CH3_Pos
#define PPI_CHG2_CH3_Msk PPI_CHG_CH3_Msk
#define PPI_CHG2_CH3_Excluded PPI_CHG_CH3_Excluded
#define PPI_CHG2_CH3_Included PPI_CHG_CH3_Included
#define PPI_CHG2_CH2_Pos PPI_CHG_CH2_Pos
#define PPI_CHG2_CH2_Msk PPI_CHG_CH2_Msk
#define PPI_CHG2_CH2_Excluded PPI_CHG_CH2_Excluded
#define PPI_CHG2_CH2_Included PPI_CHG_CH2_Included
#define PPI_CHG2_CH1_Pos PPI_CHG_CH1_Pos
#define PPI_CHG2_CH1_Msk PPI_CHG_CH1_Msk
#define PPI_CHG2_CH1_Excluded PPI_CHG_CH1_Excluded
#define PPI_CHG2_CH1_Included PPI_CHG_CH1_Included
#define PPI_CHG2_CH0_Pos PPI_CHG_CH0_Pos
#define PPI_CHG2_CH0_Msk PPI_CHG_CH0_Msk
#define PPI_CHG2_CH0_Excluded PPI_CHG_CH0_Excluded
#define PPI_CHG2_CH0_Included PPI_CHG_CH0_Included
#define PPI_CHG3_CH15_Pos PPI_CHG_CH15_Pos
#define PPI_CHG3_CH15_Msk PPI_CHG_CH15_Msk
#define PPI_CHG3_CH15_Excluded PPI_CHG_CH15_Excluded
#define PPI_CHG3_CH15_Included PPI_CHG_CH15_Included
#define PPI_CHG3_CH14_Pos PPI_CHG_CH14_Pos
#define PPI_CHG3_CH14_Msk PPI_CHG_CH14_Msk
#define PPI_CHG3_CH14_Excluded PPI_CHG_CH14_Excluded
#define PPI_CHG3_CH14_Included PPI_CHG_CH14_Included
#define PPI_CHG3_CH13_Pos PPI_CHG_CH13_Pos
#define PPI_CHG3_CH13_Msk PPI_CHG_CH13_Msk
#define PPI_CHG3_CH13_Excluded PPI_CHG_CH13_Excluded
#define PPI_CHG3_CH13_Included PPI_CHG_CH13_Included
#define PPI_CHG3_CH12_Pos PPI_CHG_CH12_Pos
#define PPI_CHG3_CH12_Msk PPI_CHG_CH12_Msk
#define PPI_CHG3_CH12_Excluded PPI_CHG_CH12_Excluded
#define PPI_CHG3_CH12_Included PPI_CHG_CH12_Included
#define PPI_CHG3_CH11_Pos PPI_CHG_CH11_Pos
#define PPI_CHG3_CH11_Msk PPI_CHG_CH11_Msk
#define PPI_CHG3_CH11_Excluded PPI_CHG_CH11_Excluded
#define PPI_CHG3_CH11_Included PPI_CHG_CH11_Included
#define PPI_CHG3_CH10_Pos PPI_CHG_CH10_Pos
#define PPI_CHG3_CH10_Msk PPI_CHG_CH10_Msk
#define PPI_CHG3_CH10_Excluded PPI_CHG_CH10_Excluded
#define PPI_CHG3_CH10_Included PPI_CHG_CH10_Included
#define PPI_CHG3_CH9_Pos PPI_CHG_CH9_Pos
#define PPI_CHG3_CH9_Msk PPI_CHG_CH9_Msk
#define PPI_CHG3_CH9_Excluded PPI_CHG_CH9_Excluded
#define PPI_CHG3_CH9_Included PPI_CHG_CH9_Included
#define PPI_CHG3_CH8_Pos PPI_CHG_CH8_Pos
#define PPI_CHG3_CH8_Msk PPI_CHG_CH8_Msk
#define PPI_CHG3_CH8_Excluded PPI_CHG_CH8_Excluded
#define PPI_CHG3_CH8_Included PPI_CHG_CH8_Included
#define PPI_CHG3_CH7_Pos PPI_CHG_CH7_Pos
#define PPI_CHG3_CH7_Msk PPI_CHG_CH7_Msk
#define PPI_CHG3_CH7_Excluded PPI_CHG_CH7_Excluded
#define PPI_CHG3_CH7_Included PPI_CHG_CH7_Included
#define PPI_CHG3_CH6_Pos PPI_CHG_CH6_Pos
#define PPI_CHG3_CH6_Msk PPI_CHG_CH6_Msk
#define PPI_CHG3_CH6_Excluded PPI_CHG_CH6_Excluded
#define PPI_CHG3_CH6_Included PPI_CHG_CH6_Included
#define PPI_CHG3_CH5_Pos PPI_CHG_CH5_Pos
#define PPI_CHG3_CH5_Msk PPI_CHG_CH5_Msk
#define PPI_CHG3_CH5_Excluded PPI_CHG_CH5_Excluded
#define PPI_CHG3_CH5_Included PPI_CHG_CH5_Included
#define PPI_CHG3_CH4_Pos PPI_CHG_CH4_Pos
#define PPI_CHG3_CH4_Msk PPI_CHG_CH4_Msk
#define PPI_CHG3_CH4_Excluded PPI_CHG_CH4_Excluded
#define PPI_CHG3_CH4_Included PPI_CHG_CH4_Included
#define PPI_CHG3_CH3_Pos PPI_CHG_CH3_Pos
#define PPI_CHG3_CH3_Msk PPI_CHG_CH3_Msk
#define PPI_CHG3_CH3_Excluded PPI_CHG_CH3_Excluded
#define PPI_CHG3_CH3_Included PPI_CHG_CH3_Included
#define PPI_CHG3_CH2_Pos PPI_CHG_CH2_Pos
#define PPI_CHG3_CH2_Msk PPI_CHG_CH2_Msk
#define PPI_CHG3_CH2_Excluded PPI_CHG_CH2_Excluded
#define PPI_CHG3_CH2_Included PPI_CHG_CH2_Included
#define PPI_CHG3_CH1_Pos PPI_CHG_CH1_Pos
#define PPI_CHG3_CH1_Msk PPI_CHG_CH1_Msk
#define PPI_CHG3_CH1_Excluded PPI_CHG_CH1_Excluded
#define PPI_CHG3_CH1_Included PPI_CHG_CH1_Included
#define PPI_CHG3_CH0_Pos PPI_CHG_CH0_Pos
#define PPI_CHG3_CH0_Msk PPI_CHG_CH0_Msk
#define PPI_CHG3_CH0_Excluded PPI_CHG_CH0_Excluded
#define PPI_CHG3_CH0_Included PPI_CHG_CH0_Included
/*lint --flb "Leave library region" */
#endif /* NRF51_TO_NRF52_H */

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ports/nrf/device/nrf52/nrf51_to_nrf52840.h
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@ -1,567 +0,0 @@
/* Copyright (c) 2016, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* * Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* * Neither the name of Nordic Semiconductor ASA nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifndef NRF51_TO_NRF52840_H
#define NRF51_TO_NRF52840_H
/*lint ++flb "Enter library region */
/* This file is given to prevent your SW from not compiling with the name changes between nRF51 and nRF52840 devices.
* It redefines the old nRF51 names into the new ones as long as the functionality is still supported. If the
* functionality is gone, there old names are not defined, so compilation will fail. Note that also includes macros
* from the nrf51_deprecated.h file. */
/* IRQ */
/* Several peripherals have been added to several indexes. Names of IRQ handlers and IRQ numbers have changed. */
#define UART0_IRQHandler UARTE0_UART0_IRQHandler
#define SPI0_TWI0_IRQHandler SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler
#define SPI1_TWI1_IRQHandler SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler
#define ADC_IRQHandler SAADC_IRQHandler
#define LPCOMP_IRQHandler COMP_LPCOMP_IRQHandler
#define SWI0_IRQHandler SWI0_EGU0_IRQHandler
#define SWI1_IRQHandler SWI1_EGU1_IRQHandler
#define SWI2_IRQHandler SWI2_EGU2_IRQHandler
#define SWI3_IRQHandler SWI3_EGU3_IRQHandler
#define SWI4_IRQHandler SWI4_EGU4_IRQHandler
#define SWI5_IRQHandler SWI5_EGU5_IRQHandler
#define UART0_IRQn UARTE0_UART0_IRQn
#define SPI0_TWI0_IRQn SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQn
#define SPI1_TWI1_IRQn SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQn
#define ADC_IRQn SAADC_IRQn
#define LPCOMP_IRQn COMP_LPCOMP_IRQn
#define SWI0_IRQn SWI0_EGU0_IRQn
#define SWI1_IRQn SWI1_EGU1_IRQn
#define SWI2_IRQn SWI2_EGU2_IRQn
#define SWI3_IRQn SWI3_EGU3_IRQn
#define SWI4_IRQn SWI4_EGU4_IRQn
#define SWI5_IRQn SWI5_EGU5_IRQn
/* UICR */
/* Register RBPCONF was renamed to APPROTECT. */
#define RBPCONF APPROTECT
#define UICR_RBPCONF_PALL_Pos UICR_APPROTECT_PALL_Pos
#define UICR_RBPCONF_PALL_Msk UICR_APPROTECT_PALL_Msk
#define UICR_RBPCONF_PALL_Enabled UICR_APPROTECT_PALL_Enabled
#define UICR_RBPCONF_PALL_Disabled UICR_APPROTECT_PALL_Disabled
/* GPIO */
/* GPIO port was renamed to P0. */
#define NRF_GPIO NRF_P0
#define NRF_GPIO_BASE NRF_P0_BASE
/* QDEC */
/* The registers PSELA, PSELB and PSELLED were restructured into a struct. */
#define PSELLED PSEL.LED
#define PSELA PSEL.A
#define PSELB PSEL.B
/* SPIS */
/* The registers PSELSCK, PSELMISO, PSELMOSI, PSELCSN were restructured into a struct. */
#define PSELSCK PSEL.SCK
#define PSELMISO PSEL.MISO
#define PSELMOSI PSEL.MOSI
#define PSELCSN PSEL.CSN
/* The registers RXDPTR, MAXRX, AMOUNTRX were restructured into a struct */
#define RXDPTR RXD.PTR
#define MAXRX RXD.MAXCNT
#define AMOUNTRX RXD.AMOUNT
#define SPIS_MAXRX_MAXRX_Pos SPIS_RXD_MAXCNT_MAXCNT_Pos
#define SPIS_MAXRX_MAXRX_Msk SPIS_RXD_MAXCNT_MAXCNT_Msk
#define SPIS_AMOUNTRX_AMOUNTRX_Pos SPIS_RXD_AMOUNT_AMOUNT_Pos
#define SPIS_AMOUNTRX_AMOUNTRX_Msk SPIS_RXD_AMOUNT_AMOUNT_Msk
/* The registers TXDPTR, MAXTX, AMOUNTTX were restructured into a struct */
#define TXDPTR TXD.PTR
#define MAXTX TXD.MAXCNT
#define AMOUNTTX TXD.AMOUNT
#define SPIS_MAXTX_MAXTX_Pos SPIS_TXD_MAXCNT_MAXCNT_Pos
#define SPIS_MAXTX_MAXTX_Msk SPIS_TXD_MAXCNT_MAXCNT_Msk
#define SPIS_AMOUNTTX_AMOUNTTX_Pos SPIS_TXD_AMOUNT_AMOUNT_Pos
#define SPIS_AMOUNTTX_AMOUNTTX_Msk SPIS_TXD_AMOUNT_AMOUNT_Msk
/* UART */
/* The registers PSELRTS, PSELTXD, PSELCTS, PSELRXD were restructured into a struct. */
#define PSELRTS PSEL.RTS
#define PSELTXD PSEL.TXD
#define PSELCTS PSEL.CTS
#define PSELRXD PSEL.RXD
/* TWI */
/* The registers PSELSCL, PSELSDA were restructured into a struct. */
#define PSELSCL PSEL.SCL
#define PSELSDA PSEL.SDA
/* From nrf51_deprecated.h */
/* NVMC */
/* The register ERASEPROTECTEDPAGE changed name to ERASEPCR0 in the documentation. */
#define ERASEPROTECTEDPAGE ERASEPCR0
/* IRQ */
/* COMP module was eliminated. Adapted to nrf52840 headers. */
#define LPCOMP_COMP_IRQHandler COMP_LPCOMP_IRQHandler
#define LPCOMP_COMP_IRQn COMP_LPCOMP_IRQn
/* REFSEL register redefined enumerated values and added some more. */
#define LPCOMP_REFSEL_REFSEL_SupplyOneEighthPrescaling LPCOMP_REFSEL_REFSEL_Ref1_8Vdd
#define LPCOMP_REFSEL_REFSEL_SupplyTwoEighthsPrescaling LPCOMP_REFSEL_REFSEL_Ref2_8Vdd
#define LPCOMP_REFSEL_REFSEL_SupplyThreeEighthsPrescaling LPCOMP_REFSEL_REFSEL_Ref3_8Vdd
#define LPCOMP_REFSEL_REFSEL_SupplyFourEighthsPrescaling LPCOMP_REFSEL_REFSEL_Ref4_8Vdd
#define LPCOMP_REFSEL_REFSEL_SupplyFiveEighthsPrescaling LPCOMP_REFSEL_REFSEL_Ref5_8Vdd
#define LPCOMP_REFSEL_REFSEL_SupplySixEighthsPrescaling LPCOMP_REFSEL_REFSEL_Ref6_8Vdd
#define LPCOMP_REFSEL_REFSEL_SupplySevenEighthsPrescaling LPCOMP_REFSEL_REFSEL_Ref7_8Vdd
/* RADIO */
/* The name of the field SKIPADDR was corrected. Old macros added for compatibility. */
#define RADIO_CRCCNF_SKIP_ADDR_Pos RADIO_CRCCNF_SKIPADDR_Pos
#define RADIO_CRCCNF_SKIP_ADDR_Msk RADIO_CRCCNF_SKIPADDR_Msk
#define RADIO_CRCCNF_SKIP_ADDR_Include RADIO_CRCCNF_SKIPADDR_Include
#define RADIO_CRCCNF_SKIP_ADDR_Skip RADIO_CRCCNF_SKIPADDR_Skip
/* FICR */
/* The registers FICR.DEVICEID0 and FICR.DEVICEID1 were renamed into an array. */
#define DEVICEID0 DEVICEID[0]
#define DEVICEID1 DEVICEID[1]
/* The registers FICR.ER0, FICR.ER1, FICR.ER2 and FICR.ER3 were renamed into an array. */
#define ER0 ER[0]
#define ER1 ER[1]
#define ER2 ER[2]
#define ER3 ER[3]
/* The registers FICR.IR0, FICR.IR1, FICR.IR2 and FICR.IR3 were renamed into an array. */
#define IR0 IR[0]
#define IR1 IR[1]
#define IR2 IR[2]
#define IR3 IR[3]
/* The registers FICR.DEVICEADDR0 and FICR.DEVICEADDR1 were renamed into an array. */
#define DEVICEADDR0 DEVICEADDR[0]
#define DEVICEADDR1 DEVICEADDR[1]
/* PPI */
/* The tasks PPI.TASKS_CHGxEN and PPI.TASKS_CHGxDIS were renamed into an array of structs. */
#define TASKS_CHG0EN TASKS_CHG[0].EN
#define TASKS_CHG0DIS TASKS_CHG[0].DIS
#define TASKS_CHG1EN TASKS_CHG[1].EN
#define TASKS_CHG1DIS TASKS_CHG[1].DIS
#define TASKS_CHG2EN TASKS_CHG[2].EN
#define TASKS_CHG2DIS TASKS_CHG[2].DIS
#define TASKS_CHG3EN TASKS_CHG[3].EN
#define TASKS_CHG3DIS TASKS_CHG[3].DIS
/* The registers PPI.CHx_EEP and PPI.CHx_TEP were renamed into an array of structs. */
#define CH0_EEP CH[0].EEP
#define CH0_TEP CH[0].TEP
#define CH1_EEP CH[1].EEP
#define CH1_TEP CH[1].TEP
#define CH2_EEP CH[2].EEP
#define CH2_TEP CH[2].TEP
#define CH3_EEP CH[3].EEP
#define CH3_TEP CH[3].TEP
#define CH4_EEP CH[4].EEP
#define CH4_TEP CH[4].TEP
#define CH5_EEP CH[5].EEP
#define CH5_TEP CH[5].TEP
#define CH6_EEP CH[6].EEP
#define CH6_TEP CH[6].TEP
#define CH7_EEP CH[7].EEP
#define CH7_TEP CH[7].TEP
#define CH8_EEP CH[8].EEP
#define CH8_TEP CH[8].TEP
#define CH9_EEP CH[9].EEP
#define CH9_TEP CH[9].TEP
#define CH10_EEP CH[10].EEP
#define CH10_TEP CH[10].TEP
#define CH11_EEP CH[11].EEP
#define CH11_TEP CH[11].TEP
#define CH12_EEP CH[12].EEP
#define CH12_TEP CH[12].TEP
#define CH13_EEP CH[13].EEP
#define CH13_TEP CH[13].TEP
#define CH14_EEP CH[14].EEP
#define CH14_TEP CH[14].TEP
#define CH15_EEP CH[15].EEP
#define CH15_TEP CH[15].TEP
/* The registers PPI.CHG0, PPI.CHG1, PPI.CHG2 and PPI.CHG3 were renamed into an array. */
#define CHG0 CHG[0]
#define CHG1 CHG[1]
#define CHG2 CHG[2]
#define CHG3 CHG[3]
/* All bitfield macros for the CHGx registers therefore changed name. */
#define PPI_CHG0_CH15_Pos PPI_CHG_CH15_Pos
#define PPI_CHG0_CH15_Msk PPI_CHG_CH15_Msk
#define PPI_CHG0_CH15_Excluded PPI_CHG_CH15_Excluded
#define PPI_CHG0_CH15_Included PPI_CHG_CH15_Included
#define PPI_CHG0_CH14_Pos PPI_CHG_CH14_Pos
#define PPI_CHG0_CH14_Msk PPI_CHG_CH14_Msk
#define PPI_CHG0_CH14_Excluded PPI_CHG_CH14_Excluded
#define PPI_CHG0_CH14_Included PPI_CHG_CH14_Included
#define PPI_CHG0_CH13_Pos PPI_CHG_CH13_Pos
#define PPI_CHG0_CH13_Msk PPI_CHG_CH13_Msk
#define PPI_CHG0_CH13_Excluded PPI_CHG_CH13_Excluded
#define PPI_CHG0_CH13_Included PPI_CHG_CH13_Included
#define PPI_CHG0_CH12_Pos PPI_CHG_CH12_Pos
#define PPI_CHG0_CH12_Msk PPI_CHG_CH12_Msk
#define PPI_CHG0_CH12_Excluded PPI_CHG_CH12_Excluded
#define PPI_CHG0_CH12_Included PPI_CHG_CH12_Included
#define PPI_CHG0_CH11_Pos PPI_CHG_CH11_Pos
#define PPI_CHG0_CH11_Msk PPI_CHG_CH11_Msk
#define PPI_CHG0_CH11_Excluded PPI_CHG_CH11_Excluded
#define PPI_CHG0_CH11_Included PPI_CHG_CH11_Included
#define PPI_CHG0_CH10_Pos PPI_CHG_CH10_Pos
#define PPI_CHG0_CH10_Msk PPI_CHG_CH10_Msk
#define PPI_CHG0_CH10_Excluded PPI_CHG_CH10_Excluded
#define PPI_CHG0_CH10_Included PPI_CHG_CH10_Included
#define PPI_CHG0_CH9_Pos PPI_CHG_CH9_Pos
#define PPI_CHG0_CH9_Msk PPI_CHG_CH9_Msk
#define PPI_CHG0_CH9_Excluded PPI_CHG_CH9_Excluded
#define PPI_CHG0_CH9_Included PPI_CHG_CH9_Included
#define PPI_CHG0_CH8_Pos PPI_CHG_CH8_Pos
#define PPI_CHG0_CH8_Msk PPI_CHG_CH8_Msk
#define PPI_CHG0_CH8_Excluded PPI_CHG_CH8_Excluded
#define PPI_CHG0_CH8_Included PPI_CHG_CH8_Included
#define PPI_CHG0_CH7_Pos PPI_CHG_CH7_Pos
#define PPI_CHG0_CH7_Msk PPI_CHG_CH7_Msk
#define PPI_CHG0_CH7_Excluded PPI_CHG_CH7_Excluded
#define PPI_CHG0_CH7_Included PPI_CHG_CH7_Included
#define PPI_CHG0_CH6_Pos PPI_CHG_CH6_Pos
#define PPI_CHG0_CH6_Msk PPI_CHG_CH6_Msk
#define PPI_CHG0_CH6_Excluded PPI_CHG_CH6_Excluded
#define PPI_CHG0_CH6_Included PPI_CHG_CH6_Included
#define PPI_CHG0_CH5_Pos PPI_CHG_CH5_Pos
#define PPI_CHG0_CH5_Msk PPI_CHG_CH5_Msk
#define PPI_CHG0_CH5_Excluded PPI_CHG_CH5_Excluded
#define PPI_CHG0_CH5_Included PPI_CHG_CH5_Included
#define PPI_CHG0_CH4_Pos PPI_CHG_CH4_Pos
#define PPI_CHG0_CH4_Msk PPI_CHG_CH4_Msk
#define PPI_CHG0_CH4_Excluded PPI_CHG_CH4_Excluded
#define PPI_CHG0_CH4_Included PPI_CHG_CH4_Included
#define PPI_CHG0_CH3_Pos PPI_CHG_CH3_Pos
#define PPI_CHG0_CH3_Msk PPI_CHG_CH3_Msk
#define PPI_CHG0_CH3_Excluded PPI_CHG_CH3_Excluded
#define PPI_CHG0_CH3_Included PPI_CHG_CH3_Included
#define PPI_CHG0_CH2_Pos PPI_CHG_CH2_Pos
#define PPI_CHG0_CH2_Msk PPI_CHG_CH2_Msk
#define PPI_CHG0_CH2_Excluded PPI_CHG_CH2_Excluded
#define PPI_CHG0_CH2_Included PPI_CHG_CH2_Included
#define PPI_CHG0_CH1_Pos PPI_CHG_CH1_Pos
#define PPI_CHG0_CH1_Msk PPI_CHG_CH1_Msk
#define PPI_CHG0_CH1_Excluded PPI_CHG_CH1_Excluded
#define PPI_CHG0_CH1_Included PPI_CHG_CH1_Included
#define PPI_CHG0_CH0_Pos PPI_CHG_CH0_Pos
#define PPI_CHG0_CH0_Msk PPI_CHG_CH0_Msk
#define PPI_CHG0_CH0_Excluded PPI_CHG_CH0_Excluded
#define PPI_CHG0_CH0_Included PPI_CHG_CH0_Included
#define PPI_CHG1_CH15_Pos PPI_CHG_CH15_Pos
#define PPI_CHG1_CH15_Msk PPI_CHG_CH15_Msk
#define PPI_CHG1_CH15_Excluded PPI_CHG_CH15_Excluded
#define PPI_CHG1_CH15_Included PPI_CHG_CH15_Included
#define PPI_CHG1_CH14_Pos PPI_CHG_CH14_Pos
#define PPI_CHG1_CH14_Msk PPI_CHG_CH14_Msk
#define PPI_CHG1_CH14_Excluded PPI_CHG_CH14_Excluded
#define PPI_CHG1_CH14_Included PPI_CHG_CH14_Included
#define PPI_CHG1_CH13_Pos PPI_CHG_CH13_Pos
#define PPI_CHG1_CH13_Msk PPI_CHG_CH13_Msk
#define PPI_CHG1_CH13_Excluded PPI_CHG_CH13_Excluded
#define PPI_CHG1_CH13_Included PPI_CHG_CH13_Included
#define PPI_CHG1_CH12_Pos PPI_CHG_CH12_Pos
#define PPI_CHG1_CH12_Msk PPI_CHG_CH12_Msk
#define PPI_CHG1_CH12_Excluded PPI_CHG_CH12_Excluded
#define PPI_CHG1_CH12_Included PPI_CHG_CH12_Included
#define PPI_CHG1_CH11_Pos PPI_CHG_CH11_Pos
#define PPI_CHG1_CH11_Msk PPI_CHG_CH11_Msk
#define PPI_CHG1_CH11_Excluded PPI_CHG_CH11_Excluded
#define PPI_CHG1_CH11_Included PPI_CHG_CH11_Included
#define PPI_CHG1_CH10_Pos PPI_CHG_CH10_Pos
#define PPI_CHG1_CH10_Msk PPI_CHG_CH10_Msk
#define PPI_CHG1_CH10_Excluded PPI_CHG_CH10_Excluded
#define PPI_CHG1_CH10_Included PPI_CHG_CH10_Included
#define PPI_CHG1_CH9_Pos PPI_CHG_CH9_Pos
#define PPI_CHG1_CH9_Msk PPI_CHG_CH9_Msk
#define PPI_CHG1_CH9_Excluded PPI_CHG_CH9_Excluded
#define PPI_CHG1_CH9_Included PPI_CHG_CH9_Included
#define PPI_CHG1_CH8_Pos PPI_CHG_CH8_Pos
#define PPI_CHG1_CH8_Msk PPI_CHG_CH8_Msk
#define PPI_CHG1_CH8_Excluded PPI_CHG_CH8_Excluded
#define PPI_CHG1_CH8_Included PPI_CHG_CH8_Included
#define PPI_CHG1_CH7_Pos PPI_CHG_CH7_Pos
#define PPI_CHG1_CH7_Msk PPI_CHG_CH7_Msk
#define PPI_CHG1_CH7_Excluded PPI_CHG_CH7_Excluded
#define PPI_CHG1_CH7_Included PPI_CHG_CH7_Included
#define PPI_CHG1_CH6_Pos PPI_CHG_CH6_Pos
#define PPI_CHG1_CH6_Msk PPI_CHG_CH6_Msk
#define PPI_CHG1_CH6_Excluded PPI_CHG_CH6_Excluded
#define PPI_CHG1_CH6_Included PPI_CHG_CH6_Included
#define PPI_CHG1_CH5_Pos PPI_CHG_CH5_Pos
#define PPI_CHG1_CH5_Msk PPI_CHG_CH5_Msk
#define PPI_CHG1_CH5_Excluded PPI_CHG_CH5_Excluded
#define PPI_CHG1_CH5_Included PPI_CHG_CH5_Included
#define PPI_CHG1_CH4_Pos PPI_CHG_CH4_Pos
#define PPI_CHG1_CH4_Msk PPI_CHG_CH4_Msk
#define PPI_CHG1_CH4_Excluded PPI_CHG_CH4_Excluded
#define PPI_CHG1_CH4_Included PPI_CHG_CH4_Included
#define PPI_CHG1_CH3_Pos PPI_CHG_CH3_Pos
#define PPI_CHG1_CH3_Msk PPI_CHG_CH3_Msk
#define PPI_CHG1_CH3_Excluded PPI_CHG_CH3_Excluded
#define PPI_CHG1_CH3_Included PPI_CHG_CH3_Included
#define PPI_CHG1_CH2_Pos PPI_CHG_CH2_Pos
#define PPI_CHG1_CH2_Msk PPI_CHG_CH2_Msk
#define PPI_CHG1_CH2_Excluded PPI_CHG_CH2_Excluded
#define PPI_CHG1_CH2_Included PPI_CHG_CH2_Included
#define PPI_CHG1_CH1_Pos PPI_CHG_CH1_Pos
#define PPI_CHG1_CH1_Msk PPI_CHG_CH1_Msk
#define PPI_CHG1_CH1_Excluded PPI_CHG_CH1_Excluded
#define PPI_CHG1_CH1_Included PPI_CHG_CH1_Included
#define PPI_CHG1_CH0_Pos PPI_CHG_CH0_Pos
#define PPI_CHG1_CH0_Msk PPI_CHG_CH0_Msk
#define PPI_CHG1_CH0_Excluded PPI_CHG_CH0_Excluded
#define PPI_CHG1_CH0_Included PPI_CHG_CH0_Included
#define PPI_CHG2_CH15_Pos PPI_CHG_CH15_Pos
#define PPI_CHG2_CH15_Msk PPI_CHG_CH15_Msk
#define PPI_CHG2_CH15_Excluded PPI_CHG_CH15_Excluded
#define PPI_CHG2_CH15_Included PPI_CHG_CH15_Included
#define PPI_CHG2_CH14_Pos PPI_CHG_CH14_Pos
#define PPI_CHG2_CH14_Msk PPI_CHG_CH14_Msk
#define PPI_CHG2_CH14_Excluded PPI_CHG_CH14_Excluded
#define PPI_CHG2_CH14_Included PPI_CHG_CH14_Included
#define PPI_CHG2_CH13_Pos PPI_CHG_CH13_Pos
#define PPI_CHG2_CH13_Msk PPI_CHG_CH13_Msk
#define PPI_CHG2_CH13_Excluded PPI_CHG_CH13_Excluded
#define PPI_CHG2_CH13_Included PPI_CHG_CH13_Included
#define PPI_CHG2_CH12_Pos PPI_CHG_CH12_Pos
#define PPI_CHG2_CH12_Msk PPI_CHG_CH12_Msk
#define PPI_CHG2_CH12_Excluded PPI_CHG_CH12_Excluded
#define PPI_CHG2_CH12_Included PPI_CHG_CH12_Included
#define PPI_CHG2_CH11_Pos PPI_CHG_CH11_Pos
#define PPI_CHG2_CH11_Msk PPI_CHG_CH11_Msk
#define PPI_CHG2_CH11_Excluded PPI_CHG_CH11_Excluded
#define PPI_CHG2_CH11_Included PPI_CHG_CH11_Included
#define PPI_CHG2_CH10_Pos PPI_CHG_CH10_Pos
#define PPI_CHG2_CH10_Msk PPI_CHG_CH10_Msk
#define PPI_CHG2_CH10_Excluded PPI_CHG_CH10_Excluded
#define PPI_CHG2_CH10_Included PPI_CHG_CH10_Included
#define PPI_CHG2_CH9_Pos PPI_CHG_CH9_Pos
#define PPI_CHG2_CH9_Msk PPI_CHG_CH9_Msk
#define PPI_CHG2_CH9_Excluded PPI_CHG_CH9_Excluded
#define PPI_CHG2_CH9_Included PPI_CHG_CH9_Included
#define PPI_CHG2_CH8_Pos PPI_CHG_CH8_Pos
#define PPI_CHG2_CH8_Msk PPI_CHG_CH8_Msk
#define PPI_CHG2_CH8_Excluded PPI_CHG_CH8_Excluded
#define PPI_CHG2_CH8_Included PPI_CHG_CH8_Included
#define PPI_CHG2_CH7_Pos PPI_CHG_CH7_Pos
#define PPI_CHG2_CH7_Msk PPI_CHG_CH7_Msk
#define PPI_CHG2_CH7_Excluded PPI_CHG_CH7_Excluded
#define PPI_CHG2_CH7_Included PPI_CHG_CH7_Included
#define PPI_CHG2_CH6_Pos PPI_CHG_CH6_Pos
#define PPI_CHG2_CH6_Msk PPI_CHG_CH6_Msk
#define PPI_CHG2_CH6_Excluded PPI_CHG_CH6_Excluded
#define PPI_CHG2_CH6_Included PPI_CHG_CH6_Included
#define PPI_CHG2_CH5_Pos PPI_CHG_CH5_Pos
#define PPI_CHG2_CH5_Msk PPI_CHG_CH5_Msk
#define PPI_CHG2_CH5_Excluded PPI_CHG_CH5_Excluded
#define PPI_CHG2_CH5_Included PPI_CHG_CH5_Included
#define PPI_CHG2_CH4_Pos PPI_CHG_CH4_Pos
#define PPI_CHG2_CH4_Msk PPI_CHG_CH4_Msk
#define PPI_CHG2_CH4_Excluded PPI_CHG_CH4_Excluded
#define PPI_CHG2_CH4_Included PPI_CHG_CH4_Included
#define PPI_CHG2_CH3_Pos PPI_CHG_CH3_Pos
#define PPI_CHG2_CH3_Msk PPI_CHG_CH3_Msk
#define PPI_CHG2_CH3_Excluded PPI_CHG_CH3_Excluded
#define PPI_CHG2_CH3_Included PPI_CHG_CH3_Included
#define PPI_CHG2_CH2_Pos PPI_CHG_CH2_Pos
#define PPI_CHG2_CH2_Msk PPI_CHG_CH2_Msk
#define PPI_CHG2_CH2_Excluded PPI_CHG_CH2_Excluded
#define PPI_CHG2_CH2_Included PPI_CHG_CH2_Included
#define PPI_CHG2_CH1_Pos PPI_CHG_CH1_Pos
#define PPI_CHG2_CH1_Msk PPI_CHG_CH1_Msk
#define PPI_CHG2_CH1_Excluded PPI_CHG_CH1_Excluded
#define PPI_CHG2_CH1_Included PPI_CHG_CH1_Included
#define PPI_CHG2_CH0_Pos PPI_CHG_CH0_Pos
#define PPI_CHG2_CH0_Msk PPI_CHG_CH0_Msk
#define PPI_CHG2_CH0_Excluded PPI_CHG_CH0_Excluded
#define PPI_CHG2_CH0_Included PPI_CHG_CH0_Included
#define PPI_CHG3_CH15_Pos PPI_CHG_CH15_Pos
#define PPI_CHG3_CH15_Msk PPI_CHG_CH15_Msk
#define PPI_CHG3_CH15_Excluded PPI_CHG_CH15_Excluded
#define PPI_CHG3_CH15_Included PPI_CHG_CH15_Included
#define PPI_CHG3_CH14_Pos PPI_CHG_CH14_Pos
#define PPI_CHG3_CH14_Msk PPI_CHG_CH14_Msk
#define PPI_CHG3_CH14_Excluded PPI_CHG_CH14_Excluded
#define PPI_CHG3_CH14_Included PPI_CHG_CH14_Included
#define PPI_CHG3_CH13_Pos PPI_CHG_CH13_Pos
#define PPI_CHG3_CH13_Msk PPI_CHG_CH13_Msk
#define PPI_CHG3_CH13_Excluded PPI_CHG_CH13_Excluded
#define PPI_CHG3_CH13_Included PPI_CHG_CH13_Included
#define PPI_CHG3_CH12_Pos PPI_CHG_CH12_Pos
#define PPI_CHG3_CH12_Msk PPI_CHG_CH12_Msk
#define PPI_CHG3_CH12_Excluded PPI_CHG_CH12_Excluded
#define PPI_CHG3_CH12_Included PPI_CHG_CH12_Included
#define PPI_CHG3_CH11_Pos PPI_CHG_CH11_Pos
#define PPI_CHG3_CH11_Msk PPI_CHG_CH11_Msk
#define PPI_CHG3_CH11_Excluded PPI_CHG_CH11_Excluded
#define PPI_CHG3_CH11_Included PPI_CHG_CH11_Included
#define PPI_CHG3_CH10_Pos PPI_CHG_CH10_Pos
#define PPI_CHG3_CH10_Msk PPI_CHG_CH10_Msk
#define PPI_CHG3_CH10_Excluded PPI_CHG_CH10_Excluded
#define PPI_CHG3_CH10_Included PPI_CHG_CH10_Included
#define PPI_CHG3_CH9_Pos PPI_CHG_CH9_Pos
#define PPI_CHG3_CH9_Msk PPI_CHG_CH9_Msk
#define PPI_CHG3_CH9_Excluded PPI_CHG_CH9_Excluded
#define PPI_CHG3_CH9_Included PPI_CHG_CH9_Included
#define PPI_CHG3_CH8_Pos PPI_CHG_CH8_Pos
#define PPI_CHG3_CH8_Msk PPI_CHG_CH8_Msk
#define PPI_CHG3_CH8_Excluded PPI_CHG_CH8_Excluded
#define PPI_CHG3_CH8_Included PPI_CHG_CH8_Included
#define PPI_CHG3_CH7_Pos PPI_CHG_CH7_Pos
#define PPI_CHG3_CH7_Msk PPI_CHG_CH7_Msk
#define PPI_CHG3_CH7_Excluded PPI_CHG_CH7_Excluded
#define PPI_CHG3_CH7_Included PPI_CHG_CH7_Included
#define PPI_CHG3_CH6_Pos PPI_CHG_CH6_Pos
#define PPI_CHG3_CH6_Msk PPI_CHG_CH6_Msk
#define PPI_CHG3_CH6_Excluded PPI_CHG_CH6_Excluded
#define PPI_CHG3_CH6_Included PPI_CHG_CH6_Included
#define PPI_CHG3_CH5_Pos PPI_CHG_CH5_Pos
#define PPI_CHG3_CH5_Msk PPI_CHG_CH5_Msk
#define PPI_CHG3_CH5_Excluded PPI_CHG_CH5_Excluded
#define PPI_CHG3_CH5_Included PPI_CHG_CH5_Included
#define PPI_CHG3_CH4_Pos PPI_CHG_CH4_Pos
#define PPI_CHG3_CH4_Msk PPI_CHG_CH4_Msk
#define PPI_CHG3_CH4_Excluded PPI_CHG_CH4_Excluded
#define PPI_CHG3_CH4_Included PPI_CHG_CH4_Included
#define PPI_CHG3_CH3_Pos PPI_CHG_CH3_Pos
#define PPI_CHG3_CH3_Msk PPI_CHG_CH3_Msk
#define PPI_CHG3_CH3_Excluded PPI_CHG_CH3_Excluded
#define PPI_CHG3_CH3_Included PPI_CHG_CH3_Included
#define PPI_CHG3_CH2_Pos PPI_CHG_CH2_Pos
#define PPI_CHG3_CH2_Msk PPI_CHG_CH2_Msk
#define PPI_CHG3_CH2_Excluded PPI_CHG_CH2_Excluded
#define PPI_CHG3_CH2_Included PPI_CHG_CH2_Included
#define PPI_CHG3_CH1_Pos PPI_CHG_CH1_Pos
#define PPI_CHG3_CH1_Msk PPI_CHG_CH1_Msk
#define PPI_CHG3_CH1_Excluded PPI_CHG_CH1_Excluded
#define PPI_CHG3_CH1_Included PPI_CHG_CH1_Included
#define PPI_CHG3_CH0_Pos PPI_CHG_CH0_Pos
#define PPI_CHG3_CH0_Msk PPI_CHG_CH0_Msk
#define PPI_CHG3_CH0_Excluded PPI_CHG_CH0_Excluded
#define PPI_CHG3_CH0_Included PPI_CHG_CH0_Included
/*lint --flb "Leave library region" */
#endif /* NRF51_TO_NRF52840_H */

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ports/nrf/device/nrf52/nrf52.h
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ports/nrf/device/nrf52/nrf52840.h
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ports/nrf/device/nrf52/nrf52840_bitfields.h
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ports/nrf/device/nrf52/nrf52_bitfields.h
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ports/nrf/device/nrf52/nrf52_name_change.h
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/* Copyright (c) 2016, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* * Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* * Neither the name of Nordic Semiconductor ASA nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifndef NRF52_NAME_CHANGE_H
#define NRF52_NAME_CHANGE_H
/*lint ++flb "Enter library region */
/* This file is given to prevent your SW from not compiling with the updates made to nrf52.h and
* nrf52_bitfields.h. The macros defined in this file were available previously. Do not use these
* macros on purpose. Use the ones defined in nrf52.h and nrf52_bitfields.h instead.
*/
/* I2S */
/* Several enumerations changed case. Adding old macros to keep compilation compatibility. */
#define I2S_ENABLE_ENABLE_DISABLE I2S_ENABLE_ENABLE_Disabled
#define I2S_ENABLE_ENABLE_ENABLE I2S_ENABLE_ENABLE_Enabled
#define I2S_CONFIG_MODE_MODE_MASTER I2S_CONFIG_MODE_MODE_Master
#define I2S_CONFIG_MODE_MODE_SLAVE I2S_CONFIG_MODE_MODE_Slave
#define I2S_CONFIG_RXEN_RXEN_DISABLE I2S_CONFIG_RXEN_RXEN_Disabled
#define I2S_CONFIG_RXEN_RXEN_ENABLE I2S_CONFIG_RXEN_RXEN_Enabled
#define I2S_CONFIG_TXEN_TXEN_DISABLE I2S_CONFIG_TXEN_TXEN_Disabled
#define I2S_CONFIG_TXEN_TXEN_ENABLE I2S_CONFIG_TXEN_TXEN_Enabled
#define I2S_CONFIG_MCKEN_MCKEN_DISABLE I2S_CONFIG_MCKEN_MCKEN_Disabled
#define I2S_CONFIG_MCKEN_MCKEN_ENABLE I2S_CONFIG_MCKEN_MCKEN_Enabled
#define I2S_CONFIG_SWIDTH_SWIDTH_8BIT I2S_CONFIG_SWIDTH_SWIDTH_8Bit
#define I2S_CONFIG_SWIDTH_SWIDTH_16BIT I2S_CONFIG_SWIDTH_SWIDTH_16Bit
#define I2S_CONFIG_SWIDTH_SWIDTH_24BIT I2S_CONFIG_SWIDTH_SWIDTH_24Bit
#define I2S_CONFIG_ALIGN_ALIGN_LEFT I2S_CONFIG_ALIGN_ALIGN_Left
#define I2S_CONFIG_ALIGN_ALIGN_RIGHT I2S_CONFIG_ALIGN_ALIGN_Right
#define I2S_CONFIG_FORMAT_FORMAT_ALIGNED I2S_CONFIG_FORMAT_FORMAT_Aligned
#define I2S_CONFIG_CHANNELS_CHANNELS_STEREO I2S_CONFIG_CHANNELS_CHANNELS_Stereo
#define I2S_CONFIG_CHANNELS_CHANNELS_LEFT I2S_CONFIG_CHANNELS_CHANNELS_Left
#define I2S_CONFIG_CHANNELS_CHANNELS_RIGHT I2S_CONFIG_CHANNELS_CHANNELS_Right
/* LPCOMP */
/* Corrected typo in RESULT register. */
#define LPCOMP_RESULT_RESULT_Bellow LPCOMP_RESULT_RESULT_Below
/*lint --flb "Leave library region" */
#endif /* NRF52_NAME_CHANGE_H */

88
ports/nrf/device/nrf52/nrf52_to_nrf52840.h
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/* Copyright (c) 2016, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* * Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* * Neither the name of Nordic Semiconductor ASA nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifndef NRF52_TO_NRF52840_H
#define NRF52_TO_NRF52840_H
/*lint ++flb "Enter library region */
/* This file is given to prevent your SW from not compiling with the name changes between nRF51 or nRF52832 and nRF52840 devices.
* It redefines the old nRF51 or nRF52832 names into the new ones as long as the functionality is still supported. If the
* functionality is gone, there old names are not defined, so compilation will fail. Note that also includes macros
* from the nrf52_namechange.h file. */
/* Differences between latest nRF52 headers and nRF52840 headers. */
/* UART */
/* The registers PSELRTS, PSELTXD, PSELCTS, PSELRXD were restructured into a struct. */
#define PSELRTS PSEL.RTS
#define PSELTXD PSEL.TXD
#define PSELCTS PSEL.CTS
#define PSELRXD PSEL.RXD
/* TWI */
/* The registers PSELSCL, PSELSDA were restructured into a struct. */
#define PSELSCL PSEL.SCL
#define PSELSDA PSEL.SDA
/* From nrf52_name_change.h. Several macros changed in different versions of nRF52 headers. By defining the following, any code written for any version of nRF52 headers will still compile. */
/* I2S */
/* Several enumerations changed case. Adding old macros to keep compilation compatibility. */
#define I2S_ENABLE_ENABLE_DISABLE I2S_ENABLE_ENABLE_Disabled
#define I2S_ENABLE_ENABLE_ENABLE I2S_ENABLE_ENABLE_Enabled
#define I2S_CONFIG_MODE_MODE_MASTER I2S_CONFIG_MODE_MODE_Master
#define I2S_CONFIG_MODE_MODE_SLAVE I2S_CONFIG_MODE_MODE_Slave
#define I2S_CONFIG_RXEN_RXEN_DISABLE I2S_CONFIG_RXEN_RXEN_Disabled
#define I2S_CONFIG_RXEN_RXEN_ENABLE I2S_CONFIG_RXEN_RXEN_Enabled
#define I2S_CONFIG_TXEN_TXEN_DISABLE I2S_CONFIG_TXEN_TXEN_Disabled
#define I2S_CONFIG_TXEN_TXEN_ENABLE I2S_CONFIG_TXEN_TXEN_Enabled
#define I2S_CONFIG_MCKEN_MCKEN_DISABLE I2S_CONFIG_MCKEN_MCKEN_Disabled
#define I2S_CONFIG_MCKEN_MCKEN_ENABLE I2S_CONFIG_MCKEN_MCKEN_Enabled
#define I2S_CONFIG_SWIDTH_SWIDTH_8BIT I2S_CONFIG_SWIDTH_SWIDTH_8Bit
#define I2S_CONFIG_SWIDTH_SWIDTH_16BIT I2S_CONFIG_SWIDTH_SWIDTH_16Bit
#define I2S_CONFIG_SWIDTH_SWIDTH_24BIT I2S_CONFIG_SWIDTH_SWIDTH_24Bit
#define I2S_CONFIG_ALIGN_ALIGN_LEFT I2S_CONFIG_ALIGN_ALIGN_Left
#define I2S_CONFIG_ALIGN_ALIGN_RIGHT I2S_CONFIG_ALIGN_ALIGN_Right
#define I2S_CONFIG_FORMAT_FORMAT_ALIGNED I2S_CONFIG_FORMAT_FORMAT_Aligned
#define I2S_CONFIG_CHANNELS_CHANNELS_STEREO I2S_CONFIG_CHANNELS_CHANNELS_Stereo
#define I2S_CONFIG_CHANNELS_CHANNELS_LEFT I2S_CONFIG_CHANNELS_CHANNELS_Left
#define I2S_CONFIG_CHANNELS_CHANNELS_RIGHT I2S_CONFIG_CHANNELS_CHANNELS_Right
/* LPCOMP */
/* Corrected typo in RESULT register. */
#define LPCOMP_RESULT_RESULT_Bellow LPCOMP_RESULT_RESULT_Below
/*lint --flb "Leave library region" */
#endif /* NRF51_TO_NRF52840_H */

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ports/nrf/device/nrf52/system_nrf52.h
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/* Copyright (c) 2012 ARM LIMITED
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* * Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* * Neither the name of ARM nor the names of its contributors may be used to
* endorse or promote products derived from this software without specific
* prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifndef SYSTEM_NRF52_H
#define SYSTEM_NRF52_H
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
/**
* Initialize the system
*
* @param none
* @return none
*
* @brief Setup the microcontroller system.
* Initialize the System and update the SystemCoreClock variable.
*/
extern void SystemInit (void);
/**
* Update SystemCoreClock variable
*
* @param none
* @return none
*
* @brief Updates the SystemCoreClock with current core Clock
* retrieved from cpu registers.
*/
extern void SystemCoreClockUpdate (void);
#ifdef __cplusplus
}
#endif
#endif /* SYSTEM_NRF52_H */

308
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@ -1,308 +0,0 @@
/* Copyright (c) 2012 ARM LIMITED
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* * Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* * Neither the name of ARM nor the names of its contributors may be used to
* endorse or promote products derived from this software without specific
* prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#include <stdint.h>
#include <stdbool.h>
#include "nrf.h"
#include "system_nrf52.h"
/*lint ++flb "Enter library region" */
#define __SYSTEM_CLOCK_64M (64000000UL)
static bool errata_16(void);
static bool errata_31(void);
static bool errata_32(void);
static bool errata_36(void);
static bool errata_37(void);
static bool errata_57(void);
static bool errata_66(void);
static bool errata_108(void);
#if defined ( __CC_ARM )
uint32_t SystemCoreClock __attribute__((used)) = __SYSTEM_CLOCK_64M;
#elif defined ( __ICCARM__ )
__root uint32_t SystemCoreClock = __SYSTEM_CLOCK_64M;
#elif defined ( __GNUC__ )
uint32_t SystemCoreClock __attribute__((used)) = __SYSTEM_CLOCK_64M;
#endif
void SystemCoreClockUpdate(void)
{
SystemCoreClock = __SYSTEM_CLOCK_64M;
}
void SystemInit(void)
{
/* Workaround for Errata 16 "System: RAM may be corrupt on wakeup from CPU IDLE" found at the Errata document
for your device located at https://infocenter.nordicsemi.com/ */
if (errata_16()){
*(volatile uint32_t *)0x4007C074 = 3131961357ul;
}
/* Workaround for Errata 31 "CLOCK: Calibration values are not correctly loaded from FICR at reset" found at the Errata document
for your device located at https://infocenter.nordicsemi.com/ */
if (errata_31()){
*(volatile uint32_t *)0x4000053C = ((*(volatile uint32_t *)0x10000244) & 0x0000E000) >> 13;
}
/* Workaround for Errata 32 "DIF: Debug session automatically enables TracePort pins" found at the Errata document
for your device located at https://infocenter.nordicsemi.com/ */
if (errata_32()){
CoreDebug->DEMCR &= ~CoreDebug_DEMCR_TRCENA_Msk;
}
/* Workaround for Errata 36 "CLOCK: Some registers are not reset when expected" found at the Errata document
for your device located at https://infocenter.nordicsemi.com/ */
if (errata_36()){
NRF_CLOCK->EVENTS_DONE = 0;
NRF_CLOCK->EVENTS_CTTO = 0;
NRF_CLOCK->CTIV = 0;
}
/* Workaround for Errata 37 "RADIO: Encryption engine is slow by default" found at the Errata document
for your device located at https://infocenter.nordicsemi.com/ */
if (errata_37()){
*(volatile uint32_t *)0x400005A0 = 0x3;
}
/* Workaround for Errata 57 "NFCT: NFC Modulation amplitude" found at the Errata document
for your device located at https://infocenter.nordicsemi.com/ */
if (errata_57()){
*(volatile uint32_t *)0x40005610 = 0x00000005;
*(volatile uint32_t *)0x40005688 = 0x00000001;
*(volatile uint32_t *)0x40005618 = 0x00000000;
*(volatile uint32_t *)0x40005614 = 0x0000003F;
}
/* Workaround for Errata 66 "TEMP: Linearity specification not met with default settings" found at the Errata document
for your device located at https://infocenter.nordicsemi.com/ */
if (errata_66()){
NRF_TEMP->A0 = NRF_FICR->TEMP.A0;
NRF_TEMP->A1 = NRF_FICR->TEMP.A1;
NRF_TEMP->A2 = NRF_FICR->TEMP.A2;
NRF_TEMP->A3 = NRF_FICR->TEMP.A3;
NRF_TEMP->A4 = NRF_FICR->TEMP.A4;
NRF_TEMP->A5 = NRF_FICR->TEMP.A5;
NRF_TEMP->B0 = NRF_FICR->TEMP.B0;
NRF_TEMP->B1 = NRF_FICR->TEMP.B1;
NRF_TEMP->B2 = NRF_FICR->TEMP.B2;
NRF_TEMP->B3 = NRF_FICR->TEMP.B3;
NRF_TEMP->B4 = NRF_FICR->TEMP.B4;
NRF_TEMP->B5 = NRF_FICR->TEMP.B5;
NRF_TEMP->T0 = NRF_FICR->TEMP.T0;
NRF_TEMP->T1 = NRF_FICR->TEMP.T1;
NRF_TEMP->T2 = NRF_FICR->TEMP.T2;
NRF_TEMP->T3 = NRF_FICR->TEMP.T3;
NRF_TEMP->T4 = NRF_FICR->TEMP.T4;
}
/* Workaround for Errata 108 "RAM: RAM content cannot be trusted upon waking up from System ON Idle or System OFF mode" found at the Errata document
for your device located at https://infocenter.nordicsemi.com/ */
if (errata_108()){
*(volatile uint32_t *)0x40000EE4 = *(volatile uint32_t *)0x10000258 & 0x0000004F;
}
/* Enable the FPU if the compiler used floating point unit instructions. __FPU_USED is a MACRO defined by the
* compiler. Since the FPU consumes energy, remember to disable FPU use in the compiler if floating point unit
* operations are not used in your code. */
#if (__FPU_USED == 1)
SCB->CPACR |= (3UL << 20) | (3UL << 22);
__DSB();
__ISB();
#endif
/* Configure NFCT pins as GPIOs if NFCT is not to be used in your code. If CONFIG_NFCT_PINS_AS_GPIOS is not defined,
two GPIOs (see Product Specification to see which ones) will be reserved for NFC and will not be available as
normal GPIOs. */
#if defined (CONFIG_NFCT_PINS_AS_GPIOS)
if ((NRF_UICR->NFCPINS & UICR_NFCPINS_PROTECT_Msk) == (UICR_NFCPINS_PROTECT_NFC << UICR_NFCPINS_PROTECT_Pos)){
NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Wen << NVMC_CONFIG_WEN_Pos;
while (NRF_NVMC->READY == NVMC_READY_READY_Busy){}
NRF_UICR->NFCPINS &= ~UICR_NFCPINS_PROTECT_Msk;
while (NRF_NVMC->READY == NVMC_READY_READY_Busy){}
NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Ren << NVMC_CONFIG_WEN_Pos;
while (NRF_NVMC->READY == NVMC_READY_READY_Busy){}
NVIC_SystemReset();
}
#endif
/* Configure GPIO pads as pPin Reset pin if Pin Reset capabilities desired. If CONFIG_GPIO_AS_PINRESET is not
defined, pin reset will not be available. One GPIO (see Product Specification to see which one) will then be
reserved for PinReset and not available as normal GPIO. */
#if defined (CONFIG_GPIO_AS_PINRESET)
if (((NRF_UICR->PSELRESET[0] & UICR_PSELRESET_CONNECT_Msk) != (UICR_PSELRESET_CONNECT_Connected << UICR_PSELRESET_CONNECT_Pos)) ||
((NRF_UICR->PSELRESET[1] & UICR_PSELRESET_CONNECT_Msk) != (UICR_PSELRESET_CONNECT_Connected << UICR_PSELRESET_CONNECT_Pos))){
NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Wen << NVMC_CONFIG_WEN_Pos;
while (NRF_NVMC->READY == NVMC_READY_READY_Busy){}
NRF_UICR->PSELRESET[0] = 21;
while (NRF_NVMC->READY == NVMC_READY_READY_Busy){}
NRF_UICR->PSELRESET[1] = 21;
while (NRF_NVMC->READY == NVMC_READY_READY_Busy){}
NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Ren << NVMC_CONFIG_WEN_Pos;
while (NRF_NVMC->READY == NVMC_READY_READY_Busy){}
NVIC_SystemReset();
}
#endif
/* Enable SWO trace functionality. If ENABLE_SWO is not defined, SWO pin will be used as GPIO (see Product
Specification to see which one). */
#if defined (ENABLE_SWO)
CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk;
NRF_CLOCK->TRACECONFIG |= CLOCK_TRACECONFIG_TRACEMUX_Serial << CLOCK_TRACECONFIG_TRACEMUX_Pos;
NRF_P0->PIN_CNF[18] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
#endif
/* Enable Trace functionality. If ENABLE_TRACE is not defined, TRACE pins will be used as GPIOs (see Product
Specification to see which ones). */
#if defined (ENABLE_TRACE)
CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk;
NRF_CLOCK->TRACECONFIG |= CLOCK_TRACECONFIG_TRACEMUX_Parallel << CLOCK_TRACECONFIG_TRACEMUX_Pos;
NRF_P0->PIN_CNF[14] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
NRF_P0->PIN_CNF[15] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
NRF_P0->PIN_CNF[16] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
NRF_P0->PIN_CNF[18] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
NRF_P0->PIN_CNF[20] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
#endif
SystemCoreClockUpdate();
}
static bool errata_16(void)
{
if ((((*(uint32_t *)0xF0000FE0) & 0x000000FF) == 0x6) && (((*(uint32_t *)0xF0000FE4) & 0x0000000F) == 0x0)){
if (((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x30){
return true;
}
}
return false;
}
static bool errata_31(void)
{
if ((((*(uint32_t *)0xF0000FE0) & 0x000000FF) == 0x6) && (((*(uint32_t *)0xF0000FE4) & 0x0000000F) == 0x0)){
if (((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x30){
return true;
}
if (((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x40){
return true;
}
if (((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x50){
return true;
}
}
return false;
}
static bool errata_32(void)
{
if ((((*(uint32_t *)0xF0000FE0) & 0x000000FF) == 0x6) && (((*(uint32_t *)0xF0000FE4) & 0x0000000F) == 0x0)){
if (((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x30){
return true;
}
}
return false;
}
static bool errata_36(void)
{
if ((((*(uint32_t *)0xF0000FE0) & 0x000000FF) == 0x6) && (((*(uint32_t *)0xF0000FE4) & 0x0000000F) == 0x0)){
if (((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x30){
return true;
}
if (((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x40){
return true;
}
if (((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x50){
return true;
}
}
return false;
}
static bool errata_37(void)
{
if ((((*(uint32_t *)0xF0000FE0) & 0x000000FF) == 0x6) && (((*(uint32_t *)0xF0000FE4) & 0x0000000F) == 0x0)){
if (((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x30){
return true;
}
}
return false;
}
static bool errata_57(void)
{
if ((((*(uint32_t *)0xF0000FE0) & 0x000000FF) == 0x6) && (((*(uint32_t *)0xF0000FE4) & 0x0000000F) == 0x0)){
if (((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x30){
return true;
}
}
return false;
}
static bool errata_66(void)
{
if ((((*(uint32_t *)0xF0000FE0) & 0x000000FF) == 0x6) && (((*(uint32_t *)0xF0000FE4) & 0x0000000F) == 0x0)){
if (((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x50){
return true;
}
}
return false;
}
static bool errata_108(void)
{
if ((((*(uint32_t *)0xF0000FE0) & 0x000000FF) == 0x6) && (((*(uint32_t *)0xF0000FE4) & 0x0000000F) == 0x0)){
if (((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x30){
return true;
}
if (((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x40){
return true;
}
if (((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x50){
return true;
}
}
return false;
}
/*lint --flb "Leave library region" */

209
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@ -1,209 +0,0 @@
/* Copyright (c) 2012 ARM LIMITED
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* * Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* * Neither the name of ARM nor the names of its contributors may be used to
* endorse or promote products derived from this software without specific
* prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#include <stdint.h>
#include <stdbool.h>
#include "nrf.h"
#include "system_nrf52840.h"
/*lint ++flb "Enter library region" */
#define __SYSTEM_CLOCK_64M (64000000UL)
static bool errata_36(void);
static bool errata_98(void);
static bool errata_103(void);
static bool errata_115(void);
static bool errata_120(void);
#if defined ( __CC_ARM )
uint32_t SystemCoreClock __attribute__((used)) = __SYSTEM_CLOCK_64M;
#elif defined ( __ICCARM__ )
__root uint32_t SystemCoreClock = __SYSTEM_CLOCK_64M;
#elif defined ( __GNUC__ )
uint32_t SystemCoreClock __attribute__((used)) = __SYSTEM_CLOCK_64M;
#endif
void SystemCoreClockUpdate(void)
{
SystemCoreClock = __SYSTEM_CLOCK_64M;
}
void SystemInit(void)
{
/* Workaround for Errata 36 "CLOCK: Some registers are not reset when expected" found at the Errata document
for your device located at https://infocenter.nordicsemi.com/ */
if (errata_36()){
NRF_CLOCK->EVENTS_DONE = 0;
NRF_CLOCK->EVENTS_CTTO = 0;
NRF_CLOCK->CTIV = 0;
}
/* Workaround for Errata 98 "NFCT: Not able to communicate with the peer" found at the Errata document
for your device located at https://infocenter.nordicsemi.com/ */
if (errata_98()){
*(volatile uint32_t *)0x4000568Cul = 0x00038148ul;
}
/* Workaround for Errata 103 "CCM: Wrong reset value of CCM MAXPACKETSIZE" found at the Errata document
for your device located at https://infocenter.nordicsemi.com/ */
if (errata_103()){
NRF_CCM->MAXPACKETSIZE = 0xFBul;
}
/* Workaround for Errata 115 "RAM: RAM content cannot be trusted upon waking up from System ON Idle or System OFF mode" found at the Errata document
for your device located at https://infocenter.nordicsemi.com/ */
if (errata_115()){
*(volatile uint32_t *)0x40000EE4 = (*(volatile uint32_t *)0x40000EE4 & 0xFFFFFFF0) | (*(uint32_t *)0x10000258 & 0x0000000F);
}
/* Workaround for Errata 120 "QSPI: Data read or written is corrupted" found at the Errata document
for your device located at https://infocenter.nordicsemi.com/ */
if (errata_120()){
*(volatile uint32_t *)0x40029640ul = 0x200ul;
}
/* Enable the FPU if the compiler used floating point unit instructions. __FPU_USED is a MACRO defined by the
* compiler. Since the FPU consumes energy, remember to disable FPU use in the compiler if floating point unit
* operations are not used in your code. */
#if (__FPU_USED == 1)
SCB->CPACR |= (3UL << 20) | (3UL << 22);
__DSB();
__ISB();
#endif
/* Configure NFCT pins as GPIOs if NFCT is not to be used in your code. If CONFIG_NFCT_PINS_AS_GPIOS is not defined,
two GPIOs (see Product Specification to see which ones) will be reserved for NFC and will not be available as
normal GPIOs. */
#if defined (CONFIG_NFCT_PINS_AS_GPIOS)
if ((NRF_UICR->NFCPINS & UICR_NFCPINS_PROTECT_Msk) == (UICR_NFCPINS_PROTECT_NFC << UICR_NFCPINS_PROTECT_Pos)){
NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Wen << NVMC_CONFIG_WEN_Pos;
while (NRF_NVMC->READY == NVMC_READY_READY_Busy){}
NRF_UICR->NFCPINS &= ~UICR_NFCPINS_PROTECT_Msk;
while (NRF_NVMC->READY == NVMC_READY_READY_Busy){}
NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Ren << NVMC_CONFIG_WEN_Pos;
while (NRF_NVMC->READY == NVMC_READY_READY_Busy){}
NVIC_SystemReset();
}
#endif
/* Configure GPIO pads as pPin Reset pin if Pin Reset capabilities desired. If CONFIG_GPIO_AS_PINRESET is not
defined, pin reset will not be available. One GPIO (see Product Specification to see which one) will then be
reserved for PinReset and not available as normal GPIO. */
#if defined (CONFIG_GPIO_AS_PINRESET)
if (((NRF_UICR->PSELRESET[0] & UICR_PSELRESET_CONNECT_Msk) != (UICR_PSELRESET_CONNECT_Connected << UICR_PSELRESET_CONNECT_Pos)) ||
((NRF_UICR->PSELRESET[1] & UICR_PSELRESET_CONNECT_Msk) != (UICR_PSELRESET_CONNECT_Connected << UICR_PSELRESET_CONNECT_Pos))){
NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Wen << NVMC_CONFIG_WEN_Pos;
while (NRF_NVMC->READY == NVMC_READY_READY_Busy){}
NRF_UICR->PSELRESET[0] = 18;
while (NRF_NVMC->READY == NVMC_READY_READY_Busy){}
NRF_UICR->PSELRESET[1] = 18;
while (NRF_NVMC->READY == NVMC_READY_READY_Busy){}
NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Ren << NVMC_CONFIG_WEN_Pos;
while (NRF_NVMC->READY == NVMC_READY_READY_Busy){}
NVIC_SystemReset();
}
#endif
/* Enable SWO trace functionality. If ENABLE_SWO is not defined, SWO pin will be used as GPIO (see Product
Specification to see which one). */
#if defined (ENABLE_SWO)
CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk;
NRF_CLOCK->TRACECONFIG |= CLOCK_TRACECONFIG_TRACEMUX_Serial << CLOCK_TRACECONFIG_TRACEMUX_Pos;
NRF_P1->PIN_CNF[0] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
#endif
/* Enable Trace functionality. If ENABLE_TRACE is not defined, TRACE pins will be used as GPIOs (see Product
Specification to see which ones). */
#if defined (ENABLE_TRACE)
CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk;
NRF_CLOCK->TRACECONFIG |= CLOCK_TRACECONFIG_TRACEMUX_Parallel << CLOCK_TRACECONFIG_TRACEMUX_Pos;
NRF_P0->PIN_CNF[7] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
NRF_P1->PIN_CNF[0] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
NRF_P0->PIN_CNF[12] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
NRF_P0->PIN_CNF[11] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
NRF_P1->PIN_CNF[9] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
#endif
SystemCoreClockUpdate();
}
static bool errata_36(void)
{
if ((*(uint32_t *)0x10000130ul == 0x8ul) && (*(uint32_t *)0x10000134ul == 0x0ul)){
return true;
}
return false;
}
static bool errata_98(void)
{
if ((*(uint32_t *)0x10000130ul == 0x8ul) && (*(uint32_t *)0x10000134ul == 0x0ul)){
return true;
}
return false;
}
static bool errata_103(void)
{
if ((*(uint32_t *)0x10000130ul == 0x8ul) && (*(uint32_t *)0x10000134ul == 0x0ul)){
return true;
}
return false;
}
static bool errata_115(void)
{
if ((*(uint32_t *)0x10000130ul == 0x8ul) && (*(uint32_t *)0x10000134ul == 0x0ul)){
return true;
}
return false;
}
static bool errata_120(void)
{
if ((*(uint32_t *)0x10000130ul == 0x8ul) && (*(uint32_t *)0x10000134ul == 0x0ul)){
return true;
}
return false;
}
/*lint --flb "Leave library region" */

69
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@ -1,69 +0,0 @@
/* Copyright (c) 2012 ARM LIMITED
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* * Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* * Neither the name of ARM nor the names of its contributors may be used to
* endorse or promote products derived from this software without specific
* prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifndef SYSTEM_NRF52_H
#define SYSTEM_NRF52_H
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
/**
* Initialize the system
*
* @param none
* @return none
*
* @brief Setup the microcontroller system.
* Initialize the System and update the SystemCoreClock variable.
*/
extern void SystemInit (void);
/**
* Update SystemCoreClock variable
*
* @param none
* @return none
*
* @brief Updates the SystemCoreClock with current core Clock
* retrieved from cpu registers.
*/
extern void SystemCoreClockUpdate (void);
#ifdef __cplusplus
}
#endif
#endif /* SYSTEM_NRF52_H */

0
ports/nrf/device/nrf51/startup_nrf51822.c → ports/nrf/device/startup_nrf51822.c
View File

0
ports/nrf/device/nrf52/startup_nrf52832.c → ports/nrf/device/startup_nrf52832.c
View File

0
ports/nrf/device/nrf52/startup_nrf52840.c → ports/nrf/device/startup_nrf52840.c
View File

9
ports/nrf/drivers/bluetooth/ble_drv.c
View File

@ -36,8 +36,7 @@
#include "nrf_sdm.h"
#include "ble_gap.h"
#include "ble.h" // sd_ble_uuid_encode
#include "hal_irq.h"
#include "hal/hal_nvmc.h"
#include "drivers/flash.h"
#include "mphalport.h"
@ -906,12 +905,12 @@ void ble_drv_discover_descriptors(void) {
static void sd_evt_handler(uint32_t evt_id) {
switch (evt_id) {
#ifdef HAL_NVMC_MODULE_ENABLED
#if MICROPY_HW_HAS_BUILTIN_FLASH
case NRF_EVT_FLASH_OPERATION_SUCCESS:
hal_nvmc_operation_finished(HAL_NVMC_SUCCESS);
flash_operation_finished(FLASH_STATE_SUCCESS);
break;
case NRF_EVT_FLASH_OPERATION_ERROR:
hal_nvmc_operation_finished(HAL_NVMC_ERROR);
flash_operation_finished(FLASH_STATE_ERROR);
break;
#endif
default:

6
ports/nrf/drivers/bluetooth/ble_uart.c
View File

@ -29,15 +29,11 @@
#include <string.h>
#include "ble_uart.h"
#include "ringbuffer.h"
#include "hal/hal_time.h"
#include "mphalport.h"
#include "lib/utils/interrupt_char.h"
#if MICROPY_PY_BLE_NUS
#if BLUETOOTH_WEBBLUETOOTH_REPL
#include "hal_time.h"
#endif // BLUETOOTH_WEBBLUETOOTH_REPL
static ubluepy_uuid_obj_t uuid_obj_service = {
.base.type = &ubluepy_uuid_type,
.type = UBLUEPY_UUID_128_BIT,

132
ports/nrf/drivers/flash.c Normal file
View File

@ -0,0 +1,132 @@
/*
* This file is part of the MicroPython project, http://micropython.org/
*
* The MIT License (MIT)
*
* Copyright (c) 2018 Ayke van Laethem
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
#include "py/mpconfig.h"
#if MICROPY_HW_HAS_BUILTIN_FLASH && BLUETOOTH_SD
#include "drivers/flash.h"
#include "drivers/bluetooth/ble_drv.h"
#include "nrf_soc.h"
// Rotates bits in `value` left `shift` times.
STATIC inline uint32_t rotate_left(uint32_t value, uint32_t shift) {
return (value << shift) | (value >> (32 - shift));
}
STATIC volatile flash_state_t flash_operation_state = FLASH_STATE_BUSY;
STATIC void operation_init() {
flash_operation_state = FLASH_STATE_BUSY;
}
void flash_operation_finished(flash_state_t result) {
flash_operation_state = result;
}
STATIC bool operation_wait(uint32_t result) {
if (ble_drv_stack_enabled() != 1) {
// SoftDevice is not enabled, no event will be generated.
return result == NRF_SUCCESS;
}
if (result != NRF_SUCCESS) {
// In all other (non-success) cases, the command hasn't been
// started and no event will be generated.
return false;
}
// Wait until the event has been generated.
while (flash_operation_state == FLASH_STATE_BUSY) {
sd_app_evt_wait();
}
// Now we can safely continue, flash operation has completed.
return flash_operation_state == FLASH_STATE_SUCCESS;
}
void flash_write_byte(uint32_t address, uint8_t b) {
uint32_t address_aligned = address & ~3;
// Value to write - leave all bits that should not change at 0xff.
uint32_t value = 0xffffff00 | b;
// Rotate bits in value to an aligned position.
value = rotate_left(value, (address & 3) * 8);
while (1) {
operation_init();
uint32_t result = sd_flash_write((uint32_t*)address_aligned, &value, 1);
if (operation_wait(result)) break;
}
}
void flash_page_erase(uint32_t pageaddr) {
while (1) {
operation_init();
uint32_t result = sd_flash_page_erase(pageaddr / FLASH_PAGESIZE);
if (operation_wait(result)) break;
}
}
void flash_write_bytes(uint32_t dst, const uint8_t *src, uint32_t num_bytes) {
const uint8_t *src_end = src + num_bytes;
// sd_flash_write does not accept unaligned addresses so we have to
// work around that by writing all unaligned addresses byte-by-byte.
// Write first bytes to align the write address.
while (src != src_end && (dst & 0b11)) {
flash_write_byte(dst, *src);
dst++;
src++;
}
// Write as many words as possible.
// dst is now aligned, src possibly not.
while (src_end - src >= 4) {
uint8_t buf[4] __attribute__((aligned(4)));
for (int i = 0; i < 4; i++) {
buf[i] = ((uint8_t*)src)[i];
}
operation_init();
uint32_t result = sd_flash_write((uint32_t*)dst, (const uint32_t*)&buf, 1);
if (operation_wait(result)) {
// If it is successfully written, go to the next word.
src += 4;
dst += 4;
}
}
// Write remaining unaligned bytes.
while (src != src_end) {
flash_write_byte(dst, *src);
dst++;
src++;
}
}
#endif // MICROPY_HW_HAS_BUILTIN_FLASH

43
ports/nrf/hal/hal_temp.h → ports/nrf/drivers/flash.h
View File

@ -3,7 +3,7 @@
*
* The MIT License (MIT)
*
* Copyright (c) 2017 Bander F. Ajba
* Copyright (c) 2018 Ayke van Laethem
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
@ -24,16 +24,41 @@
* THE SOFTWARE.
*/
#ifndef HAL_TEMP_H__
#define HAL_TEMP_H__
#ifndef __MICROPY_INCLUDED_LIB_FLASH_H__
#define __MICROPY_INCLUDED_LIB_FLASH_H__
#include "nrf.h"
#include "nrf_nvmc.h"
#define MASK_SIGN (0x00000200UL)
#define MASK_SIGN_EXTENSION (0xFFFFFC00UL)
#if defined(NRF51)
#define FLASH_PAGESIZE (1024)
void hal_temp_init(void);
#elif defined(NRF52_SERIES)
#define FLASH_PAGESIZE (4096)
#else
#error Unknown chip
#endif
int32_t hal_temp_read(void);
#define FLASH_IS_PAGE_ALIGNED(addr) ((uint32_t)(addr) & (FLASH_PAGESIZE - 1))
#endif
#if BLUETOOTH_SD
typedef enum {
FLASH_STATE_BUSY,
FLASH_STATE_SUCCESS,
FLASH_STATE_ERROR,
} flash_state_t;
void flash_page_erase(uint32_t address);
void flash_write_byte(uint32_t address, uint8_t value);
void flash_write_bytes(uint32_t address, const uint8_t *src, uint32_t num_bytes);
void flash_operation_finished(flash_state_t result);
#else
#define flash_page_erase nrf_nvmc_page_erase
#define flash_write_byte nrf_nvmc_write_byte
#define flash_write_bytes nrf_nvmc_write_bytes
#endif
#endif // __MICROPY_INCLUDED_LIB_FLASH_H__

13
ports/nrf/drivers/softpwm.c
View File

@ -31,8 +31,8 @@
#include "stddef.h"
#include "py/runtime.h"
#include "py/gc.h"
#include "hal_timer.h"
#include "hal_gpio.h"
#include "nrf_timer.h"
#include "nrf_gpio.h"
#include "pin.h"
#include "ticker.h"
@ -154,10 +154,11 @@ int32_t pwm_callback(void) {
int32_t tnow = (event->time*events->period)>>10;
do {
if (event->turn_on) {
hal_gpio_pin_set(0, event->pin);
nrf_gpio_pin_set(event->pin);
next_event++;
} else {
hal_gpio_out_clear(0, events->all_pins);
// TODO: Resolve port for nrf52
nrf_gpio_port_out_clear(NRF_GPIO, events->all_pins);
next_event = 0;
tnow = 0;
if (pending_events) {
@ -214,7 +215,7 @@ void pwm_set_duty_cycle(int32_t pin, uint32_t value) {
old_events = active_events;
}
if (((1<<pin)&old_events->all_pins) == 0) {
hal_gpio_cfg_pin(0, pin, HAL_GPIO_MODE_OUTPUT, HAL_GPIO_PULL_DISABLED);
nrf_gpio_cfg_output(pin);
}
int ev = find_pin_in_events(old_events, pin);
pwm_events *events;
@ -251,7 +252,7 @@ void pwm_release(int32_t pin) {
return;
// If i >= 0 it means that `ev` is in RAM, so it safe to discard the const qualifier
((pwm_events *)ev)->events[i].pin = 31;
hal_gpio_pin_clear(0, pin);
nrf_gpio_pin_clear(pin);
}
#endif // MICROPY_PY_MACHINE_SOFT_PWM

18
ports/nrf/drivers/ticker.c
View File

@ -29,7 +29,7 @@
#if MICROPY_PY_MACHINE_SOFT_PWM
#include "ticker.h"
#include "hal_irq.h"
#include "nrfx_glue.h"
#define FastTicker NRF_TIMER1
#define FastTicker_IRQn TIMER1_IRQn
@ -58,15 +58,15 @@ void ticker_init0(void) {
ticker->SHORTS = 0;
#ifdef NRF51
hal_irq_priority(FastTicker_IRQn, 1);
NRFX_IRQ_PRIORITY_SET(FastTicker_IRQn, 1);
#else
hal_irq_priority(FastTicker_IRQn, 2);
NRFX_IRQ_PRIORITY_SET(FastTicker_IRQn, 2);
#endif
hal_irq_priority(SlowTicker_IRQn, 3);
hal_irq_priority(SlowTicker_IRQn, 3);
NRFX_IRQ_PRIORITY_SET(SlowTicker_IRQn, 3);
NRFX_IRQ_PRIORITY_SET(SlowTicker_IRQn, 3);
hal_irq_enable(SlowTicker_IRQn);
NRFX_IRQ_ENABLE(SlowTicker_IRQn);
}
void ticker_register_low_pri_callback(callback_ptr slow_ticker_callback) {
@ -77,7 +77,7 @@ void ticker_register_low_pri_callback(callback_ptr slow_ticker_callback) {
* http://www.nordicsemi.com/eng/content/download/29490/494569/file/nRF51822-PAN%20v3.0.pdf
*/
void ticker_start(void) {
hal_irq_enable(FastTicker_IRQn);
NRFX_IRQ_ENABLE(FastTicker_IRQn);
#ifdef NRF51
*(uint32_t *)0x40009C0C = 1; // for Timer 1
#endif
@ -85,7 +85,7 @@ void ticker_start(void) {
}
void ticker_stop(void) {
hal_irq_disable(FastTicker_IRQn);
NRFX_IRQ_DISABLE(FastTicker_IRQn);
FastTicker->TASKS_STOP = 1;
#ifdef NRF51
*(uint32_t *)0x40009C0C = 0; // for Timer 1
@ -119,7 +119,7 @@ void FastTicker_IRQHandler(void) {
ticker->EVENTS_COMPARE[3] = 0;
ticker->CC[3] += MICROSECONDS_PER_MACRO_TICK;
ticks += MILLISECONDS_PER_MACRO_TICK;
hal_irq_pending(SlowTicker_IRQn);
NRFX_IRQ_PENDING_SET(SlowTicker_IRQn);
}
}

27
ports/nrf/examples/ssd1306_mod.py
View File

@ -20,8 +20,35 @@
from ssd1306 import SSD1306_I2C
SET_COL_ADDR = const(0x21)
SET_PAGE_ADDR = const(0x22)
class SSD1306_I2C_Mod(SSD1306_I2C):
def show(self):
x0 = 0
x1 = self.width - 1
if self.width == 64:
# displays with width of 64 pixels are shifted by 32
x0 += 32
x1 += 32
self.write_cmd(SET_COL_ADDR)
self.write_cmd(x0)
self.write_cmd(x1)
self.write_cmd(SET_PAGE_ADDR)
self.write_cmd(0)
self.write_cmd(self.pages - 1)
chunk_size = 254 # 255, excluding opcode.
num_of_chunks = len(self.buffer) // chunk_size
leftover = len(self.buffer) - (num_of_chunks * chunk_size)
for i in range(0, num_of_chunks):
self.write_data(self.buffer[chunk_size*i:chunk_size*(i+1)])
if (leftover > 0):
self.write_data(self.buffer[chunk_size * num_of_chunks:])
def write_data(self, buf):
buffer = bytearray([0x40]) + buf # Co=0, D/C#=1
self.i2c.writeto(self.addr, buffer)

4
ports/nrf/examples/ubluepy_temp.py
View File

@ -23,7 +23,7 @@
# THE SOFTWARE
from pyb import LED
from machine import RTC, Temp
from machine import RTCounter, Temp
from ubluepy import Service, Characteristic, UUID, Peripheral, constants
def event_handler(id, handle, data):
@ -70,7 +70,7 @@ LED(1).off()
# use RTC1 as RTC0 is used by bluetooth stack
# set up RTC callback every 5 second
rtc = RTC(1, period=5, mode=RTC.PERIODIC, callback=send_temp)
rtc = RTCounter(1, period=50, mode=RTCounter.PERIODIC, callback=send_temp)
notif_enabled = False

129
ports/nrf/hal/hal_adc.c
View File

@ -1,129 +0,0 @@
/*
* This file is part of the MicroPython project, http://micropython.org/
*
* The MIT License (MIT)
*
* Copyright (c) 2017 Glenn Ruben Bakke
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
#include <stdio.h>
#include "mphalport.h"
#include "hal_adc.h"
#ifdef HAL_ADC_MODULE_ENABLED
#define ADC_REF_VOLTAGE_IN_MILLIVOLTS (1200) // Reference voltage (in milli volts) used by ADC while doing conversion.
#define ADC_PRE_SCALING_COMPENSATION (3) // The ADC is configured to use VDD with 1/3 prescaling as input. And hence the result of conversion is to be multiplied by 3 to get the actual value of the battery voltage.
#define DIODE_FWD_VOLT_DROP_MILLIVOLTS (270) // Typical forward voltage drop of the diode (Part no: SD103ATW-7-F) that is connected in series with the voltage supply. This is the voltage drop when the forward current is 1mA. Source: Data sheet of 'SURFACE MOUNT SCHOTTKY BARRIER DIODE ARRAY' available at www.diodes.com.
#define ADC_RESULT_IN_MILLI_VOLTS(ADC_VALUE)\
((((ADC_VALUE) * ADC_REF_VOLTAGE_IN_MILLIVOLTS) / 255) * ADC_PRE_SCALING_COMPENSATION)
static const uint32_t hal_adc_input_lookup[] = {
ADC_CONFIG_PSEL_AnalogInput0 << ADC_CONFIG_PSEL_Pos,
ADC_CONFIG_PSEL_AnalogInput1 << ADC_CONFIG_PSEL_Pos,
ADC_CONFIG_PSEL_AnalogInput2 << ADC_CONFIG_PSEL_Pos,
ADC_CONFIG_PSEL_AnalogInput3 << ADC_CONFIG_PSEL_Pos,
ADC_CONFIG_PSEL_AnalogInput4 << ADC_CONFIG_PSEL_Pos,
ADC_CONFIG_PSEL_AnalogInput5 << ADC_CONFIG_PSEL_Pos,
ADC_CONFIG_PSEL_AnalogInput6 << ADC_CONFIG_PSEL_Pos,
ADC_CONFIG_PSEL_AnalogInput7 << ADC_CONFIG_PSEL_Pos
};
static uint8_t battery_level_in_percent(const uint16_t mvolts)
{
uint8_t battery_level;
if (mvolts >= 3000) {
battery_level = 100;
} else if (mvolts > 2900) {
battery_level = 100 - ((3000 - mvolts) * 58) / 100;
} else if (mvolts > 2740) {
battery_level = 42 - ((2900 - mvolts) * 24) / 160;
} else if (mvolts > 2440) {
battery_level = 18 - ((2740 - mvolts) * 12) / 300;
} else if (mvolts > 2100) {
battery_level = 6 - ((2440 - mvolts) * 6) / 340;
} else {
battery_level = 0;
}
return battery_level;
}
uint16_t hal_adc_channel_value(hal_adc_config_t const * p_adc_conf) {
ADC_BASE->INTENSET = ADC_INTENSET_END_Msk;
ADC_BASE->CONFIG = (ADC_CONFIG_RES_8bit << ADC_CONFIG_RES_Pos)
| (ADC_CONFIG_INPSEL_AnalogInputTwoThirdsPrescaling << ADC_CONFIG_INPSEL_Pos)
| (ADC_CONFIG_REFSEL_VBG << ADC_CONFIG_REFSEL_Pos)
| (hal_adc_input_lookup[p_adc_conf->channel])
| (ADC_CONFIG_EXTREFSEL_None << ADC_CONFIG_EXTREFSEL_Pos);
ADC_BASE->EVENTS_END = 0;
ADC_BASE->ENABLE = ADC_ENABLE_ENABLE_Enabled;
ADC_BASE->EVENTS_END = 0;
ADC_BASE->TASKS_START = 1;
while (!ADC_BASE->EVENTS_END) {
;
}
uint8_t adc_result;
ADC_BASE->EVENTS_END = 0;
adc_result = ADC_BASE->RESULT;
ADC_BASE->TASKS_STOP = 1;
return adc_result;
}
uint16_t hal_adc_battery_level(void) {
ADC_BASE->INTENSET = ADC_INTENSET_END_Msk;
ADC_BASE->CONFIG = (ADC_CONFIG_RES_8bit << ADC_CONFIG_RES_Pos)
| (ADC_CONFIG_INPSEL_SupplyOneThirdPrescaling << ADC_CONFIG_INPSEL_Pos)
| (ADC_CONFIG_REFSEL_VBG << ADC_CONFIG_REFSEL_Pos)
| (ADC_CONFIG_PSEL_Disabled << ADC_CONFIG_PSEL_Pos)
| (ADC_CONFIG_EXTREFSEL_None << ADC_CONFIG_EXTREFSEL_Pos);
ADC_BASE->EVENTS_END = 0;
ADC_BASE->ENABLE = ADC_ENABLE_ENABLE_Enabled;
ADC_BASE->EVENTS_END = 0;
ADC_BASE->TASKS_START = 1;
while (!ADC_BASE->EVENTS_END) {
;
}
uint8_t adc_result;
uint16_t batt_lvl_in_milli_volts;
ADC_BASE->EVENTS_END = 0;
adc_result = ADC_BASE->RESULT;
ADC_BASE->TASKS_STOP = 1;
batt_lvl_in_milli_volts = ADC_RESULT_IN_MILLI_VOLTS(adc_result) + DIODE_FWD_VOLT_DROP_MILLIVOLTS;
return battery_level_in_percent(batt_lvl_in_milli_volts);
}
#endif // HAL_ADC_MODULE_ENABLED

75
ports/nrf/hal/hal_adc.h
View File

@ -1,75 +0,0 @@
/*
* This file is part of the MicroPython project, http://micropython.org/
*
* The MIT License (MIT)
*
* Copyright (c) 2017 Glenn Ruben Bakke
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
#ifndef HAL_ADC_H__
#define HAL_ADC_H__
#include <stdint.h>
#include "nrf.h"
#if NRF51
#define ADC_IRQ_NUM ADC_IRQn
#define ADC_BASE ((NRF_ADC_Type *)NRF_ADC_BASE)
#define HAL_ADC_Type NRF_ADC_Type
#else
#define ADC_IRQ_NUM SAADC_IRQn
#define ADC_BASE ((NRF_SAADC_Type *)NRF_SAADC_BASE)
#define HAL_ADC_Type NRF_SAADC_Type
#endif
typedef enum {
HAL_ADC_CHANNEL_2 = 2,
HAL_ADC_CHANNEL_3,
HAL_ADC_CHANNEL_4,
HAL_ADC_CHANNEL_5,
HAL_ADC_CHANNEL_6,
HAL_ADC_CHANNEL_7,
} hal_adc_channel_t;
/**
* @brief ADC Configuration Structure definition
*/
typedef struct {
hal_adc_channel_t channel;
} hal_adc_config_t;
/**
* @brief ADC handle Structure definition
*/
typedef struct __ADC_HandleTypeDef {
hal_adc_config_t config; /* ADC config parameters */
} ADC_HandleTypeDef;
uint16_t hal_adc_channel_value(hal_adc_config_t const * p_adc_conf);
uint16_t hal_adc_battery_level(void);
#endif // HAL_ADC_H__

118
ports/nrf/hal/hal_adce.c
View File

@ -1,118 +0,0 @@
/*
* This file is part of the MicroPython project, http://micropython.org/
*
* The MIT License (MIT)
*
* Copyright (c) 2017 Glenn Ruben Bakke
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
#include "mphalport.h"
#include "hal_adc.h"
#ifdef HAL_ADCE_MODULE_ENABLED
static const uint32_t hal_adc_input_lookup_pos[] = {
SAADC_CH_PSELP_PSELP_AnalogInput0 << SAADC_CH_PSELP_PSELP_Pos,
SAADC_CH_PSELP_PSELP_AnalogInput1 << SAADC_CH_PSELP_PSELP_Pos,
SAADC_CH_PSELP_PSELP_AnalogInput2 << SAADC_CH_PSELP_PSELP_Pos,
SAADC_CH_PSELP_PSELP_AnalogInput3 << SAADC_CH_PSELP_PSELP_Pos,
SAADC_CH_PSELP_PSELP_AnalogInput4 << SAADC_CH_PSELP_PSELP_Pos,
SAADC_CH_PSELP_PSELP_AnalogInput5 << SAADC_CH_PSELP_PSELP_Pos,
SAADC_CH_PSELP_PSELP_AnalogInput6 << SAADC_CH_PSELP_PSELP_Pos,
SAADC_CH_PSELP_PSELP_AnalogInput7 << SAADC_CH_PSELP_PSELP_Pos
};
#define HAL_ADCE_PSELP_NOT_CONNECTED (SAADC_CH_PSELP_PSELP_NC << SAADC_CH_PSELP_PSELP_Pos)
#define HAL_ADCE_PSELP_VDD (SAADC_CH_PSELP_PSELP_VDD << SAADC_CH_PSELP_PSELP_Pos)
/*static const uint32_t hal_adc_input_lookup_neg[] = {
SAADC_CH_PSELN_PSELN_AnalogInput0 << SAADC_CH_PSELN_PSELN_Pos,
SAADC_CH_PSELN_PSELN_AnalogInput1 << SAADC_CH_PSELN_PSELN_Pos,
SAADC_CH_PSELN_PSELN_AnalogInput2 << SAADC_CH_PSELN_PSELN_Pos,
SAADC_CH_PSELN_PSELN_AnalogInput3 << SAADC_CH_PSELN_PSELN_Pos,
SAADC_CH_PSELN_PSELN_AnalogInput4 << SAADC_CH_PSELN_PSELN_Pos,
SAADC_CH_PSELN_PSELN_AnalogInput5 << SAADC_CH_PSELN_PSELN_Pos,
SAADC_CH_PSELN_PSELN_AnalogInput6 << SAADC_CH_PSELN_PSELN_Pos,
SAADC_CH_PSELN_PSELN_AnalogInput7 << SAADC_CH_PSELN_PSELN_Pos
};*/
#define HAL_ADCE_PSELN_NOT_CONNECTED (SAADC_CH_PSELN_PSELN_NC << SAADC_CH_PSELN_PSELN_Pos)
#define HAL_ADCE_PSELN_VDD (SAADC_CH_PSELN_PSELN_VDD << SAADC_CH_PSELN_PSELN_Pos)
uint16_t hal_adc_channel_value(hal_adc_config_t const * p_adc_conf) {
int16_t result = 0;
// configure to use VDD/4 and gain 1/4
ADC_BASE->CH[0].CONFIG = (SAADC_CH_CONFIG_GAIN_Gain1_4 << SAADC_CH_CONFIG_GAIN_Pos)
| (SAADC_CH_CONFIG_MODE_SE << SAADC_CH_CONFIG_MODE_Pos)
| (SAADC_CH_CONFIG_REFSEL_VDD1_4 << SAADC_CH_CONFIG_REFSEL_Pos)
| (SAADC_CH_CONFIG_RESN_Bypass << SAADC_CH_CONFIG_RESN_Pos)
| (SAADC_CH_CONFIG_RESP_Bypass << SAADC_CH_CONFIG_RESP_Pos)
| (SAADC_CH_CONFIG_TACQ_3us << SAADC_CH_CONFIG_TACQ_Pos);
// positive input
ADC_BASE->CH[0].PSELP = hal_adc_input_lookup_pos[p_adc_conf->channel]; // HAL_ADCE_PSELP_VDD;
ADC_BASE->CH[0].PSELN = HAL_ADCE_PSELN_NOT_CONNECTED;
ADC_BASE->RESOLUTION = SAADC_RESOLUTION_VAL_8bit << SAADC_RESOLUTION_VAL_Pos;
ADC_BASE->RESULT.MAXCNT = 1;
ADC_BASE->RESULT.PTR = (uint32_t)&result;
ADC_BASE->SAMPLERATE = SAADC_SAMPLERATE_MODE_Task << SAADC_SAMPLERATE_MODE_Pos;
ADC_BASE->ENABLE = SAADC_ENABLE_ENABLE_Enabled << SAADC_ENABLE_ENABLE_Pos;
// calibrate ADC
ADC_BASE->TASKS_CALIBRATEOFFSET = 1;
while (ADC_BASE->EVENTS_CALIBRATEDONE == 0) {
;
}
ADC_BASE->EVENTS_CALIBRATEDONE = 0;
while (ADC_BASE->STATUS == (SAADC_STATUS_STATUS_Busy << SAADC_STATUS_STATUS_Pos)) {
;
}
// start the ADC
ADC_BASE->TASKS_START = 1;
while (ADC_BASE->EVENTS_STARTED == 0) {
;
}
ADC_BASE->EVENTS_STARTED = 0;
// sample ADC
ADC_BASE->TASKS_SAMPLE = 1;
while (ADC_BASE->EVENTS_END == 0) {
;
}
ADC_BASE->EVENTS_END = 0;
ADC_BASE->TASKS_STOP = 1;
while (ADC_BASE->EVENTS_STOPPED == 0) {
;
}
ADC_BASE->EVENTS_STOPPED = 0;
return result;
}
uint16_t hal_adc_battery_level(void) {
return 0;
}
#endif // HAL_ADCE_MODULE_ENABLED

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/*
* This file is part of the MicroPython project, http://micropython.org/
*
* The MIT License (MIT)
*
* Copyright (c) 2017 Glenn Ruben Bakke
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
#include "hal_gpio.h"
#include "mphalport.h"
#include "hal_irq.h"
#define GPIOTE_IRQ_NUM GPIOTE_IRQn
#define GPIOTE_BASE ((NRF_GPIOTE_Type *)NRF_GPIOTE_BASE)
#define HAL_GPIOTE_Type NRF_GPIOTE_Type
static hal_gpio_event_callback_t m_callback;
void hal_gpio_register_callback(hal_gpio_event_callback_t cb) {
m_callback = cb;
#if 0
hal_gpio_event_config_t config;
config.channel = HAL_GPIO_EVENT_CHANNEL_0;
config.event = HAL_GPIO_POLARITY_EVENT_HIGH_TO_LOW;
config.init_level = 1;
config.pin = 13;
config.port = 0;
// start LFCLK if not already started
if (NRF_CLOCK->LFCLKSTAT == 0) {
NRF_CLOCK->TASKS_LFCLKSTART = 1;
while (NRF_CLOCK->EVENTS_LFCLKSTARTED == 0);
NRF_CLOCK->EVENTS_LFCLKSTARTED = 0;
}
hal_irq_enable(GPIOTE_IRQ_NUM);
hal_irq_priority(GPIOTE_IRQ_NUM, 3);
hal_gpio_event_config(&config);
#endif
}
void hal_gpio_event_config(hal_gpio_event_config_t const * p_config) {
#if 0
hal_gpio_cfg_pin(p_config->port, p_config->pin, HAL_GPIO_MODE_INPUT, HAL_GPIO_PULL_UP);
uint8_t channel = (uint8_t)p_config->channel;
GPIOTE_BASE->CONFIG[channel] = \
GPIOTE_CONFIG_MODE_Event << GPIOTE_CONFIG_MODE_Pos \
| p_config->pin << GPIOTE_CONFIG_PSEL_Pos \
| p_config->event \
| p_config->init_level << GPIOTE_CONFIG_OUTINIT_Pos;
GPIOTE_BASE->INTENSET = 1 << channel;
GPIOTE_BASE->EVENTS_IN[channel] = 0;
#endif
}
#if 0
void GPIOTE_IRQHandler(void) {
if (GPIOTE_BASE->EVENTS_IN[0]) {
GPIOTE_BASE->EVENTS_IN[0] = 0;
m_callback(HAL_GPIO_EVENT_CHANNEL_0);
}
if (GPIOTE_BASE->EVENTS_IN[1]) {
GPIOTE_BASE->EVENTS_IN[1] = 0;
m_callback(HAL_GPIO_EVENT_CHANNEL_1);
}
if (GPIOTE_BASE->EVENTS_IN[2]) {
GPIOTE_BASE->EVENTS_IN[2] = 0;
m_callback(HAL_GPIO_EVENT_CHANNEL_2);
}
if (GPIOTE_BASE->EVENTS_IN[3]) {
GPIOTE_BASE->EVENTS_IN[3] = 0;
m_callback(HAL_GPIO_EVENT_CHANNEL_3);
}
#if NRF52
if (GPIOTE_BASE->EVENTS_IN[4]) {
GPIOTE_BASE->EVENTS_IN[4] = 0;
m_callback(HAL_GPIO_EVENT_CHANNEL_4);
}
if (GPIOTE_BASE->EVENTS_IN[5]) {
GPIOTE_BASE->EVENTS_IN[5] = 0;
m_callback(HAL_GPIO_EVENT_CHANNEL_5);
}
if (GPIOTE_BASE->EVENTS_IN[6]) {
GPIOTE_BASE->EVENTS_IN[6] = 0;
m_callback(HAL_GPIO_EVENT_CHANNEL_6);
}
if (GPIOTE_BASE->EVENTS_IN[7]) {
GPIOTE_BASE->EVENTS_IN[7] = 0;
m_callback(HAL_GPIO_EVENT_CHANNEL_7);
}
#endif
}
#endif // if 0

128
ports/nrf/hal/hal_gpio.h
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/*
* This file is part of the MicroPython project, http://micropython.org/
*
* The MIT License (MIT)
*
* Copyright (c) 2017 Glenn Ruben Bakke
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
#ifndef HAL_GPIO_H__
#define HAL_GPIO_H__
#include "nrf.h"
#if NRF51
#define POINTERS (const uint32_t[]){NRF_GPIO_BASE}
#endif
#if NRF52
#ifdef NRF52832_XXAA
#define POINTERS (const uint32_t[]){NRF_P0_BASE}
#endif
#ifdef NRF52840_XXAA
#define POINTERS (const uint32_t[]){NRF_P0_BASE, NRF_P1_BASE}
#endif
#endif
#define GPIO_BASE(x) ((NRF_GPIO_Type *)POINTERS[x])
#define hal_gpio_pin_high(p) (((NRF_GPIO_Type *)(GPIO_BASE((p)->port)))->OUTSET = (p)->pin_mask)
#define hal_gpio_pin_low(p) (((NRF_GPIO_Type *)(GPIO_BASE((p)->port)))->OUTCLR = (p)->pin_mask)
#define hal_gpio_pin_read(p) (((NRF_GPIO_Type *)(GPIO_BASE((p)->port)))->IN >> ((p)->pin) & 1)
typedef enum {
HAL_GPIO_POLARITY_EVENT_LOW_TO_HIGH = GPIOTE_CONFIG_POLARITY_LoToHi << GPIOTE_CONFIG_POLARITY_Pos,
HAL_GPIO_POLARITY_EVENT_HIGH_TO_LOW = GPIOTE_CONFIG_POLARITY_HiToLo << GPIOTE_CONFIG_POLARITY_Pos,
HAL_GPIO_POLARITY_EVENT_TOGGLE = GPIOTE_CONFIG_POLARITY_Toggle << GPIOTE_CONFIG_POLARITY_Pos
} hal_gpio_polarity_event_t;
typedef enum {
HAL_GPIO_PULL_DISABLED = (GPIO_PIN_CNF_PULL_Disabled << GPIO_PIN_CNF_PULL_Pos),
HAL_GPIO_PULL_DOWN = (GPIO_PIN_CNF_PULL_Pulldown << GPIO_PIN_CNF_PULL_Pos),
HAL_GPIO_PULL_UP = (GPIO_PIN_CNF_PULL_Pullup << GPIO_PIN_CNF_PULL_Pos)
} hal_gpio_pull_t;
typedef enum {
HAL_GPIO_MODE_OUTPUT = (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos),
HAL_GPIO_MODE_INPUT = (GPIO_PIN_CNF_DIR_Input << GPIO_PIN_CNF_DIR_Pos),
} hal_gpio_mode_t;
static inline void hal_gpio_cfg_pin(uint8_t port, uint32_t pin_number, hal_gpio_mode_t mode, hal_gpio_pull_t pull) {
GPIO_BASE(port)->PIN_CNF[pin_number] = (GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos)
| (GPIO_PIN_CNF_DRIVE_S0S1 << GPIO_PIN_CNF_DRIVE_Pos)
| pull
| (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos)
| mode;
}
static inline void hal_gpio_out_set(uint8_t port, uint32_t pin_mask) {
GPIO_BASE(port)->OUTSET = pin_mask;
}
static inline void hal_gpio_out_clear(uint8_t port, uint32_t pin_mask) {
GPIO_BASE(port)->OUTCLR = pin_mask;
}
static inline void hal_gpio_pin_set(uint8_t port, uint32_t pin) {
GPIO_BASE(port)->OUTSET = (1 << pin);
}
static inline void hal_gpio_pin_clear(uint8_t port, uint32_t pin) {
GPIO_BASE(port)->OUTCLR = (1 << pin);
}
static inline void hal_gpio_pin_toggle(uint8_t port, uint32_t pin) {
uint32_t pin_mask = (1 << pin);
uint32_t pins_state = NRF_GPIO->OUT;
GPIO_BASE(port)->OUTSET = (~pins_state) & pin_mask;
GPIO_BASE(port)->OUTCLR = pins_state & pin_mask;
}
typedef enum {
HAL_GPIO_EVENT_CHANNEL_0 = 0,
HAL_GPIO_EVENT_CHANNEL_1,
HAL_GPIO_EVENT_CHANNEL_2,
HAL_GPIO_EVENT_CHANNEL_3,
#if NRF52
HAL_GPIO_EVENT_CHANNEL_4,
HAL_GPIO_EVENT_CHANNEL_5,
HAL_GPIO_EVENT_CHANNEL_6,
HAL_GPIO_EVENT_CHANNEL_7
#endif
} hal_gpio_event_channel_t;
typedef struct {
hal_gpio_event_channel_t channel;
hal_gpio_polarity_event_t event;
uint32_t pin;
uint8_t port;
uint8_t init_level;
} hal_gpio_event_config_t;
typedef void (*hal_gpio_event_callback_t)(hal_gpio_event_channel_t channel);
void hal_gpio_register_callback(hal_gpio_event_callback_t cb);
void hal_gpio_event_config(hal_gpio_event_config_t const * p_config);
#endif // HAL_GPIO_H__

119
ports/nrf/hal/hal_irq.h
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/*
* This file is part of the MicroPython project, http://micropython.org/
*
* The MIT License (MIT)
*
* Copyright (c) 2017 Glenn Ruben Bakke
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
#ifndef HAL_IRQ_H__
#define HAL_IRQ_H__
#include <stdint.h>
#include "nrf.h"
#if BLUETOOTH_SD
#include "py/nlr.h"
#include "ble_drv.h"
#define BLUETOOTH_STACK_ENABLED() (ble_drv_stack_enabled())
#ifdef NRF51
#include "nrf_soc.h"
#elif defined(NRF52)
#include "nrf_nvic.h"
#endif
#endif // BLUETOOTH_SD
static inline void hal_irq_clear(uint32_t irq_num) {
#if BLUETOOTH_SD
if (BLUETOOTH_STACK_ENABLED() == 1) {
if (sd_nvic_ClearPendingIRQ(irq_num) != 0) {
nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError,
"IRQ (%d) clear error", irq_num));
}
} else
#endif // BLUETOOTH_SD
{
NVIC_ClearPendingIRQ(irq_num);
}
}
static inline void hal_irq_enable(uint32_t irq_num) {
hal_irq_clear(irq_num);
#if BLUETOOTH_SD
if (BLUETOOTH_STACK_ENABLED() == 1) {
if (sd_nvic_EnableIRQ(irq_num) != 0) {
nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError,
"IRQ (%d) enable error", irq_num));
}
} else
#endif // BLUETOOTH_SD
{
NVIC_EnableIRQ(irq_num);
}
}
static inline void hal_irq_disable(uint32_t irq_num) {
#if BLUETOOTH_SD
if (BLUETOOTH_STACK_ENABLED() == 1) {
if (sd_nvic_DisableIRQ(irq_num) != 0) {
nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError,
"IRQ (%d) disable error", irq_num));
}
} else
#endif // BLUETOOTH_SD
{
NVIC_DisableIRQ(irq_num);
}
}
static inline void hal_irq_priority(uint32_t irq_num, uint8_t priority) {
#if BLUETOOTH_SD
if (BLUETOOTH_STACK_ENABLED() == 1) {
if (sd_nvic_SetPriority(irq_num, priority) != 0) {
nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError,
"IRQ (%d) priority error", irq_num, priority));
}
} else
#endif // BLUETOOTH_SD
{
NVIC_SetPriority(irq_num, priority);
}
}
static inline void hal_irq_pending(uint32_t irq_num) {
#if BLUETOOTH_SD
if (BLUETOOTH_STACK_ENABLED() == 1) {
if (sd_nvic_SetPendingIRQ(irq_num) != 0) {
nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError,
"IRQ (%d) pending error", irq_num));
}
} else
#endif // BLUETOOTH_SD
{
NVIC_SetPendingIRQ(irq_num);
}
}
#endif // HAL_IRQ_H__

209
ports/nrf/hal/hal_nvmc.c
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/*
* This file is part of the MicroPython project, http://micropython.org/
*
* The MIT License (MIT)
*
* Copyright (c) 2017 Ayke van Laethem
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
#include <stdio.h>
#include "mphalport.h"
#include "hal_nvmc.h"
#if BLUETOOTH_SD
#include "ble_drv.h"
#include "nrf_soc.h"
#endif
#ifdef HAL_NVMC_MODULE_ENABLED
// Rotates bits in `value` left `shift` times.
STATIC inline uint32_t rotate_left(uint32_t value, uint32_t shift) {
return (value << shift) | (value >> (32 - shift));
}
#if BLUETOOTH_SD
STATIC volatile uint8_t hal_nvmc_operation_state = HAL_NVMC_BUSY;
STATIC void operation_init() {
hal_nvmc_operation_state = HAL_NVMC_BUSY;
}
void hal_nvmc_operation_finished(uint8_t result) {
hal_nvmc_operation_state = result;
}
STATIC bool operation_wait(uint32_t result) {
if (ble_drv_stack_enabled() != 1) {
// SoftDevice is not enabled, no event will be generated.
return result == NRF_SUCCESS;
}
if (result != NRF_SUCCESS) {
// In all other (non-success) cases, the command hasn't been
// started and no event will be generated.
return false;
}
// Wait until the event has been generated.
while (hal_nvmc_operation_state == HAL_NVMC_BUSY) {
__WFE();
}
// Now we can safely continue, flash operation has completed.
return hal_nvmc_operation_state == HAL_NVMC_SUCCESS;
}
bool hal_nvmc_erase_page(uint32_t pageaddr) {
operation_init();
uint32_t result = sd_flash_page_erase(pageaddr / HAL_NVMC_PAGESIZE);
return operation_wait(result);
}
bool hal_nvmc_write_words(uint32_t *dest, const uint32_t *buf, size_t len) {
operation_init();
uint32_t result = sd_flash_write(dest, buf, len);
return operation_wait(result);
}
bool hal_nvmc_write_byte(byte *dest_in, byte b) {
uint32_t dest = (uint32_t)dest_in;
uint32_t dest_aligned = dest & ~3;
// Value to write - leave all bits that should not change at 0xff.
uint32_t value = 0xffffff00 | b;
// Rotate bits in value to an aligned position.
value = rotate_left(value, (dest & 3) * 8);
operation_init();
uint32_t result = sd_flash_write((uint32_t*)dest_aligned, &value, 1);
return operation_wait(result);
}
#else // BLUETOOTH_SD
bool hal_nvmc_erase_page(uint32_t pageaddr) {
// Configure NVMC to erase a page.
NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Een;
while (NRF_NVMC->READY == NVMC_READY_READY_Busy) {}
// Set the page to erase
NRF_NVMC->ERASEPAGE = pageaddr;
while (NRF_NVMC->READY == NVMC_READY_READY_Busy) {}
// Switch back to read-only.
NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Ren;
while (NRF_NVMC->READY == NVMC_READY_READY_Busy) {}
// Operation succeeded.
return true;
}
bool hal_nvmc_write_words(uint32_t *dest, const uint32_t *buf, size_t len) {
// Note that we're writing 32-bit integers, not bytes. Thus the 'real'
// length of the buffer is len*4.
// Configure NVMC so that writes are allowed (anywhere).
NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Wen;
while (NRF_NVMC->READY == NVMC_READY_READY_Busy) {}
// Write all integers to flash.
for (int i = 0; i < len; i++) {
dest[i] = buf[i];
while (NRF_NVMC->READY == NVMC_READY_READY_Busy) {}
}
// Switch back to read-only.
NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Ren;
while (NRF_NVMC->READY == NVMC_READY_READY_Busy) {}
// Operation succeeded.
return true;
}
bool hal_nvmc_write_byte(byte *dest_in, byte b) {
// This code can probably be optimized.
// Configure NVMC so that writes are allowed (anywhere).
NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Wen;
while (NRF_NVMC->READY == NVMC_READY_READY_Busy) {}
// According to the nRF51 RM (chapter 6), only word writes to
// word-aligned addresses are allowed.
// https://www.nordicsemi.com/eng/nordic/Products/nRF51822/nRF51-RM/62725
uint32_t dest = (uint32_t)dest_in;
uint32_t dest_aligned = dest & ~3;
// Value to write - leave all bits that should not change at 0xff.
uint32_t value = 0xffffff00 | b;
// Rotate bits in value to an aligned position.
value = rotate_left(value, (dest & 3) * 8);
// Put the value at the right place.
*(uint32_t*)dest_aligned = value;
while (NRF_NVMC->READY == NVMC_READY_READY_Busy) {}
// Switch back to read-only.
NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Ren;
while (NRF_NVMC->READY == NVMC_READY_READY_Busy) {}
// Operation succeeded.
return true;
}
#endif // BLUETOOTH_SD
bool hal_nvmc_write_buffer(void *dest_in, const void *buf_in, size_t len) {
byte *dest = dest_in;
const byte *buf = buf_in;
// Write first bytes to align the buffer.
while (len && ((uint32_t)dest & 0b11)) {
hal_nvmc_write_byte(dest, *buf);
dest++;
buf++;
len--;
}
// Now the start of the buffer is aligned. Write as many words as
// possible, as that's much faster than writing bytes.
if (len / 4 && ((uint32_t)buf & 0b11) == 0) {
hal_nvmc_write_words((uint32_t*)dest, (const uint32_t*)buf, len / 4);
dest += len & ~0b11;
buf += len & ~0b11;
len = len & 0b11;
}
// Write remaining unaligned bytes.
while (len) {
hal_nvmc_write_byte(dest, *buf);
dest++;
buf++;
len--;
}
return true;
}
#endif // HAL_NVMC_MODULE_ENABLED

68
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@ -1,68 +0,0 @@
/*
* This file is part of the MicroPython project, http://micropython.org/
*
* The MIT License (MIT)
*
* Copyright (c) 2017 Ayke van Laethem
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
#ifndef HAL_NVMC_H__
#define HAL_NVMC_H__
#include <stdint.h>
#include "nrf.h"
// Erase a single page. The pageaddr is an address within the first page.
bool hal_nvmc_erase_page(uint32_t pageaddr);
// Write an array of 32-bit words to flash. The len parameter is the
// number of words, not the number of bytes. Dest and buf must be aligned.
bool hal_nvmc_write_words(uint32_t *dest, const uint32_t *buf, size_t len);
// Write a byte to flash. May have any alignment.
bool hal_nvmc_write_byte(byte *dest, byte b);
// Write an (unaligned) byte buffer to flash.
bool hal_nvmc_write_buffer(void *dest_in, const void *buf_in, size_t len);
// Call for ble_drv.c: notify (from an interrupt) that the current flash
// operation has finished.
void hal_nvmc_operation_finished(uint8_t result);
enum {
HAL_NVMC_BUSY,
HAL_NVMC_SUCCESS,
HAL_NVMC_ERROR,
};
#if defined(NRF51)
#define HAL_NVMC_PAGESIZE (1024)
#elif defined(NRF52)
#define HAL_NVMC_PAGESIZE (4096)
#else
#error Unknown chip
#endif
#define HAL_NVMC_IS_PAGE_ALIGNED(addr) ((uint32_t)(addr) & (HAL_NVMC_PAGESIZE - 1))
#endif // HAL_NVMC_H__

118
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/*
* This file is part of the MicroPython project, http://micropython.org/
*
* The MIT License (MIT)
*
* Copyright (c) 2016 Glenn Ruben Bakke
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
#include <stdint.h>
#include <stdio.h>
#include "mphalport.h"
#include "hal_pwm.h"
#ifdef HAL_PWM_MODULE_ENABLED
#define PWM_COUNTER_TOP 16000 // 16MHz divided by 16000-> 1ms
volatile uint16_t g_pwm_seq[4];
volatile uint16_t g_pwm_period;
static const uint32_t hal_pwm_frequency_lookup[] = {
PWM_PRESCALER_PRESCALER_DIV_1, // 16MHz
PWM_PRESCALER_PRESCALER_DIV_2, // 8MHz
PWM_PRESCALER_PRESCALER_DIV_4, // 4MHz
PWM_PRESCALER_PRESCALER_DIV_8, // 2MHz
PWM_PRESCALER_PRESCALER_DIV_16, // 1MHz
PWM_PRESCALER_PRESCALER_DIV_32, // 500kHz
PWM_PRESCALER_PRESCALER_DIV_64, // 250kHz
PWM_PRESCALER_PRESCALER_DIV_128 // 125kHz
};
void hal_pwm_init(NRF_PWM_Type * p_instance, hal_pwm_init_t const * p_pwm_init) {
g_pwm_period = p_pwm_init->period;
uint16_t pulse_width = ((g_pwm_period * p_pwm_init->duty)/100);
if (p_pwm_init->pulse_width > 0) {
pulse_width = p_pwm_init->pulse_width;
}
if (p_pwm_init->mode == HAL_PWM_MODE_HIGH_LOW) {
g_pwm_seq[0] = g_pwm_period - pulse_width;
g_pwm_seq[1] = g_pwm_period - pulse_width;
} else {
g_pwm_seq[0] = pulse_width;
g_pwm_seq[1] = pulse_width;
}
g_pwm_seq[2] = 0;
g_pwm_seq[3] = 0;
p_instance->PSEL.OUT[0] = (p_pwm_init->pwm_pin << PWM_PSEL_OUT_PIN_Pos)
| (PWM_PSEL_OUT_CONNECT_Connected << PWM_PSEL_OUT_CONNECT_Pos);
p_instance->ENABLE = (PWM_ENABLE_ENABLE_Enabled << PWM_ENABLE_ENABLE_Pos);
p_instance->MODE = (PWM_MODE_UPDOWN_Up << PWM_MODE_UPDOWN_Pos);
p_instance->PRESCALER = (hal_pwm_frequency_lookup[p_pwm_init->freq] << PWM_PRESCALER_PRESCALER_Pos);
p_instance->COUNTERTOP = (p_pwm_init->period << PWM_COUNTERTOP_COUNTERTOP_Pos);
p_instance->LOOP = (PWM_LOOP_CNT_Disabled << PWM_LOOP_CNT_Pos);
p_instance->DECODER = (PWM_DECODER_LOAD_Individual << PWM_DECODER_LOAD_Pos)
| (PWM_DECODER_MODE_RefreshCount << PWM_DECODER_MODE_Pos);
p_instance->SEQ[0].PTR = ((uint32_t)(g_pwm_seq) << PWM_SEQ_PTR_PTR_Pos);
p_instance->SEQ[0].CNT = ((sizeof(g_pwm_seq) / sizeof(uint16_t)) << PWM_SEQ_CNT_CNT_Pos);
p_instance->SEQ[0].REFRESH = 0;
p_instance->SEQ[0].ENDDELAY = 0;
}
void hal_pwm_start(NRF_PWM_Type * p_instance) {
p_instance->TASKS_SEQSTART[0] = 1;
}
void hal_pwm_stop(NRF_PWM_Type * p_instance) {
p_instance->TASKS_SEQSTART[0] = 0;
p_instance->ENABLE = (PWM_ENABLE_ENABLE_Disabled << PWM_ENABLE_ENABLE_Pos);
}
void hal_pwm_freq_set(NRF_PWM_Type * p_instance, uint16_t freq) {
#if 0
p_instance->PRESCALER = (hal_pwm_frequency_lookup[freq] << PWM_PRESCALER_PRESCALER_Pos);
#endif
}
void hal_pwm_period_set(NRF_PWM_Type * p_instance, uint16_t period) {
#if 0
g_pwm_period = period;
p_instance->COUNTERTOP = (g_pwm_period << PWM_COUNTERTOP_COUNTERTOP_Pos);
#endif
}
void hal_pwm_duty_set(NRF_PWM_Type * p_instance, uint8_t duty) {
#if 0
uint16_t duty_cycle = ((g_pwm_period * duty)/100);
g_pwm_seq[0] = duty_cycle;
g_pwm_seq[1] = duty_cycle;
#endif
}
#endif // HAL_PWM_MODULE_ENABLED

108
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@ -1,108 +0,0 @@
/*
* This file is part of the MicroPython project, http://micropython.org/
*
* The MIT License (MIT)
*
* Copyright (c) 2016 Glenn Ruben Bakke
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
#ifndef HAL_PWM_H__
#define HAL_PWM_H__
#include <stdint.h>
#include "nrf.h"
// TODO: nrf51 series need Soft PWM. Not part of HAL.
#if NRF52
#define PWM0 ((NRF_PWM_Type *)NRF_PWM0_BASE)
#define PWM0_IRQ_NUM PWM1_IRQn
#define PWM1 ((NRF_PWM_Type *)NRF_PWM1_BASE)
#define PWM1_IRQ_NUM PWM1_IRQn
#define PWM2 ((NRF_PWM_Type *)NRF_PWM2_BASE)
#define PWM2_IRQ_NUM PWM2_IRQn
#if 0 // TODO: nrf52840
#define PWM3 ((NRF_PWM_Type *)NRF_PWM3_BASE)
#define PWM3_IRQ_NUM PWM3_IRQn
#endif
#else
#error "Device not supported."
#endif
/**
* @brief PWM frequency type definition
*/
typedef enum {
HAL_PWM_FREQ_16Mhz = 0,
HAL_PWM_FREQ_8Mhz,
HAL_PWM_FREQ_4Mhz,
HAL_PWM_FREQ_2Mhz,
HAL_PWM_FREQ_1Mhz,
HAL_PWM_FREQ_500khz,
HAL_PWM_FREQ_250khz,
HAL_PWM_FREQ_125khz
} hal_pwm_freq_t;
/**
* @brief PWM mode type definition
*/
typedef enum {
HAL_PWM_MODE_LOW_HIGH = 0,
HAL_PWM_MODE_HIGH_LOW
} hal_pwm_mode_t;
typedef struct {
uint8_t pwm_pin;
hal_pwm_freq_t freq;
uint8_t duty;
uint16_t pulse_width;
uint16_t period;
hal_pwm_mode_t mode;
} hal_pwm_init_t;
/**
* @brief PWM handle Structure definition
*/
typedef struct __PWM_HandleTypeDef
{
NRF_PWM_Type *instance; /* PWM registers base address */
hal_pwm_init_t init; /* PWM initialization parameters */
} PWM_HandleTypeDef;
void hal_pwm_init(NRF_PWM_Type * p_instance, hal_pwm_init_t const * p_pwm_init);
void hal_pwm_freq_set(NRF_PWM_Type * p_instance, uint16_t freq);
void hal_pwm_period_set(NRF_PWM_Type * p_instance, uint16_t period);
void hal_pwm_duty_set(NRF_PWM_Type * p_instance, uint8_t duty);
void hal_pwm_start(NRF_PWM_Type * p_instance);
void hal_pwm_stop(NRF_PWM_Type * p_instance);
#endif // HAL_PWM_H__

122
ports/nrf/hal/hal_qspie.c
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/*
* This file is part of the MicroPython project, http://micropython.org/
*
* The MIT License (MIT)
*
* Copyright (c) 2017 Glenn Ruben Bakke
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
#include "mphalport.h"
#include "hal_qspie.h"
#ifdef HAL_QSPIE_MODULE_ENABLED
#define QSPI_IRQ_NUM QSPI_IRQn
#define QSPI_BASE ((NRF_QSPI_Type *)NRF_QSPI_BASE)
// frequency, 32 MHz / (SCKFREQ + 1)
static const uint32_t hal_qspi_frequency_lookup[] = {
(15 << QSPI_IFCONFIG1_SCKFREQ_Pos), // 2 Mbps
(7 << QSPI_IFCONFIG1_SCKFREQ_Pos), // 4 Mbps
(3 << QSPI_IFCONFIG1_SCKFREQ_Pos), // 8 Mbps
(1 << QSPI_IFCONFIG1_SCKFREQ_Pos), // 16 Mbps
(0 << QSPI_IFCONFIG1_SCKFREQ_Pos), // 32 Mbps
};
void hal_qspi_master_init(NRF_QSPI_Type * p_instance, hal_qspi_init_t const * p_qspi_init)
{
// configure SCK
p_instance->PSEL.SCK = (p_qspi_init->clk_pin << QSPI_PSEL_SCK_PIN_Pos)
| (p_qspi_init->clk_pin_port << QSPI_PSEL_SCK_PORT_Pos)
| (QSPI_PSEL_SCK_CONNECT_Connected << QSPI_PSEL_SCK_CONNECT_Pos);
// configure CS
if (p_qspi_init->use_csn) {
p_instance->PSEL.CSN = (p_qspi_init->clk_pin << QSPI_PSEL_CSN_PIN_Pos)
| (p_qspi_init->clk_pin_port << QSPI_PSEL_CSN_PORT_Pos)
| (QSPI_PSEL_CSN_CONNECT_Connected << QSPI_PSEL_CSN_CONNECT_Pos);
} else {
p_instance->PSEL.CSN = (QSPI_PSEL_CSN_CONNECT_Disconnected << QSPI_PSEL_CSN_CONNECT_Pos);
}
// configure MOSI/IO0, valid for all configurations
p_instance->PSEL.IO0 = (p_qspi_init->d0_mosi_pin << QSPI_PSEL_IO0_PIN_Pos)
| (p_qspi_init->d0_mosi_pin_port << QSPI_PSEL_IO0_PORT_Pos)
| (QSPI_PSEL_IO0_CONNECT_Connected << QSPI_PSEL_IO0_CONNECT_Pos);
if (p_qspi_init->data_line != HAL_QSPI_DATA_LINE_SINGLE) {
// configure MISO/IO1
p_instance->PSEL.IO1 = (p_qspi_init->d1_miso_pin << QSPI_PSEL_IO1_PIN_Pos)
| (p_qspi_init->d1_miso_pin_port << QSPI_PSEL_IO1_PORT_Pos)
| (QSPI_PSEL_IO1_CONNECT_Connected << QSPI_PSEL_IO1_CONNECT_Pos);
if (p_qspi_init->data_line == HAL_QSPI_DATA_LINE_QUAD) {
// configure IO2
p_instance->PSEL.IO2 = (p_qspi_init->d2_pin << QSPI_PSEL_IO2_PIN_Pos)
| (p_qspi_init->d2_pin_port << QSPI_PSEL_IO2_PORT_Pos)
| (QSPI_PSEL_IO2_CONNECT_Connected << QSPI_PSEL_IO2_CONNECT_Pos);
// configure IO3
p_instance->PSEL.IO3 = (p_qspi_init->d3_pin << QSPI_PSEL_IO3_PIN_Pos)
| (p_qspi_init->d3_pin_port << QSPI_PSEL_IO3_PORT_Pos)
| (QSPI_PSEL_IO3_CONNECT_Connected << QSPI_PSEL_IO3_CONNECT_Pos);
}
}
uint32_t mode;
switch (p_qspi_init->mode) {
case HAL_SPI_MODE_CPOL0_CPHA0:
mode = (QSPI_IFCONFIG1_SPIMODE_MODE0 << QSPI_IFCONFIG1_SPIMODE_Pos);
break;
case HAL_SPI_MODE_CPOL1_CPHA1:
mode = (QSPI_IFCONFIG1_SPIMODE_MODE3 << QSPI_IFCONFIG1_SPIMODE_Pos);
break;
default:
mode = 0;
break;
}
// interface config1
p_instance->IFCONFIG1 = hal_qspi_frequency_lookup[p_qspi_init->freq]
| mode
| (1 << QSPI_IFCONFIG1_SCKDELAY_Pos); // number of 16 MHz periods (62.5 ns)
p_instance->ENABLE = 1;
}
void hal_qspi_master_tx_rx(NRF_QSPI_Type * p_instance,
uint16_t transfer_size,
const uint8_t * tx_data,
uint8_t * rx_data)
{
p_instance->READ.DST = (uint32_t)rx_data;
p_instance->READ.CNT = transfer_size;
p_instance->READ.SRC = (uint32_t)tx_data;
p_instance->READ.CNT = transfer_size;
p_instance->TASKS_ACTIVATE = 1;
while (p_instance->EVENTS_READY == 0) {
;
}
p_instance->TASKS_ACTIVATE = 0;
}
#endif // HAL_QSPIE_MODULE_ENABLED

110
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@ -1,110 +0,0 @@
/*
* This file is part of the MicroPython project, http://micropython.org/
*
* The MIT License (MIT)
*
* Copyright (c) 2017 Glenn Ruben Bakke
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
#ifndef HAL_QSPIE_H__
#define HAL_QSPIE_H__
#ifdef HAL_QSPIE_MODULE_ENABLED
#if NRF52840_XXAA
#include <nrf.h>
#else
#error "Device not supported."
#endif
/**
* @brief Quad SPI clock frequency type definition
*/
typedef enum {
HAL_FREQ_2_Mbps,
HAL_FREQ_4_Mbps,
HAL_FREQ_8_Mbps,
HAL_FREQ_16_Mbps,
HAL_FREQ_32_Mbps
} hal_qspi_clk_freq_t;
/**
* @brief Quad SPI mode type definition
*/
typedef enum {
HAL_SPI_MODE_CPOL0_CPHA0 = 0, // CPOL = 0, CPHA = 0 (data on leading edge)
HAL_SPI_MODE_CPOL1_CPHA1 = 3 // CPOL = 1, CPHA = 1 (data on trailing edge)
} hal_qspi_mode_t;
/**
* @brief Quad SPI data line configuration type definition
*/
typedef enum {
HAL_QSPI_DATA_LINE_SINGLE,
HAL_QSPI_DATA_LINE_DUAL,
HAL_QSPI_DATA_LINE_QUAD
} hal_qspi_data_line_t;
/**
* @brief Quad SPI Configuration Structure definition
*/
typedef struct {
uint8_t d0_mosi_pin;
uint8_t d1_miso_pin;
uint8_t d2_pin;
uint8_t d3_pin;
uint8_t clk_pin;
uint8_t csn_pin;
uint8_t d0_mosi_pin_port;
uint8_t d1_miso_pin_port;
uint8_t d2_pin_port;
uint8_t d3_pin_port;
uint8_t clk_pin_port;
uint8_t csn_pin_port;
bool use_csn;
hal_qspi_mode_t mode;
hal_qspi_data_line_t data_line;
hal_qspi_clk_freq_t freq;
} hal_qspi_init_t;
/**
* @brief Quad SPI handle Structure definition
*/
typedef struct __QSPI_HandleTypeDef
{
NRF_QSPI_Type *instance; /* QSPI registers base address */
hal_qspi_init_t init; /* QSPI initialization parameters */
} QSPI_HandleTypeDef;
void hal_qspi_master_init(NRF_QSPI_Type * p_instance, hal_qspi_init_t const * p_qspi_init);
void hal_qspi_master_tx_rx(NRF_QSPI_Type * p_instance,
uint16_t transfer_size,
const uint8_t * tx_data,
uint8_t * rx_data);
#endif // HAL_QSPIE_MODULE_ENABLED
#endif // HAL_QSPIE_H__

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@ -1,76 +0,0 @@
/*
* This file is part of the MicroPython project, http://micropython.org/
*
* The MIT License (MIT)
*
* Copyright (c) 2017 Glenn Ruben Bakke
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
#include "mphalport.h"
#include "hal_rng.h"
#ifdef HAL_RNG_MODULE_ENABLED
#if BLUETOOTH_SD
#include "py/nlr.h"
#include "ble_drv.h"
#include "nrf_soc.h"
#define BLUETOOTH_STACK_ENABLED() (ble_drv_stack_enabled())
#endif // BLUETOOTH_SD
uint32_t hal_rng_generate(void) {
uint32_t retval = 0;
#if BLUETOOTH_SD
if (BLUETOOTH_STACK_ENABLED() == 1) {
uint32_t status;
do {
status = sd_rand_application_vector_get((uint8_t *)&retval, 4); // Extract 4 bytes
} while (status != 0);
} else {
#endif
uint8_t * p_retval = (uint8_t *)&retval;
NRF_RNG->EVENTS_VALRDY = 0;
NRF_RNG->TASKS_START = 1;
for (uint16_t i = 0; i < 4; i++) {
while (NRF_RNG->EVENTS_VALRDY == 0) {
;
}
NRF_RNG->EVENTS_VALRDY = 0;
p_retval[i] = NRF_RNG->VALUE;
}
NRF_RNG->TASKS_STOP = 1;
#if BLUETOOTH_SD
}
#endif
return retval;
}
#endif // HAL_RNG_MODULE_ENABLED

34
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@ -1,34 +0,0 @@
/*
* This file is part of the MicroPython project, http://micropython.org/
*
* The MIT License (MIT)
*
* Copyright (c) 2017 Glenn Ruben Bakke
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
#ifndef HAL_RNG_H__
#define HAL_RNG_H__
#include "nrf.h"
uint32_t hal_rng_generate(void);
#endif // HAL_RNG_H__

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/*
* This file is part of the MicroPython project, http://micropython.org/
*
* The MIT License (MIT)
*
* Copyright (c) 2016 Glenn Ruben Bakke
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
#include "mphalport.h"
#include "hal_rtc.h"
#include "hal_irq.h"
#ifdef HAL_RTC_MODULE_ENABLED
#define HAL_LFCLK_FREQ (32768UL)
#define HAL_RTC_FREQ (10UL)
#define HAL_RTC_COUNTER_PRESCALER ((HAL_LFCLK_FREQ/HAL_RTC_FREQ)-1)
static hal_rtc_app_callback m_callback;
static uint32_t m_period[sizeof(RTC_BASE_POINTERS) / sizeof(uint32_t)];
void hal_rtc_callback_set(hal_rtc_app_callback callback) {
m_callback = callback;
}
void hal_rtc_init(hal_rtc_conf_t const * p_rtc_conf) {
NRF_RTC_Type * p_rtc = RTC_BASE(p_rtc_conf->id);
// start LFCLK if not already started
if (NRF_CLOCK->LFCLKSTAT == 0) {
NRF_CLOCK->TASKS_LFCLKSTART = 1;
while (NRF_CLOCK->EVENTS_LFCLKSTARTED == 0);
NRF_CLOCK->EVENTS_LFCLKSTARTED = 0;
}
m_period[p_rtc_conf->id] = p_rtc_conf->period;
p_rtc->PRESCALER = HAL_RTC_COUNTER_PRESCALER;
hal_irq_priority(RTC_IRQ_NUM(p_rtc_conf->id), p_rtc_conf->irq_priority);
}
void hal_rtc_start(uint8_t id) {
NRF_RTC_Type * p_rtc = RTC_BASE(id);
uint32_t period = HAL_RTC_FREQ * m_period[id];
uint32_t counter = p_rtc->COUNTER;
p_rtc->CC[0] = counter + period;
p_rtc->EVTENSET = RTC_EVTEN_COMPARE0_Msk;
p_rtc->INTENSET = RTC_INTENSET_COMPARE0_Msk;
hal_irq_clear(RTC_IRQ_NUM(id));
hal_irq_enable(RTC_IRQ_NUM(id));
p_rtc->TASKS_START = 1;
}
void hal_rtc_stop(uint8_t id) {
NRF_RTC_Type * p_rtc = RTC_BASE(id);
p_rtc->EVTENCLR = RTC_EVTEN_COMPARE0_Msk;
p_rtc->INTENCLR = RTC_INTENSET_COMPARE0_Msk;
hal_irq_disable(RTC_IRQ_NUM(id));
p_rtc->TASKS_STOP = 1;
}
static void common_irq_handler(uint8_t id) {
NRF_RTC_Type * p_rtc = RTC_BASE(id);
// clear all events
p_rtc->EVENTS_COMPARE[0] = 0;
p_rtc->EVENTS_COMPARE[1] = 0;
p_rtc->EVENTS_COMPARE[2] = 0;
p_rtc->EVENTS_COMPARE[3] = 0;
p_rtc->EVENTS_TICK = 0;
p_rtc->EVENTS_OVRFLW = 0;
m_callback(id);
}
void RTC0_IRQHandler(void)
{
common_irq_handler(0);
}
void RTC1_IRQHandler(void)
{
common_irq_handler(1);
}
#if NRF52
void RTC2_IRQHandler(void)
{
common_irq_handler(2);
}
#endif // NRF52
#endif // HAL_RTC_MODULE_ENABLED

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/*
* This file is part of the MicroPython project, http://micropython.org/
*
* The MIT License (MIT)
*
* Copyright (c) 2016 Glenn Ruben Bakke
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
#ifndef HAL_RTC_H__
#define HAL_RTC_H__
#include "nrf.h"
#if NRF51
#define RTC_BASE_POINTERS (const uint32_t[]){NRF_RTC0_BASE, \
NRF_RTC1_BASE}
#define RTC_IRQ_VALUES (const uint32_t[]){RTC0_IRQn, \
RTC1_IRQn}
#endif
#if NRF52
#define RTC_BASE_POINTERS (const uint32_t[]){NRF_RTC0_BASE, \
NRF_RTC1_BASE, \
NRF_RTC2_BASE}
#define RTC_IRQ_VALUES (const uint32_t[]){RTC0_IRQn, \
RTC1_IRQn, \
RTC2_IRQn}
#endif
#define RTC_BASE(x) ((NRF_RTC_Type *)RTC_BASE_POINTERS[x])
#define RTC_IRQ_NUM(x) (RTC_IRQ_VALUES[x])
typedef void (*hal_rtc_app_callback)(uint8_t id);
/**
* @brief RTC Configuration Structure definition
*/
typedef struct {
uint8_t id; /* RTC instance id */
uint32_t period; /* RTC period in ms */
uint32_t irq_priority; /* RTC IRQ priority */
} hal_rtc_conf_t;
void hal_rtc_callback_set(hal_rtc_app_callback callback);
void hal_rtc_init(hal_rtc_conf_t const * p_rtc_config);
void hal_rtc_start(uint8_t id);
void hal_rtc_stop(uint8_t id);
#endif // HAL_RTC_H__

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/*
* This file is part of the MicroPython project, http://micropython.org/
*
* The MIT License (MIT)
*
* Copyright (c) 2016 Glenn Ruben Bakke
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
#include <stdint.h>
#include <stdio.h>
#include "mphalport.h"
#include "hal_spi.h"
#ifdef HAL_SPI_MODULE_ENABLED
static const uint32_t hal_spi_frequency_lookup[] = {
SPI_FREQUENCY_FREQUENCY_K125, // 125 kbps
SPI_FREQUENCY_FREQUENCY_K250, // 250 kbps
SPI_FREQUENCY_FREQUENCY_K500, // 500 kbps
SPI_FREQUENCY_FREQUENCY_M1, // 1 Mbps
SPI_FREQUENCY_FREQUENCY_M2, // 2 Mbps
SPI_FREQUENCY_FREQUENCY_M4, // 4 Mbps
SPI_FREQUENCY_FREQUENCY_M8 // 8 Mbps
};
void hal_spi_master_init(NRF_SPI_Type * p_instance, hal_spi_init_t const * p_spi_init) {
hal_gpio_cfg_pin(p_spi_init->clk_pin->port, p_spi_init->clk_pin->pin, HAL_GPIO_MODE_OUTPUT, HAL_GPIO_PULL_DISABLED);
hal_gpio_cfg_pin(p_spi_init->mosi_pin->port, p_spi_init->mosi_pin->pin, HAL_GPIO_MODE_OUTPUT, HAL_GPIO_PULL_DISABLED);
hal_gpio_cfg_pin(p_spi_init->miso_pin->port, p_spi_init->miso_pin->pin, HAL_GPIO_MODE_INPUT, HAL_GPIO_PULL_DISABLED);
#if NRF51
p_instance->PSELSCK = p_spi_init->clk_pin->pin;
p_instance->PSELMOSI = p_spi_init->mosi_pin->pin;
p_instance->PSELMISO = p_spi_init->miso_pin->pin;
#else
p_instance->PSEL.SCK = p_spi_init->clk_pin->pin;
p_instance->PSEL.MOSI = p_spi_init->mosi_pin->pin;
p_instance->PSEL.MISO = p_spi_init->miso_pin->pin;
#if NRF52840_XXAA
p_instance->PSEL.SCK |= (p_spi_init->clk_pin->port << SPI_PSEL_SCK_PORT_Pos);
p_instance->PSEL.MOSI |= (p_spi_init->mosi_pin->port << SPI_PSEL_MOSI_PORT_Pos);
p_instance->PSEL.MISO |= (p_spi_init->miso_pin->port << SPI_PSEL_MISO_PORT_Pos);
#endif
#endif
p_instance->FREQUENCY = hal_spi_frequency_lookup[p_spi_init->freq];
uint32_t mode;
switch (p_spi_init->mode) {
case HAL_SPI_MODE_CPOL0_CPHA0:
mode = (SPI_CONFIG_CPHA_Leading << SPI_CONFIG_CPHA_Pos) | (SPI_CONFIG_CPOL_ActiveHigh << SPI_CONFIG_CPOL_Pos);
break;
case HAL_SPI_MODE_CPOL0_CPHA1:
mode = (SPI_CONFIG_CPHA_Trailing << SPI_CONFIG_CPHA_Pos) | (SPI_CONFIG_CPOL_ActiveHigh << SPI_CONFIG_CPOL_Pos);
break;
case HAL_SPI_MODE_CPOL1_CPHA0:
mode = (SPI_CONFIG_CPHA_Leading << SPI_CONFIG_CPHA_Pos) | (SPI_CONFIG_CPOL_ActiveLow << SPI_CONFIG_CPOL_Pos);
break;
case HAL_SPI_MODE_CPOL1_CPHA1:
mode = (SPI_CONFIG_CPHA_Trailing << SPI_CONFIG_CPHA_Pos) | (SPI_CONFIG_CPOL_ActiveLow << SPI_CONFIG_CPOL_Pos);
break;
default:
mode = 0;
break;
}
if (p_spi_init->firstbit == HAL_SPI_LSB_FIRST) {
p_instance->CONFIG = (mode | (SPI_CONFIG_ORDER_LsbFirst << SPI_CONFIG_ORDER_Pos));
} else {
p_instance->CONFIG = (mode | (SPI_CONFIG_ORDER_MsbFirst << SPI_CONFIG_ORDER_Pos));
}
p_instance->EVENTS_READY = 0U;
p_instance->ENABLE = (SPI_ENABLE_ENABLE_Enabled << SPI_ENABLE_ENABLE_Pos);
}
void hal_spi_master_tx_rx(NRF_SPI_Type * p_instance,
uint16_t transfer_size,
const uint8_t * tx_data,
uint8_t * rx_data) {
uint16_t number_of_txd_bytes = 0;
p_instance->EVENTS_READY = 0;
while (number_of_txd_bytes < transfer_size) {
p_instance->TXD = (uint32_t)(tx_data[number_of_txd_bytes]);
// wait for the transaction complete or timeout (about 10ms - 20 ms)
while (p_instance->EVENTS_READY == 0) {
;
}
p_instance->EVENTS_READY = 0;
uint8_t in_byte = (uint8_t)p_instance->RXD;
if (rx_data != NULL) {
rx_data[number_of_txd_bytes] = in_byte;
}
number_of_txd_bytes++;
};
}
#endif // HAL_SPI_MODULE_ENABLED

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/*
* This file is part of the MicroPython project, http://micropython.org/
*
* The MIT License (MIT)
*
* Copyright (c) 2016 Glenn Ruben Bakke
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
#ifndef HAL_SPI_H__
#define HAL_SPI_H__
#include <stdbool.h>
#include "nrf.h"
#if NRF51
#define SPI_BASE_POINTERS (const uint32_t[]){NRF_SPI0_BASE, NRF_SPI1_BASE}
#define SPI_IRQ_VALUES (const uint32_t[]){SPI0_TWI0_IRQn, SPI1_TWI1_IRQn}
#endif
#if NRF52
#ifdef NRF52832_XXAA
#define SPI_BASE_POINTERS (const uint32_t[]){NRF_SPI0_BASE, \
NRF_SPI1_BASE, \
NRF_SPI2_BASE}
#define SPI_IRQ_VALUES (const uint32_t[]){SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQn, \
SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQn, \
SPIM2_SPIS2_SPI2_IRQn}
#endif
#ifdef NRF52840_XXAA
#define SPI_BASE_POINTERS (const uint32_t[]){NRF_SPI0_BASE, \
NRF_SPI1_BASE, \
NRF_SPI2_BASE, \
NRF_SPIM3_BASE}
#define SPI_IRQ_VALUES (const uint32_t[]){SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQn, \
SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQn, \
SPIM2_SPIS2_SPI2_IRQn, \
SPIM3_IRQn}
#endif
#endif
#define SPI_BASE(x) ((NRF_SPI_Type *)SPI_BASE_POINTERS[x])
#define SPI_IRQ_NUM(x) (SPI_IRQ_VALUES[x])
/**
* @brief SPI clock frequency type definition
*/
typedef enum {
HAL_SPI_FREQ_125_Kbps = 0,
HAL_SPI_FREQ_250_Kbps,
HAL_SPI_FREQ_500_Kbps,
HAL_SPI_FREQ_1_Mbps,
HAL_SPI_FREQ_2_Mbps,
HAL_SPI_FREQ_4_Mbps,
HAL_SPI_FREQ_8_Mbps,
#if NRF52840_XXAA
HAL_SPI_FREQ_16_Mbps,
HAL_SPI_FREQ_32_Mbps
#endif
} hal_spi_clk_freq_t;
/**
* @brief SPI mode type definition
*/
typedef enum {
HAL_SPI_MODE_CPOL0_CPHA0 = 0, // CPOL = 0, CPHA = 0 (data on leading edge)
HAL_SPI_MODE_CPOL0_CPHA1, // CPOL = 0, CPHA = 1 (data on trailing edge)
HAL_SPI_MODE_CPOL1_CPHA0, // CPOL = 1, CPHA = 0 (data on leading edge)
HAL_SPI_MODE_CPOL1_CPHA1 // CPOL = 1, CPHA = 1 (data on trailing edge)
} hal_spi_mode_t;
/**
* @brief SPI firstbit mode definition
*/
typedef enum {
HAL_SPI_MSB_FIRST = 0,
HAL_SPI_LSB_FIRST
} hal_spi_firstbit_t;
/**
* @brief SPI Configuration Structure definition
*/
typedef struct {
const pin_obj_t * mosi_pin;
const pin_obj_t * miso_pin;
const pin_obj_t * clk_pin;
hal_spi_firstbit_t firstbit;
hal_spi_mode_t mode;
uint32_t irq_priority;
hal_spi_clk_freq_t freq;
} hal_spi_init_t;
/**
* @brief SPI handle Structure definition
*/
typedef struct __SPI_HandleTypeDef
{
NRF_SPI_Type *instance; /* SPI registers base address */
hal_spi_init_t init; /* SPI initialization parameters */
} SPI_HandleTypeDef;
void hal_spi_master_init(NRF_SPI_Type * p_instance, hal_spi_init_t const * p_spi_init);
void hal_spi_master_tx_rx(NRF_SPI_Type * p_instance,
uint16_t transfer_size,
const uint8_t * tx_data,
uint8_t * rx_data);
#endif // HAL_SPI_H__

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/*
* This file is part of the MicroPython project, http://micropython.org/
*
* The MIT License (MIT)
*
* Copyright (c) 2016 Glenn Ruben Bakke
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
#include <stdint.h>
#include <stdio.h>
#include "mphalport.h"
#include "hal_spi.h"
#ifdef HAL_SPIE_MODULE_ENABLED
static const uint32_t hal_spi_frequency_lookup[] = {
SPIM_FREQUENCY_FREQUENCY_K125, // 125 kbps
SPIM_FREQUENCY_FREQUENCY_K250, // 250 kbps
SPIM_FREQUENCY_FREQUENCY_K500, // 500 kbps
SPIM_FREQUENCY_FREQUENCY_M1, // 1 Mbps
SPIM_FREQUENCY_FREQUENCY_M2, // 2 Mbps
SPIM_FREQUENCY_FREQUENCY_M4, // 4 Mbps
SPIM_FREQUENCY_FREQUENCY_M8, // 8 Mbps
#if NRF52840_XXAA
SPIM_FREQUENCY_FREQUENCY_M16, // 16 Mbps
SPIM_FREQUENCY_FREQUENCY_M32, // 32 Mbps
#endif
};
void hal_spi_master_init(NRF_SPI_Type * p_instance, hal_spi_init_t const * p_spi_init) {
// cast to master type
NRF_SPIM_Type * spim_instance = (NRF_SPIM_Type *)p_instance;
hal_gpio_cfg_pin(p_spi_init->clk_pin->port, p_spi_init->clk_pin->pin, HAL_GPIO_MODE_OUTPUT, HAL_GPIO_PULL_DISABLED);
hal_gpio_cfg_pin(p_spi_init->mosi_pin->port, p_spi_init->mosi_pin->pin, HAL_GPIO_MODE_OUTPUT, HAL_GPIO_PULL_DISABLED);
hal_gpio_cfg_pin(p_spi_init->miso_pin->port, p_spi_init->miso_pin->pin, HAL_GPIO_MODE_INPUT, HAL_GPIO_PULL_DISABLED);
spim_instance->PSEL.SCK = p_spi_init->clk_pin->pin;
spim_instance->PSEL.MOSI = p_spi_init->mosi_pin->pin;
spim_instance->PSEL.MISO = p_spi_init->miso_pin->pin;
#if NRF52840_XXAA
spim_instance->PSEL.SCK |= (p_spi_init->clk_pin->port << SPIM_PSEL_SCK_PORT_Pos);
spim_instance->PSEL.MOSI |= (p_spi_init->mosi_pin->port << SPIM_PSEL_MOSI_PORT_Pos);
spim_instance->PSEL.MISO |= (p_spi_init->miso_pin->port << SPIM_PSEL_MISO_PORT_Pos);
#endif
spim_instance->FREQUENCY = hal_spi_frequency_lookup[p_spi_init->freq];
uint32_t mode;
switch (p_spi_init->mode) {
case HAL_SPI_MODE_CPOL0_CPHA0:
mode = (SPIM_CONFIG_CPHA_Leading << SPIM_CONFIG_CPHA_Pos) | (SPIM_CONFIG_CPOL_ActiveHigh << SPIM_CONFIG_CPOL_Pos);
break;
case HAL_SPI_MODE_CPOL0_CPHA1:
mode = (SPIM_CONFIG_CPHA_Trailing << SPIM_CONFIG_CPHA_Pos) | (SPIM_CONFIG_CPOL_ActiveHigh << SPIM_CONFIG_CPOL_Pos);
break;
case HAL_SPI_MODE_CPOL1_CPHA0:
mode = (SPIM_CONFIG_CPHA_Leading << SPIM_CONFIG_CPHA_Pos) | (SPIM_CONFIG_CPOL_ActiveLow << SPIM_CONFIG_CPOL_Pos);
break;
case HAL_SPI_MODE_CPOL1_CPHA1:
mode = (SPIM_CONFIG_CPHA_Trailing << SPIM_CONFIG_CPHA_Pos) | (SPIM_CONFIG_CPOL_ActiveLow << SPIM_CONFIG_CPOL_Pos);
break;
default:
mode = 0;
break;
}
if (p_spi_init->firstbit == HAL_SPI_LSB_FIRST) {
spim_instance->CONFIG = (mode | (SPIM_CONFIG_ORDER_LsbFirst << SPIM_CONFIG_ORDER_Pos));
} else {
spim_instance->CONFIG = (mode | (SPIM_CONFIG_ORDER_MsbFirst << SPIM_CONFIG_ORDER_Pos));
}
spim_instance->EVENTS_END = 0;
spim_instance->ENABLE = (SPIM_ENABLE_ENABLE_Enabled << SPIM_ENABLE_ENABLE_Pos);
}
void hal_spi_master_tx_rx(NRF_SPI_Type * p_instance, uint16_t transfer_size, const uint8_t * tx_data, uint8_t * rx_data) {
// cast to master type
NRF_SPIM_Type * spim_instance = (NRF_SPIM_Type *)p_instance;
if (tx_data != NULL) {
spim_instance->TXD.PTR = (uint32_t)(tx_data);
spim_instance->TXD.MAXCNT = transfer_size;
}
if (rx_data != NULL) {
spim_instance->RXD.PTR = (uint32_t)(rx_data);
spim_instance->RXD.MAXCNT = transfer_size;
}
spim_instance->TASKS_START = 1;
while(spim_instance->EVENTS_END != 1) {
;
}
spim_instance->EVENTS_END = 0;
spim_instance->TASKS_STOP = 1;
}
#endif // HAL_SPIE_MODULE_ENABLED

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/*
* This file is part of the MicroPython project, http://micropython.org/
*
* The MIT License (MIT)
*
* Copyright (c) 2017 Bander F. Ajba
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
#include <stdio.h>
#include <stdint.h>
#include "mphalport.h"
#include "hal_temp.h"
#if BLUETOOTH_SD
#include "py/nlr.h"
#include "ble_drv.h"
#include "nrf_soc.h"
#define BLUETOOTH_STACK_ENABLED() (ble_drv_stack_enabled())
#endif // BLUETOOTH_SD
#ifdef HAL_TEMP_MODULE_ENABLED
void hal_temp_init(void) {
// @note Workaround for PAN_028 rev2.0A anomaly 31 - TEMP: Temperature offset value has to be manually loaded to the TEMP module
*(uint32_t *) 0x4000C504 = 0;
}
int32_t hal_temp_read(void) {
#if BLUETOOTH_SD
if (BLUETOOTH_STACK_ENABLED() == 1) {
int32_t temp;
(void)sd_temp_get(&temp);
return temp / 4; // resolution of 0.25 degree celsius
}
#endif // BLUETOOTH_SD
int32_t volatile temp;
hal_temp_init();
NRF_TEMP->TASKS_START = 1; // Start the temperature measurement.
while (NRF_TEMP->EVENTS_DATARDY == 0) {
// Do nothing.
}
NRF_TEMP->EVENTS_DATARDY = 0;
// @note Workaround for PAN_028 rev2.0A anomaly 29 - TEMP: Stop task clears the TEMP register.
temp = (((NRF_TEMP->TEMP & MASK_SIGN) != 0) ? (NRF_TEMP->TEMP | MASK_SIGN_EXTENSION) : (NRF_TEMP->TEMP) / 4);
// @note Workaround for PAN_028 rev2.0A anomaly 30 - TEMP: Temp module analog front end does not power down when DATARDY event occurs.
NRF_TEMP->TASKS_STOP = 1; // Stop the temperature measurement.
return temp;
}
#endif // HAL_TEMP_MODULE_ENABLED

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/*
* This file is part of the MicroPython project, http://micropython.org/
*
* The MIT License (MIT)
*
* Copyright (c) 2016 Glenn Ruben Bakke
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
#include "mphalport.h"
#include "hal_time.h"
#ifdef HAL_TIME_MODULE_ENABLED
void mp_hal_delay_us(mp_uint_t us)
{
register uint32_t delay __ASM ("r0") = us;
__ASM volatile (
#ifdef NRF51
".syntax unified\n"
#endif
"1:\n"
" SUBS %0, %0, #1\n"
" NOP\n"
" NOP\n"
" NOP\n"
" NOP\n"
" NOP\n"
" NOP\n"
" NOP\n"
" NOP\n"
" NOP\n"
" NOP\n"
" NOP\n"
" NOP\n"
#ifdef NRF52
" NOP\n"
" NOP\n"
" NOP\n"
" NOP\n"
" NOP\n"
" NOP\n"
" NOP\n"
" NOP\n"
" NOP\n"
" NOP\n"
" NOP\n"
" NOP\n"
" NOP\n"
" NOP\n"
" NOP\n"
" NOP\n"
" NOP\n"
" NOP\n"
" NOP\n"
" NOP\n"
" NOP\n"
" NOP\n"
" NOP\n"
" NOP\n"
" NOP\n"
" NOP\n"
" NOP\n"
" NOP\n"
" NOP\n"
" NOP\n"
" NOP\n"
" NOP\n"
" NOP\n"
" NOP\n"
" NOP\n"
" NOP\n"
" NOP\n"
" NOP\n"
" NOP\n"
" NOP\n"
" NOP\n"
" NOP\n"
" NOP\n"
" NOP\n"
" NOP\n"
" NOP\n"
#endif
" BNE 1b\n"
#ifdef NRF51
".syntax divided\n"
#endif
: "+r" (delay));
}
void mp_hal_delay_ms(mp_uint_t ms)
{
for (mp_uint_t i = 0; i < ms; i++)
{
mp_hal_delay_us(999);
}
}
#endif // HAL_TIME_MODULE_ENABLED

34
ports/nrf/hal/hal_time.h
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@ -1,34 +0,0 @@
/*
* This file is part of the MicroPython project, http://micropython.org/
*
* The MIT License (MIT)
*
* Copyright (c) 2016 Glenn Ruben Bakke
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
#ifndef HAL_TIME_H__
#define HAL_TIME_H__
void mp_hal_delay_ms(mp_uint_t ms);
void mp_hal_delay_us(mp_uint_t us);
#endif // HAL_TIME_H__

103
ports/nrf/hal/hal_timer.c
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@ -1,103 +0,0 @@
/*
* This file is part of the MicroPython project, http://micropython.org/
*
* The MIT License (MIT)
*
* Copyright (c) 2016 Glenn Ruben Bakke
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
#include "mphalport.h"
#include "hal_timer.h"
#include "hal_irq.h"
#ifdef HAL_TIMER_MODULE_ENABLED
static hal_timer_app_callback m_callback;
void hal_timer_callback_set(hal_timer_app_callback callback) {
m_callback = callback;
}
void hal_timer_init(hal_timer_conf_t const * p_timer_conf) {
NRF_TIMER_Type * p_timer = TIMER_BASE(p_timer_conf->id);
p_timer->CC[0] = 1000 * p_timer_conf->period;
p_timer->MODE = TIMER_MODE_MODE_Timer;
p_timer->BITMODE = TIMER_BITMODE_BITMODE_24Bit << TIMER_BITMODE_BITMODE_Pos;
p_timer->PRESCALER = 4; // 1 us
p_timer->INTENSET = TIMER_INTENSET_COMPARE0_Msk;
p_timer->SHORTS = (TIMER_SHORTS_COMPARE0_CLEAR_Enabled << TIMER_SHORTS_COMPARE0_CLEAR_Pos);
p_timer->TASKS_CLEAR = 1;
hal_irq_priority(TIMER_IRQ_NUM(p_timer_conf->id), p_timer_conf->irq_priority);
}
void hal_timer_start(uint8_t id) {
NRF_TIMER_Type * p_timer = TIMER_BASE(id);
p_timer->TASKS_CLEAR = 1;
hal_irq_enable(TIMER_IRQ_NUM(id));
p_timer->TASKS_START = 1;
}
void hal_timer_stop(uint8_t id) {
NRF_TIMER_Type * p_timer = TIMER_BASE(id);
hal_irq_disable(TIMER_IRQ_NUM(id));
p_timer->TASKS_STOP = 1;
}
static void common_irq_handler(uint8_t id) {
NRF_TIMER_Type * p_timer = TIMER_BASE(id);
if (p_timer->EVENTS_COMPARE[0]) {
p_timer->EVENTS_COMPARE[0] = 0;
m_callback(id);
}
}
void TIMER0_IRQHandler(void) {
common_irq_handler(0);
}
#if (MICROPY_PY_MACHINE_SOFT_PWM != 1)
void TIMER1_IRQHandler(void) {
common_irq_handler(1);
}
#endif
void TIMER2_IRQHandler(void) {
common_irq_handler(2);
}
#if NRF52
void TIMER3_IRQHandler(void) {
common_irq_handler(3);
}
void TIMER4_IRQHandler(void) {
common_irq_handler(4);
}
#endif
#endif // HAL_TIMER_MODULE_ENABLED

76
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@ -1,76 +0,0 @@
/*
* This file is part of the MicroPython project, http://micropython.org/
*
* The MIT License (MIT)
*
* Copyright (c) 2016 Glenn Ruben Bakke
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
#ifndef HAL_TIMER_H__
#define HAL_TIMER_H__
#include "nrf.h"
#if NRF51
#define TIMER_BASE_POINTERS (const uint32_t[]){NRF_TIMER0_BASE, \
NRF_TIMER1_BASE, \
NRF_TIMER2_BASE}
#define TIMER_IRQ_VALUES (const uint32_t[]){TIMER0_IRQn, \
TIMER1_IRQn, \
TIMER2_IRQn}
#endif
#if NRF52
#define TIMER_BASE_POINTERS (const uint32_t[]){NRF_TIMER0_BASE, \
NRF_TIMER1_BASE, \
NRF_TIMER1_BASE, \
NRF_TIMER1_BASE, \
NRF_TIMER2_BASE}
#define TIMER_IRQ_VALUES (const uint32_t[]){TIMER0_IRQn, \
TIMER1_IRQn, \
TIMER2_IRQn, \
TIMER3_IRQn, \
TIMER4_IRQn}
#endif
#define TIMER_BASE(x) ((NRF_TIMER_Type *)TIMER_BASE_POINTERS[x])
#define TIMER_IRQ_NUM(x) (TIMER_IRQ_VALUES[x])
typedef void (*hal_timer_app_callback)(uint8_t id);
/**
* @brief Timer Configuration Structure definition
*/
typedef struct {
uint8_t id;
uint32_t period;
uint8_t irq_priority;
} hal_timer_conf_t;
void hal_timer_callback_set(hal_timer_app_callback callback);
void hal_timer_init(hal_timer_conf_t const * p_timer_config);
void hal_timer_start(uint8_t id);
void hal_timer_stop(uint8_t id);
#endif // HAL_TIMER_H__

133
ports/nrf/hal/hal_twi.c
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@ -1,133 +0,0 @@
/*
* This file is part of the MicroPython project, http://micropython.org/
*
* The MIT License (MIT)
*
* Copyright (c) 2017 Glenn Ruben Bakke
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
#include "mphalport.h"
#include "hal_twi.h"
#ifdef HAL_TWI_MODULE_ENABLED
static const uint32_t hal_twi_frequency_lookup[] = {
TWI_FREQUENCY_FREQUENCY_K100, // 100 kbps
TWI_FREQUENCY_FREQUENCY_K250, // 250 kbps
TWI_FREQUENCY_FREQUENCY_K400, // 400 kbps
};
void hal_twi_master_init(NRF_TWI_Type * p_instance, hal_twi_init_t const * p_twi_init) {
#if NRF52840_XXAA
p_instance->PSEL.SCL = p_twi_init->scl_pin->pin;
p_instance->PSEL.SDA = p_twi_init->sda_pin->pin;
p_instance->PSEL.SCL |= (p_twi_init->scl_pin->port << TWI_PSEL_SCL_PORT_Pos);
p_instance->PSEL.SDA |= (p_twi_init->sda_pin->port << TWI_PSEL_SDA_PORT_Pos);
#else
p_instance->PSELSCL = p_twi_init->scl_pin->pin;
p_instance->PSELSDA = p_twi_init->sda_pin->pin;
#endif
p_instance->FREQUENCY = hal_twi_frequency_lookup[p_twi_init->freq];
p_instance->ENABLE = (TWI_ENABLE_ENABLE_Enabled << TWI_ENABLE_ENABLE_Pos);
}
#include <stdio.h>
void hal_twi_master_tx(NRF_TWI_Type * p_instance,
uint8_t addr,
uint16_t transfer_size,
const uint8_t * tx_data,
bool stop) {
uint16_t number_of_txd_bytes = 0;
p_instance->ADDRESS = addr;
p_instance->EVENTS_TXDSENT = 0;
p_instance->TXD = tx_data[number_of_txd_bytes];
p_instance->TASKS_STARTTX = 1;
while (number_of_txd_bytes < transfer_size) {
// wait for the transaction complete
while (p_instance->EVENTS_TXDSENT == 0) {
;
}
number_of_txd_bytes++;
// TODO: This could go one byte out of bound.
p_instance->TXD = tx_data[number_of_txd_bytes];
p_instance->EVENTS_TXDSENT = 0;
}
if (stop) {
p_instance->EVENTS_STOPPED = 0;
p_instance->TASKS_STOP = 1;
while (p_instance->EVENTS_STOPPED == 0) {
;
}
}
}
void hal_twi_master_rx(NRF_TWI_Type * p_instance,
uint8_t addr,
uint16_t transfer_size,
uint8_t * rx_data,
bool stop) {
uint16_t number_of_rxd_bytes = 0;
p_instance->ADDRESS = addr;
p_instance->EVENTS_RXDREADY = 0;
p_instance->TASKS_STARTRX = 1;
while (number_of_rxd_bytes < transfer_size) {
// wait for the transaction complete
while (p_instance->EVENTS_RXDREADY == 0) {
;
}
rx_data[number_of_rxd_bytes] = p_instance->RXD;
p_instance->EVENTS_RXDREADY = 0;
number_of_rxd_bytes++;
}
if (stop) {
p_instance->EVENTS_STOPPED = 0;
p_instance->TASKS_STOP = 1;
while (p_instance->EVENTS_STOPPED == 0) {
;
}
}
}
void hal_twi_slave_init(NRF_TWI_Type * p_instance, hal_twi_init_t const * p_twi_init) {
}
#endif // HAL_TWI_MODULE_ENABLED

118
ports/nrf/hal/hal_twi.h
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@ -1,118 +0,0 @@
/*
* This file is part of the MicroPython project, http://micropython.org/
*
* The MIT License (MIT)
*
* Copyright (c) 2017 Glenn Ruben Bakke
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
#ifndef HAL_TWI_H__
#define HAL_TWI_H__
#include <stdbool.h>
#include "nrf.h"
#define TWI_BASE_POINTERS (const uint32_t[]){NRF_TWI0_BASE, NRF_TWI1_BASE}
#define TWI_BASE(x) ((NRF_TWI_Type *)TWI_BASE_POINTERS[x])
#if NRF51
#define TWI_IRQ_VALUES (const uint32_t[]){SPI0_TWI0_IRQn, SPI1_TWI1_IRQn}
#elif NRF52
#define TWI_IRQ_VALUES (const uint32_t[]){SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQn, \
SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQn}
#endif
#if NRF52
/**
* @brief TWIM Configuration Structure definition
*/
typedef struct {
} hal_twim_init_t;
/**
* @brief TWIS Configuration Structure definition
*/
typedef struct {
} hal_twis_init_t;
#endif
/**
* @brief TWI clock frequency type definition
*/
typedef enum {
HAL_TWI_FREQ_100_Kbps = 0,
HAL_TWI_FREQ_250_Kbps,
HAL_TWI_FREQ_400_Kbps
} hal_twi_clk_freq_t;
/**
* @brief TWI role type definition
*/
typedef enum {
HAL_TWI_MASTER,
HAL_TWI_SLAVE
} hal_twi_role_t;
/**
* @brief TWI Configuration Structure definition
*/
typedef struct {
uint8_t id; /* TWI instance id */
const pin_obj_t * scl_pin; /* TWI SCL pin */
const pin_obj_t * sda_pin; /* TWI SDA pin */
hal_twi_role_t role; /* TWI master/slave */
hal_twi_clk_freq_t freq; /* TWI frequency */
} hal_twi_init_t;
/**
* @brief TWI handle Structure definition
*/
typedef struct __TWI_HandleTypeDef
{
NRF_TWI_Type *instance; /* TWI register base address */
hal_twi_init_t init; /* TWI initialization parameters */
} TWI_HandleTypeDef;
void hal_twi_master_init(NRF_TWI_Type * p_instance, hal_twi_init_t const * p_twi_init);
void hal_twi_master_tx(NRF_TWI_Type * p_instance,
uint8_t addr,
uint16_t transfer_size,
const uint8_t * tx_data,
bool stop);
void hal_twi_master_rx(NRF_TWI_Type * p_instance,
uint8_t addr,
uint16_t transfer_size,
uint8_t * rx_data,
bool stop);
void hal_twi_slave_init(NRF_TWI_Type * p_instance, hal_twi_init_t const * p_twi_init);
#endif // HAL_TWI_H__

115
ports/nrf/hal/hal_twie.c
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@ -1,115 +0,0 @@
/*
* This file is part of the MicroPython project, http://micropython.org/
*
* The MIT License (MIT)
*
* Copyright (c) 2017 Glenn Ruben Bakke
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
#include "mphalport.h"
#include "hal_twi.h"
#ifdef HAL_TWIE_MODULE_ENABLED
// EasyDMA variants
#define TWI_MASTER_BASE(x) ((NRF_TWIM_Type *)TWI_BASE_POINTERS[x])
#define TWI_SLAVE_BASE(x) ((NRF_TWIS_Type *)TWI_BASE_POINTERS[x])
static const uint32_t hal_twi_frequency_lookup[] = {
TWIM_FREQUENCY_FREQUENCY_K100, // 100 kbps
TWIM_FREQUENCY_FREQUENCY_K250, // 250 kbps
TWIM_FREQUENCY_FREQUENCY_K400, // 400 kbps
};
void hal_twi_master_init(NRF_TWI_Type * p_instance, hal_twi_init_t const * p_twi_init) {
// cast to master type
NRF_TWIM_Type * twim_instance = (NRF_TWIM_Type *)p_instance;
twim_instance->PSEL.SCL = p_twi_init->scl_pin->pin;
twim_instance->PSEL.SDA = p_twi_init->sda_pin->pin;
#if NRF52840_XXAA
twim_instance->PSEL.SCL |= (p_twi_init->scl_pin->port << TWIM_PSEL_SCL_PORT_Pos);
twim_instance->PSEL.SDA |= (p_twi_init->sda_pin->port << TWIM_PSEL_SDA_PORT_Pos);
#endif
twim_instance->FREQUENCY = hal_twi_frequency_lookup[p_twi_init->freq];
twim_instance->ENABLE = (TWIM_ENABLE_ENABLE_Enabled << TWIM_ENABLE_ENABLE_Pos);
}
#include <stdio.h>
void hal_twi_master_tx(NRF_TWI_Type * p_instance,
uint8_t addr,
uint16_t transfer_size,
const uint8_t * tx_data,
bool stop) {
// cast to master type
NRF_TWIM_Type * twim_instance = (NRF_TWIM_Type *)p_instance;
twim_instance->ADDRESS = addr;
printf("Hal I2C transfer size: %u, addr: %x, stop: %u\n", transfer_size, addr, stop);
twim_instance->TXD.MAXCNT = transfer_size;
twim_instance->TXD.PTR = (uint32_t)tx_data;
if (stop) {
twim_instance->SHORTS = TWIM_SHORTS_LASTTX_STOP_Msk;
} else {
twim_instance->SHORTS = TWIM_SHORTS_LASTTX_SUSPEND_Msk;
}
if (twim_instance->EVENTS_SUSPENDED == 1) {
printf("Resuming\n");
twim_instance->EVENTS_SUSPENDED = 0;
twim_instance->EVENTS_STOPPED = 0;
twim_instance->TASKS_RESUME = 1; // in case of resume
} else {
printf("Starting\n");
twim_instance->EVENTS_SUSPENDED = 0;
twim_instance->EVENTS_STOPPED = 0;
twim_instance->TASKS_STARTTX = 1;
}
printf("Going into loop\n");
while (twim_instance->EVENTS_STOPPED == 0 && twim_instance->EVENTS_SUSPENDED == 0) {
;
}
}
void hal_twi_master_rx(NRF_TWI_Type * p_instance,
uint8_t addr,
uint16_t transfer_size,
const uint8_t * rx_data) {
// cast to master type
NRF_TWIM_Type * twim_instance = (NRF_TWIM_Type *)p_instance;
twim_instance->ADDRESS = addr;
}
void hal_twi_slave_init(NRF_TWI_Type * p_instance, hal_twi_init_t const * p_twi_init) {
// cast to slave type
NRF_TWIS_Type * twis_instance = (NRF_TWIS_Type *)p_instance;
(void)twis_instance;
}
#endif // HAL_TWIE_MODULE_ENABLED

146
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@ -1,146 +0,0 @@
/*
* This file is part of the MicroPython project, http://micropython.org/
*
* The MIT License (MIT)
*
* Copyright (c) 2016 Glenn Ruben Bakke
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
#include <stdint.h>
#include <stdio.h>
#include "nrf.h"
#include "mphalport.h"
#include "hal_uart.h"
#ifdef HAL_UART_MODULE_ENABLED
uint32_t hal_uart_baudrate_lookup[] = {
UART_BAUDRATE_BAUDRATE_Baud1200, ///< 1200 baud.
UART_BAUDRATE_BAUDRATE_Baud2400, ///< 2400 baud.
UART_BAUDRATE_BAUDRATE_Baud4800, ///< 4800 baud.
UART_BAUDRATE_BAUDRATE_Baud9600, ///< 9600 baud.
UART_BAUDRATE_BAUDRATE_Baud14400, ///< 14400 baud.
UART_BAUDRATE_BAUDRATE_Baud19200, ///< 19200 baud.
UART_BAUDRATE_BAUDRATE_Baud28800, ///< 28800 baud.
UART_BAUDRATE_BAUDRATE_Baud38400, ///< 38400 baud.
UART_BAUDRATE_BAUDRATE_Baud57600, ///< 57600 baud.
UART_BAUDRATE_BAUDRATE_Baud76800, ///< 76800 baud.
UART_BAUDRATE_BAUDRATE_Baud115200, ///< 115200 baud.
UART_BAUDRATE_BAUDRATE_Baud230400, ///< 230400 baud.
UART_BAUDRATE_BAUDRATE_Baud250000, ///< 250000 baud.
UART_BAUDRATE_BAUDRATE_Baud460800, ///< 460800 baud.
UART_BAUDRATE_BAUDRATE_Baud921600, ///< 921600 baud.
UART_BAUDRATE_BAUDRATE_Baud1M, ///< 1000000 baud.
};
hal_uart_error_t hal_uart_char_write(NRF_UART_Type * p_instance, uint8_t ch) {
p_instance->ERRORSRC = 0;
p_instance->TXD = (uint8_t)ch;
while (p_instance->EVENTS_TXDRDY != 1) {
// Blocking wait.
}
// Clear the TX flag.
p_instance->EVENTS_TXDRDY = 0;
return p_instance->ERRORSRC;
}
hal_uart_error_t hal_uart_char_read(NRF_UART_Type * p_instance, uint8_t * ch) {
p_instance->ERRORSRC = 0;
while (p_instance->EVENTS_RXDRDY != 1) {
// Wait for RXD data.
}
p_instance->EVENTS_RXDRDY = 0;
*ch = p_instance->RXD;
return p_instance->ERRORSRC;
}
hal_uart_error_t hal_uart_buffer_write(NRF_UART_Type * p_instance, uint8_t * p_buffer, uint32_t num_of_bytes, uart_complete_cb cb) {
int i = 0;
hal_uart_error_t err = 0;
uint8_t ch = p_buffer[i++];
while (i < num_of_bytes) {
err = hal_uart_char_write(p_instance, ch);
if (err) {
return err;
}
ch = p_buffer[i++];
}
cb();
return err;
}
hal_uart_error_t hal_uart_buffer_read(NRF_UART_Type * p_instance, uint8_t * p_buffer, uint32_t num_of_bytes, uart_complete_cb cb) {
int i = 0;
hal_uart_error_t err = 0;
while (i < num_of_bytes) {
hal_uart_error_t err = hal_uart_char_read(p_instance, &p_buffer[i]);
if (err) {
return err;
}
i++;
}
cb();
return err;
}
void hal_uart_init(NRF_UART_Type * p_instance, hal_uart_init_t const * p_uart_init) {
hal_gpio_cfg_pin(p_uart_init->tx_pin->port, p_uart_init->tx_pin->pin, HAL_GPIO_MODE_OUTPUT, HAL_GPIO_PULL_DISABLED);
hal_gpio_cfg_pin(p_uart_init->tx_pin->port, p_uart_init->rx_pin->pin, HAL_GPIO_MODE_INPUT, HAL_GPIO_PULL_DISABLED);
hal_gpio_pin_clear(p_uart_init->tx_pin->port, p_uart_init->tx_pin->pin);
p_instance->PSELTXD = p_uart_init->tx_pin->pin;
p_instance->PSELRXD = p_uart_init->rx_pin->pin;
#if NRF52840_XXAA
p_instance->PSELTXD |= (p_uart_init->tx_pin->port << UARTE_PSEL_TXD_PORT_Pos);
p_instance->PSELRXD |= (p_uart_init->rx_pin->port << UARTE_PSEL_RXD_PORT_Pos);
#endif
if (p_uart_init->flow_control) {
hal_gpio_cfg_pin(p_uart_init->rts_pin->port, p_uart_init->rts_pin->pin, HAL_GPIO_MODE_OUTPUT, HAL_GPIO_PULL_DISABLED);
hal_gpio_cfg_pin(p_uart_init->cts_pin->port, p_uart_init->cts_pin->pin, HAL_GPIO_MODE_INPUT, HAL_GPIO_PULL_DISABLED);
p_instance->PSELCTS = p_uart_init->cts_pin->pin;
p_instance->PSELRTS = p_uart_init->rts_pin->pin;
#if NRF52840_XXAA
p_instance->PSELCTS |= (p_uart_init->cts_pin->port << UARTE_PSEL_CTS_PORT_Pos);
p_instance->PSELRTS |= (p_uart_init->rts_pin->port << UARTE_PSEL_RTS_PORT_Pos);
#endif
p_instance->CONFIG = (UART_CONFIG_HWFC_Enabled << UART_CONFIG_HWFC_Pos);
}
p_instance->BAUDRATE = (hal_uart_baudrate_lookup[p_uart_init->baud_rate]);
p_instance->ENABLE = (UART_ENABLE_ENABLE_Enabled << UART_ENABLE_ENABLE_Pos);
p_instance->EVENTS_TXDRDY = 0;
p_instance->EVENTS_RXDRDY = 0;
p_instance->TASKS_STARTTX = 1;
p_instance->TASKS_STARTRX = 1;
}
#endif // HAL_UART_MODULE_ENABLED

125
ports/nrf/hal/hal_uart.h
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@ -1,125 +0,0 @@
/*
* This file is part of the MicroPython project, http://micropython.org/
*
* The MIT License (MIT)
*
* Copyright (c) 2016 Glenn Ruben Bakke
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
#ifndef HAL_UART_H__
#define HAL_UART_H__
#include <stdint.h>
#include <stdbool.h>
#include "nrf.h"
#if NRF51
#define UART_HWCONTROL_NONE ((uint32_t)UART_CONFIG_HWFC_Disabled << UART_CONFIG_HWFC_Pos)
#define UART_HWCONTROL_RTS_CTS ((uint32_t)(UART_CONFIG_HWFC_Enabled << UART_CONFIG_HWFC_Pos)
#define IS_UART_HARDWARE_FLOW_CONTROL(CONTROL)\
(((CONTROL) == UART_HWCONTROL_NONE) || \
((CONTROL) == UART_HWCONTROL_RTS_CTS))
#define UART_BASE_POINTERS (const uint32_t[]){NRF_UART0_BASE}
#define UART_IRQ_VALUES (const uint32_t[]){UART0_IRQn}
#elif NRF52
#define UART_HWCONTROL_NONE ((uint32_t)UARTE_CONFIG_HWFC_Disabled << UARTE_CONFIG_HWFC_Pos)
#define UART_HWCONTROL_RTS_CTS ((uint32_t)(UARTE_CONFIG_HWFC_Enabled << UARTE_CONFIG_HWFC_Pos)
#define IS_UART_HARDWARE_FLOW_CONTROL(CONTROL)\
(((CONTROL) == UART_HWCONTROL_NONE) || \
((CONTROL) == UART_HWCONTROL_RTS_CTS))
#ifdef HAL_UART_MODULE_ENABLED
#define UART_BASE_POINTERS (const uint32_t[]){NRF_UART0_BASE}
#define UART_IRQ_VALUES (const uint32_t[]){UARTE0_UART0_IRQn}
#else // HAL_UARTE_MODULE_ENABLED
#ifdef NRF52832_XXAA
#define UART_BASE_POINTERS (const uint32_t[]){NRF_UARTE0_BASE}
#define UART_IRQ_VALUES (const uint32_t[]){UARTE0_UART0_IRQn}
#elif NRF52840_XXAA
#define UART_BASE_POINTERS (const uint32_t[]){NRF_UARTE0_BASE, \
NRF_UARTE1_BASE}
#define UART_IRQ_VALUES (const uint32_t[]){UARTE0_UART0_IRQn, \
UARTE1_IRQn}
#endif // HAL_UARTE_MODULE_ENABLED
#endif
#else
#error "Device not supported."
#endif
#define UART_BASE(x) ((NRF_UART_Type *)UART_BASE_POINTERS[x])
#define UART_IRQ_NUM(x) (UART_IRQ_VALUES[x])
typedef enum
{
HAL_UART_ERROR_NONE = 0x00, /*!< No error */
HAL_UART_ERROR_ORE = 0x01, /*!< Overrun error. A start bit is received while the previous data still lies in RXD. (Previous data is lost.) */
HAL_UART_ERROR_PE = 0x02, /*!< Parity error. A character with bad parity is received, if HW parity check is enabled. */
HAL_UART_ERROR_FE = 0x04, /*!< Frame error. A valid stop bit is not detected on the serial data input after all bits in a character have been received. */
HAL_UART_ERROR_BE = 0x08, /*!< Break error. The serial data input is '0' for longer than the length of a data frame. (The data frame length is 10 bits without parity bit, and 11 bits with parity bit.). */
} hal_uart_error_t;
typedef enum {
HAL_UART_BAUD_1K2 = 0, /**< 1200 baud */
HAL_UART_BAUD_2K4, /**< 2400 baud */
HAL_UART_BAUD_4K8, /**< 4800 baud */
HAL_UART_BAUD_9K6, /**< 9600 baud */
HAL_UART_BAUD_14K4, /**< 14.4 kbaud */
HAL_UART_BAUD_19K2, /**< 19.2 kbaud */
HAL_UART_BAUD_28K8, /**< 28.8 kbaud */
HAL_UART_BAUD_38K4, /**< 38.4 kbaud */
HAL_UART_BAUD_57K6, /**< 57.6 kbaud */
HAL_UART_BAUD_76K8, /**< 76.8 kbaud */
HAL_UART_BAUD_115K2, /**< 115.2 kbaud */
HAL_UART_BAUD_230K4, /**< 230.4 kbaud */
HAL_UART_BAUD_250K0, /**< 250.0 kbaud */
HAL_UART_BAUD_500K0, /**< 500.0 kbaud */
HAL_UART_BAUD_1M0 /**< 1 mbaud */
} hal_uart_baudrate_t;
typedef struct {
uint8_t id; /* UART instance id */
const pin_obj_t * rx_pin; /* RX pin. */
const pin_obj_t * tx_pin; /* TX pin. */
const pin_obj_t * rts_pin; /* RTS pin, only used if flow control is enabled. */
const pin_obj_t * cts_pin; /* CTS pin, only used if flow control is enabled. */
bool flow_control; /* Flow control setting, if flow control is used, the system will use low power UART mode, based on CTS signal. */
bool use_parity; /* Even parity if TRUE, no parity if FALSE. */
uint32_t baud_rate; /* Baud rate configuration. */
uint32_t irq_priority; /* UARTE IRQ priority. */
uint32_t irq_num;
} hal_uart_init_t;
typedef struct
{
NRF_UART_Type * p_instance; /* UART registers base address */
hal_uart_init_t init; /* UART communication parameters */
} UART_HandleTypeDef;
typedef void (*uart_complete_cb)(void);
void hal_uart_init(NRF_UART_Type * p_instance, hal_uart_init_t const * p_uart_init);
hal_uart_error_t hal_uart_char_write(NRF_UART_Type * p_instance, uint8_t ch);
hal_uart_error_t hal_uart_char_read(NRF_UART_Type * p_instance, uint8_t * ch);
#endif // HAL_UART_H__

180
ports/nrf/hal/hal_uarte.c
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@ -1,180 +0,0 @@
/*
* This file is part of the MicroPython project, http://micropython.org/
*
* The MIT License (MIT)
*
* Copyright (c) 2016 Glenn Ruben Bakke
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
#include <stdint.h>
#include <stdio.h>
#include "mphalport.h"
#include "hal_uart.h"
#include "hal_irq.h"
#ifdef HAL_UARTE_MODULE_ENABLED
#include "nrf.h"
#ifndef NRF52
#error "Device not supported."
#endif
#define UART_BASE(x) ((NRF_UART_Type *)UART_BASE_POINTERS[x])
#define UART_IRQ_NUM(x) (UART_IRQ_VALUES[x])
#define TX_BUF_SIZE 1
#define RX_BUF_SIZE 1
static const uint32_t hal_uart_baudrate_lookup[] = {
UARTE_BAUDRATE_BAUDRATE_Baud1200, ///< 1200 baud.
UARTE_BAUDRATE_BAUDRATE_Baud2400, ///< 2400 baud.
UARTE_BAUDRATE_BAUDRATE_Baud4800, ///< 4800 baud.
UARTE_BAUDRATE_BAUDRATE_Baud9600, ///< 9600 baud.
UARTE_BAUDRATE_BAUDRATE_Baud14400, ///< 14400 baud.
UARTE_BAUDRATE_BAUDRATE_Baud19200, ///< 19200 baud.
UARTE_BAUDRATE_BAUDRATE_Baud28800, ///< 28800 baud.
UARTE_BAUDRATE_BAUDRATE_Baud38400, ///< 38400 baud.
UARTE_BAUDRATE_BAUDRATE_Baud57600, ///< 57600 baud.
UARTE_BAUDRATE_BAUDRATE_Baud76800, ///< 76800 baud.
UARTE_BAUDRATE_BAUDRATE_Baud115200, ///< 115200 baud.
UARTE_BAUDRATE_BAUDRATE_Baud230400, ///< 230400 baud.
UARTE_BAUDRATE_BAUDRATE_Baud250000, ///< 250000 baud.
UARTE_BAUDRATE_BAUDRATE_Baud460800, ///< 460800 baud.
UARTE_BAUDRATE_BAUDRATE_Baud921600, ///< 921600 baud.
UARTE_BAUDRATE_BAUDRATE_Baud1M, ///< 1000000 baud.
};
void nrf_sendchar(NRF_UART_Type * p_instance, int ch) {
hal_uart_char_write(p_instance, ch);
}
void hal_uart_init(NRF_UART_Type * p_instance, hal_uart_init_t const * p_uart_init) {
NRF_UARTE_Type * uarte_instance = (NRF_UARTE_Type *)p_instance;
hal_gpio_cfg_pin(p_uart_init->tx_pin->port, p_uart_init->tx_pin->pin, HAL_GPIO_MODE_OUTPUT, HAL_GPIO_PULL_DISABLED);
hal_gpio_pin_set(p_uart_init->tx_pin->port, p_uart_init->tx_pin->pin);
hal_gpio_cfg_pin(p_uart_init->tx_pin->port, p_uart_init->rx_pin->pin, HAL_GPIO_MODE_INPUT, HAL_GPIO_PULL_DISABLED);
uarte_instance->BAUDRATE = (hal_uart_baudrate_lookup[p_uart_init->baud_rate]);
uint32_t hwfc = (p_uart_init->flow_control)
? (UARTE_CONFIG_HWFC_Enabled << UARTE_CONFIG_HWFC_Pos)
: (UARTE_CONFIG_HWFC_Disabled << UARTE_CONFIG_HWFC_Pos);
uint32_t parity = (p_uart_init->use_parity)
? (UARTE_CONFIG_PARITY_Included << UARTE_CONFIG_PARITY_Pos)
: (UARTE_CONFIG_PARITY_Excluded << UARTE_CONFIG_PARITY_Pos);
uarte_instance->CONFIG = (uint32_t)hwfc | (uint32_t)parity;
uarte_instance->PSEL.RXD = p_uart_init->rx_pin->pin;
uarte_instance->PSEL.TXD = p_uart_init->tx_pin->pin;
#if NRF52840_XXAA
uarte_instance->PSEL.RXD |= (p_uart_init->rx_pin->port << UARTE_PSEL_RXD_PORT_Pos);
uarte_instance->PSEL.TXD |= (p_uart_init->tx_pin->port << UARTE_PSEL_TXD_PORT_Pos);
#endif
if (hwfc) {
hal_gpio_cfg_pin(p_uart_init->cts_pin->port, p_uart_init->cts_pin->pin, HAL_GPIO_MODE_INPUT, HAL_GPIO_PULL_DISABLED);
hal_gpio_cfg_pin(p_uart_init->rts_pin->port, p_uart_init->rts_pin->pin, HAL_GPIO_MODE_OUTPUT, HAL_GPIO_PULL_DISABLED);
hal_gpio_pin_set(p_uart_init->rts_pin->port, p_uart_init->rts_pin->pin);
uarte_instance->PSEL.RTS = p_uart_init->rts_pin->pin;
uarte_instance->PSEL.CTS = p_uart_init->cts_pin->pin;
#if NRF52840_XXAA
uarte_instance->PSEL.RTS |= (p_uart_init->rx_pin->port << UARTE_PSEL_RTS_PORT_Pos);
uarte_instance->PSEL.CTS |= (p_uart_init->rx_pin->port << UARTE_PSEL_CTS_PORT_Pos);
#endif
}
hal_irq_priority(p_uart_init->irq_num, p_uart_init->irq_priority);
hal_irq_enable(p_uart_init->irq_num);
uarte_instance->INTENSET = (UARTE_INTENSET_ENDRX_Set << UARTE_INTENSET_ENDRX_Pos);
uarte_instance->INTENSET = (UARTE_INTENSET_ENDTX_Set << UARTE_INTENSET_ENDTX_Pos);
uarte_instance->ENABLE = (UARTE_ENABLE_ENABLE_Enabled << UARTE_ENABLE_ENABLE_Pos);
uarte_instance->EVENTS_ENDTX = 0;
uarte_instance->EVENTS_ENDRX = 0;
}
hal_uart_error_t hal_uart_char_write(NRF_UART_Type * p_instance, uint8_t ch) {
NRF_UARTE_Type * uarte_instance = (NRF_UARTE_Type *)p_instance;
uarte_instance->ERRORSRC = 0;
static volatile uint8_t m_tx_buf[TX_BUF_SIZE];
(void)m_tx_buf;
uarte_instance->INTENCLR = (UARTE_INTENSET_ENDTX_Set << UARTE_INTENSET_ENDTX_Pos);
m_tx_buf[0] = ch;
uarte_instance->TXD.PTR = (uint32_t)((uint8_t *)m_tx_buf);
uarte_instance->TXD.MAXCNT = (uint32_t)sizeof(m_tx_buf);
uarte_instance->TASKS_STARTTX = 1;
while((0 == uarte_instance->EVENTS_ENDTX));
uarte_instance->EVENTS_ENDTX = 0;
uarte_instance->TASKS_STOPTX = 1;
uarte_instance->INTENSET = (UARTE_INTENSET_ENDTX_Set << UARTE_INTENSET_ENDTX_Pos);
return uarte_instance->ERRORSRC;
}
hal_uart_error_t hal_uart_char_read(NRF_UART_Type * p_instance, uint8_t * ch) {
NRF_UARTE_Type * uarte_instance = (NRF_UARTE_Type *)p_instance;
uarte_instance->ERRORSRC = 0;
static volatile uint8_t m_rx_buf[RX_BUF_SIZE];
uarte_instance->INTENCLR = (UARTE_INTENSET_ENDRX_Set << UARTE_INTENSET_ENDRX_Pos);
uarte_instance->RXD.PTR = (uint32_t)((uint8_t *)m_rx_buf);
uarte_instance->RXD.MAXCNT = (uint32_t)sizeof(m_rx_buf);
uarte_instance->TASKS_STARTRX = 1;
while ((0 == uarte_instance->EVENTS_ENDRX));
uarte_instance->EVENTS_ENDRX = 0;
uarte_instance->TASKS_STOPRX = 1;
uarte_instance->INTENSET = (UARTE_INTENSET_ENDRX_Set << UARTE_INTENSET_ENDRX_Pos);
*ch = (uint8_t)m_rx_buf[0];
return uarte_instance->ERRORSRC;
}
#endif // HAL_UARTE_MODULE_ENABLED

30
ports/nrf/hal/nrf51_hal.h
View File

@ -1,30 +0,0 @@
/*
* This file is part of the MicroPython project, http://micropython.org/
*
* The MIT License (MIT)
*
* Copyright (c) 2016 Glenn Ruben Bakke
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
#include <nrf.h>
// include config from board
#include "nrf51_hal_conf.h"

11
ports/nrf/main.c
View File

@ -50,7 +50,8 @@
#include "pin.h"
#include "spi.h"
#include "i2c.h"
#include "rtc.h"
#include "adc.h"
#include "rtcounter.h"
#if MICROPY_PY_MACHINE_HW_PWM
#include "pwm.h"
#endif
@ -122,11 +123,15 @@ soft_reset:
i2c_init0();
#endif
#if MICROPY_PY_MACHINE_ADC
adc_init0();
#endif
#if MICROPY_PY_MACHINE_HW_PWM
pwm_init0();
#endif
#if MICROPY_PY_MACHINE_RTC
#if MICROPY_PY_MACHINE_RTCOUNTER
rtc_init0();
#endif
@ -294,7 +299,7 @@ MP_DEFINE_CONST_FUN_OBJ_KW(mp_builtin_open_obj, 1, mp_builtin_open);
void HardFault_Handler(void)
{
#if NRF52
#if defined(NRF52_SERIES)
static volatile uint32_t reg;
static volatile uint32_t reg2;
static volatile uint32_t bfar;

200
ports/nrf/modules/machine/adc.c
View File

@ -3,7 +3,7 @@
*
* The MIT License (MIT)
*
* Copyright (c) 2017 Glenn Ruben Bakke
* Copyright (c) 2017-2018 Glenn Ruben Bakke
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
@ -30,36 +30,66 @@
#include "py/nlr.h"
#include "py/runtime.h"
#include "py/mphal.h"
#include "adc.h"
#include "hal_adc.h"
#if MICROPY_PY_MACHINE_ADC
#include "adc.h"
#if NRF51
#include "nrfx_adc.h"
#else
#include "nrfx_saadc.h"
#endif
typedef struct _machine_adc_obj_t {
mp_obj_base_t base;
ADC_HandleTypeDef *adc;
uint8_t id;
#if NRF51
uint8_t ain;
#endif
} machine_adc_obj_t;
ADC_HandleTypeDef ADCHandle0 = {.config.channel = 0};
ADC_HandleTypeDef ADCHandle1 = {.config.channel = 1};
ADC_HandleTypeDef ADCHandle2 = {.config.channel = 2};
ADC_HandleTypeDef ADCHandle3 = {.config.channel = 3};
ADC_HandleTypeDef ADCHandle4 = {.config.channel = 4};
ADC_HandleTypeDef ADCHandle5 = {.config.channel = 5};
ADC_HandleTypeDef ADCHandle6 = {.config.channel = 6};
ADC_HandleTypeDef ADCHandle7 = {.config.channel = 7};
STATIC const machine_adc_obj_t machine_adc_obj[] = {
{{&machine_adc_type}, &ADCHandle0},
{{&machine_adc_type}, &ADCHandle1},
{{&machine_adc_type}, &ADCHandle2},
{{&machine_adc_type}, &ADCHandle3},
{{&machine_adc_type}, &ADCHandle4},
{{&machine_adc_type}, &ADCHandle5},
{{&machine_adc_type}, &ADCHandle6},
{{&machine_adc_type}, &ADCHandle7},
#if NRF51
{{&machine_adc_type}, .id = 0, .ain = NRF_ADC_CONFIG_INPUT_0},
{{&machine_adc_type}, .id = 1, .ain = NRF_ADC_CONFIG_INPUT_1},
{{&machine_adc_type}, .id = 2, .ain = NRF_ADC_CONFIG_INPUT_2},
{{&machine_adc_type}, .id = 3, .ain = NRF_ADC_CONFIG_INPUT_3},
{{&machine_adc_type}, .id = 4, .ain = NRF_ADC_CONFIG_INPUT_4},
{{&machine_adc_type}, .id = 5, .ain = NRF_ADC_CONFIG_INPUT_5},
{{&machine_adc_type}, .id = 6, .ain = NRF_ADC_CONFIG_INPUT_6},
{{&machine_adc_type}, .id = 7, .ain = NRF_ADC_CONFIG_INPUT_7},
#else
{{&machine_adc_type}, .id = 0},
{{&machine_adc_type}, .id = 1},
{{&machine_adc_type}, .id = 2},
{{&machine_adc_type}, .id = 3},
{{&machine_adc_type}, .id = 4},
{{&machine_adc_type}, .id = 5},
{{&machine_adc_type}, .id = 6},
{{&machine_adc_type}, .id = 7},
#endif
};
#if defined(NRF52_SERIES)
STATIC void saadc_event_handler(nrfx_saadc_evt_t const * p_event) {
(void)p_event;
}
#endif
void adc_init0(void) {
#if defined(NRF52_SERIES)
const nrfx_saadc_config_t config = {
.resolution = NRF_SAADC_RESOLUTION_8BIT,
.oversample = NRF_SAADC_OVERSAMPLE_DISABLED,
.interrupt_priority = 6,
.low_power_mode = false
};
nrfx_saadc_init(&config, saadc_event_handler);
#endif
}
STATIC int adc_find(mp_obj_t id) {
// given an integer id
int adc_id = mp_obj_get_int(id);
@ -67,44 +97,54 @@ STATIC int adc_find(mp_obj_t id) {
int adc_idx = adc_id;
if (adc_idx >= 0 && adc_idx <= MP_ARRAY_SIZE(machine_adc_obj)
&& machine_adc_obj[adc_idx].adc != NULL) {
&& machine_adc_obj[adc_idx].id != -1) {
return adc_idx;
}
nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError,
"ADC(%d) does not exist", adc_id));
}
/// \method __str__()
/// Return a string describing the ADC object.
STATIC void machine_adc_print(const mp_print_t *print, mp_obj_t o, mp_print_kind_t kind) {
machine_adc_obj_t *self = o;
(void)self;
mp_printf(print, "ADC()");
mp_printf(print, "ADC(%u)", self->id);
}
/******************************************************************************/
/* MicroPython bindings for machine API */
// for make_new
enum {
ARG_NEW_PIN,
};
STATIC mp_obj_t machine_adc_make_new(const mp_obj_type_t *type, size_t n_args, size_t n_kw, const mp_obj_t *all_args) {
enum { ARG_id };
static const mp_arg_t allowed_args[] = {
{ ARG_NEW_PIN, MP_ARG_OBJ, {.u_obj = MP_OBJ_NEW_SMALL_INT(-1) } },
{ MP_QSTR_id, MP_ARG_OBJ, {.u_obj = MP_OBJ_NEW_SMALL_INT(-1) } },
};
// parse args
mp_arg_val_t args[MP_ARRAY_SIZE(allowed_args)];
mp_arg_parse_all_kw_array(n_args, n_kw, all_args, MP_ARRAY_SIZE(allowed_args), allowed_args, args);
int adc_id = adc_find(args[ARG_NEW_PIN].u_obj);
int adc_id = adc_find(args[ARG_id].u_obj);
const machine_adc_obj_t *self = &machine_adc_obj[adc_id];
#if defined(NRF52_SERIES)
const nrf_saadc_channel_config_t config = {
.resistor_p = NRF_SAADC_RESISTOR_DISABLED,
.resistor_n = NRF_SAADC_RESISTOR_DISABLED,
.gain = NRF_SAADC_GAIN1_4,
.reference = NRF_SAADC_REFERENCE_VDD4,
.acq_time = NRF_SAADC_ACQTIME_3US,
.mode = NRF_SAADC_MODE_SINGLE_ENDED,
.burst = NRF_SAADC_BURST_DISABLED,
.pin_p = self->id, // 0 - 7
.pin_n = NRF_SAADC_INPUT_DISABLED
};
nrfx_saadc_channel_init(self->id, &config);
#endif
return MP_OBJ_FROM_PTR(self);
}
@ -112,14 +152,106 @@ STATIC mp_obj_t machine_adc_make_new(const mp_obj_type_t *type, size_t n_args, s
/// Read adc level.
mp_obj_t machine_adc_value(mp_obj_t self_in) {
machine_adc_obj_t *self = self_in;
return MP_OBJ_NEW_SMALL_INT(hal_adc_channel_value(&self->adc->config));
#if NRF51
nrf_adc_value_t value = 0;
nrfx_adc_channel_t channel_config = {
.config.resolution = NRF_ADC_CONFIG_RES_8BIT,
.config.input = NRF_ADC_CONFIG_SCALING_INPUT_TWO_THIRDS,
.config.reference = NRF_ADC_CONFIG_REF_VBG,
.config.input = self->ain,
.config.extref = ADC_CONFIG_EXTREFSEL_None << ADC_CONFIG_EXTREFSEL_Pos // Currently not defined in nrfx/hal.
};
nrfx_adc_sample_convert(&channel_config, &value);
#else // NRF52
nrf_saadc_value_t value = 0;
nrfx_saadc_sample_convert(self->id, &value);
#endif
return MP_OBJ_NEW_SMALL_INT(value);
}
STATIC MP_DEFINE_CONST_FUN_OBJ_1(mp_machine_adc_value_obj, machine_adc_value);
#if NRF51
#define ADC_REF_VOLTAGE_IN_MILLIVOLT (1200) // Reference voltage in mV (1.2V).
#define ADC_PRE_SCALING_MULTIPLIER (3) // VDD 1/3 prescaling as input. Hence, multiplied by 3 to get the value of the battery voltage.
#else // NRF52
#define ADC_REF_VOLTAGE_IN_MILLIVOLT (600) // Reference voltage in mV (0.6V).
#define ADC_PRE_SCALING_MULTIPLIER (6) // VDD 1/6 prescaling as input. Hence, multiplied by 6 to get the value of the battery voltage.
#endif
#define DIODE_VOLT_DROP_MILLIVOLT (270) // Voltage drop over diode.
#define BATTERY_MILLIVOLT(VALUE) \
((((VALUE) * ADC_REF_VOLTAGE_IN_MILLIVOLT) / 255) * ADC_PRE_SCALING_MULTIPLIER)
static uint8_t battery_level_in_percent(const uint16_t mvolts)
{
uint8_t battery_level;
if (mvolts >= 3000) {
battery_level = 100;
} else if (mvolts > 2900) {
battery_level = 100 - ((3000 - mvolts) * 58) / 100;
} else if (mvolts > 2740) {
battery_level = 42 - ((2900 - mvolts) * 24) / 160;
} else if (mvolts > 2440) {
battery_level = 18 - ((2740 - mvolts) * 12) / 300;
} else if (mvolts > 2100) {
battery_level = 6 - ((2440 - mvolts) * 6) / 340;
} else {
battery_level = 0;
}
return battery_level;
}
/// \method battery_level()
/// Get battery level in percentage.
mp_obj_t machine_adc_battery_level(void) {
return MP_OBJ_NEW_SMALL_INT(hal_adc_battery_level());
#if NRF51
nrf_adc_value_t value = 0;
nrfx_adc_channel_t channel_config = {
.config.resolution = NRF_ADC_CONFIG_RES_8BIT,
.config.input = NRF_ADC_CONFIG_SCALING_SUPPLY_ONE_THIRD,
.config.reference = NRF_ADC_CONFIG_REF_VBG,
.config.input = NRF_ADC_CONFIG_INPUT_DISABLED,
.config.extref = ADC_CONFIG_EXTREFSEL_None << ADC_CONFIG_EXTREFSEL_Pos // Currently not defined in nrfx/hal.
};
nrfx_adc_sample_convert(&channel_config, &value);
#else // NRF52
nrf_saadc_value_t value = 0;
const nrf_saadc_channel_config_t config = {
.resistor_p = NRF_SAADC_RESISTOR_DISABLED,
.resistor_n = NRF_SAADC_RESISTOR_DISABLED,
.gain = NRF_SAADC_GAIN1_6,
.reference = NRF_SAADC_REFERENCE_INTERNAL,
.acq_time = NRF_SAADC_ACQTIME_3US,
.mode = NRF_SAADC_MODE_SINGLE_ENDED,
.burst = NRF_SAADC_BURST_DISABLED,
.pin_p = NRF_SAADC_INPUT_VDD,
.pin_n = NRF_SAADC_INPUT_DISABLED
};
nrfx_saadc_channel_init(0, &config);
nrfx_saadc_sample_convert(0, &value);
#endif
uint16_t batt_lvl_in_milli_volts = BATTERY_MILLIVOLT(value) + DIODE_VOLT_DROP_MILLIVOLT;
uint16_t batt_in_percent = battery_level_in_percent(batt_lvl_in_milli_volts);
return MP_OBJ_NEW_SMALL_INT(batt_in_percent);
}
STATIC MP_DEFINE_CONST_FUN_OBJ_0(mp_machine_adc_battery_level_obj, machine_adc_battery_level);

4
ports/nrf/modules/machine/adc.h
View File

@ -27,8 +27,8 @@
#ifndef ADC_H__
#define ADC_H__
#include "hal_adc.h"
extern const mp_obj_type_t machine_adc_type;
void adc_init0(void);
#endif // ADC_H__

106
ports/nrf/modules/machine/i2c.c
View File

@ -29,10 +29,11 @@
#include "py/nlr.h"
#include "py/runtime.h"
#include "py/mperrno.h"
#include "py/mphal.h"
#include "extmod/machine_i2c.h"
#include "i2c.h"
#include "hal_twi.h"
#include "nrfx_twi.h"
#if MICROPY_PY_MACHINE_I2C
@ -40,63 +41,41 @@ STATIC const mp_obj_type_t machine_hard_i2c_type;
typedef struct _machine_hard_i2c_obj_t {
mp_obj_base_t base;
TWI_HandleTypeDef *i2c;
nrfx_twi_t p_twi; // Driver instance
} machine_hard_i2c_obj_t;
TWI_HandleTypeDef I2CHandle0 = {.instance = NULL, .init.id = 0};
TWI_HandleTypeDef I2CHandle1 = {.instance = NULL, .init.id = 1};
STATIC const machine_hard_i2c_obj_t machine_hard_i2c_obj[] = {
{{&machine_hard_i2c_type}, &I2CHandle0},
{{&machine_hard_i2c_type}, &I2CHandle1},
{{&machine_hard_i2c_type}, .p_twi = NRFX_TWI_INSTANCE(0)},
{{&machine_hard_i2c_type}, .p_twi = NRFX_TWI_INSTANCE(1)},
};
void i2c_init0(void) {
// reset the I2C handles
memset(&I2CHandle0, 0, sizeof(TWI_HandleTypeDef));
I2CHandle0.instance = TWI_BASE(0);
memset(&I2CHandle1, 0, sizeof(TWI_HandleTypeDef));
I2CHandle0.instance = TWI_BASE(1);
}
STATIC int i2c_find(mp_obj_t id) {
// given an integer id
int i2c_id = mp_obj_get_int(id);
if (i2c_id >= 0 && i2c_id <= MP_ARRAY_SIZE(machine_hard_i2c_obj)
&& machine_hard_i2c_obj[i2c_id].i2c != NULL) {
if (i2c_id >= 0 && i2c_id < MP_ARRAY_SIZE(machine_hard_i2c_obj)) {
return i2c_id;
}
nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError,
"I2C(%d) does not exist", i2c_id));
}
STATIC void machine_hard_i2c_print(const mp_print_t *print, mp_obj_t o, mp_print_kind_t kind) {
machine_hard_i2c_obj_t *self = o;
mp_printf(print, "I2C(%u, scl=(port=%u, pin=%u), sda=(port=%u, pin=%u))",
self->i2c->init.id,
self->i2c->init.scl_pin->port,
self->i2c->init.scl_pin->pin,
self->i2c->init.sda_pin->port,
self->i2c->init.sda_pin->pin);
STATIC void machine_hard_i2c_print(const mp_print_t *print, mp_obj_t self_in, mp_print_kind_t kind) {
machine_hard_i2c_obj_t *self = self_in;
mp_printf(print, "I2C(%u)", self->p_twi.drv_inst_idx);
}
/******************************************************************************/
/* MicroPython bindings for machine API */
// for make_new
enum {
ARG_NEW_id,
ARG_NEW_scl,
ARG_NEW_sda,
ARG_NEW_freq,
ARG_NEW_timeout,
};
mp_obj_t machine_hard_i2c_make_new(const mp_obj_type_t *type, size_t n_args, size_t n_kw, const mp_obj_t *all_args) {
enum { ARG_id, ARG_scl, ARG_sda };
static const mp_arg_t allowed_args[] = {
{ ARG_NEW_id, MP_ARG_REQUIRED | MP_ARG_OBJ },
{ ARG_NEW_scl, MP_ARG_OBJ, {.u_obj = MP_OBJ_NULL} },
{ ARG_NEW_sda, MP_ARG_OBJ, {.u_obj = MP_OBJ_NULL} },
{ MP_QSTR_id, MP_ARG_REQUIRED | MP_ARG_OBJ },
{ MP_QSTR_scl, MP_ARG_REQUIRED | MP_ARG_OBJ },
{ MP_QSTR_sda, MP_ARG_REQUIRED | MP_ARG_OBJ },
};
// parse args
@ -104,36 +83,41 @@ mp_obj_t machine_hard_i2c_make_new(const mp_obj_type_t *type, size_t n_args, siz
mp_arg_parse_all_kw_array(n_args, n_kw, all_args, MP_ARRAY_SIZE(allowed_args), allowed_args, args);
// get static peripheral object
int i2c_id = i2c_find(args[ARG_NEW_id].u_obj);
int i2c_id = i2c_find(args[ARG_id].u_obj);
const machine_hard_i2c_obj_t *self = &machine_hard_i2c_obj[i2c_id];
if (args[ARG_NEW_scl].u_obj != MP_OBJ_NULL) {
self->i2c->init.scl_pin = args[ARG_NEW_scl].u_obj;
} else {
nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError,
"I2C SCL Pin not set"));
}
nrfx_twi_config_t config;
config.scl = mp_hal_get_pin_obj(args[ARG_scl].u_obj)->pin;
config.sda = mp_hal_get_pin_obj(args[ARG_sda].u_obj)->pin;
if (args[ARG_NEW_sda].u_obj != MP_OBJ_NULL) {
self->i2c->init.sda_pin = args[ARG_NEW_sda].u_obj;
} else {
nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError,
"I2C SDA Pin not set"));
}
config.frequency = NRF_TWI_FREQ_400K;
self->i2c->init.freq = HAL_TWI_FREQ_100_Kbps;
config.hold_bus_uninit = false;
hal_twi_master_init(self->i2c->instance, &self->i2c->init);
// Set context to this object.
nrfx_twi_init(&self->p_twi, &config, NULL, (void *)self);
return MP_OBJ_FROM_PTR(self);
}
#include <stdio.h>
int machine_hard_i2c_readfrom(mp_obj_base_t *self_in, uint16_t addr, uint8_t *dest, size_t len, bool stop) {
machine_hard_i2c_obj_t *self = (machine_hard_i2c_obj_t *)self_in;
hal_twi_master_rx(self->i2c->instance, addr, len, dest, stop);
nrfx_twi_enable(&self->p_twi);
nrfx_err_t err_code = nrfx_twi_rx(&self->p_twi, addr, dest, len);
if (err_code != NRFX_SUCCESS) {
if (err_code == NRFX_ERROR_DRV_TWI_ERR_ANACK) {
return -MP_ENODEV;
}
else if (err_code == NRFX_ERROR_DRV_TWI_ERR_DNACK) {
return -MP_EIO;
}
return -MP_ETIMEDOUT;
}
nrfx_twi_disable(&self->p_twi);
return 0;
}
@ -141,9 +125,23 @@ int machine_hard_i2c_readfrom(mp_obj_base_t *self_in, uint16_t addr, uint8_t *de
int machine_hard_i2c_writeto(mp_obj_base_t *self_in, uint16_t addr, const uint8_t *src, size_t len, bool stop) {
machine_hard_i2c_obj_t *self = (machine_hard_i2c_obj_t *)self_in;
hal_twi_master_tx(self->i2c->instance, addr, len, src, stop);
nrfx_twi_enable(&self->p_twi);
return 0;
nrfx_err_t err_code = nrfx_twi_tx(&self->p_twi, addr, src, len, !stop);
if (err_code != NRFX_SUCCESS) {
if (err_code == NRFX_ERROR_DRV_TWI_ERR_ANACK) {
return -MP_ENODEV;
}
else if (err_code == NRFX_ERROR_DRV_TWI_ERR_DNACK) {
return -MP_EIO;
}
return -MP_ETIMEDOUT;
}
nrfx_twi_disable(&self->p_twi);
return len;
}
STATIC const mp_machine_i2c_p_t machine_hard_i2c_p = {

2
ports/nrf/modules/machine/i2c.h
View File

@ -27,8 +27,6 @@
#ifndef I2C_H__
#define I2C_H__
#include "hal_twi.h"
extern const mp_obj_type_t machine_i2c_type;
void i2c_init0(void);

8
ports/nrf/modules/machine/led.c
View File

@ -33,8 +33,8 @@
#if MICROPY_HW_HAS_LED
#define LED_OFF(led) {(MICROPY_HW_LED_PULLUP) ? hal_gpio_pin_set(0, led) : hal_gpio_pin_clear(0, led); }
#define LED_ON(led) {(MICROPY_HW_LED_PULLUP) ? hal_gpio_pin_clear(0, led) : hal_gpio_pin_set(0, led); }
#define LED_OFF(pin) {(MICROPY_HW_LED_PULLUP) ? nrf_gpio_pin_set(pin) : nrf_gpio_pin_clear(pin); }
#define LED_ON(pin) {(MICROPY_HW_LED_PULLUP) ? nrf_gpio_pin_clear(pin) : nrf_gpio_pin_set(pin); }
typedef struct _pyb_led_obj_t {
mp_obj_base_t base;
@ -66,7 +66,7 @@ STATIC const pyb_led_obj_t pyb_led_obj[] = {
void led_init(void) {
for (uint8_t i = 0; i < NUM_LEDS; i++) {
LED_OFF(pyb_led_obj[i].hw_pin);
hal_gpio_cfg_pin(0, pyb_led_obj[i].hw_pin, HAL_GPIO_MODE_OUTPUT, HAL_GPIO_PULL_DISABLED);
nrf_gpio_cfg_output(pyb_led_obj[i].hw_pin);
}
}
@ -79,7 +79,7 @@ void led_state(pyb_led_obj_t * led_obj, int state) {
}
void led_toggle(pyb_led_obj_t * led_obj) {
hal_gpio_pin_toggle(0, led_obj->hw_pin);
nrf_gpio_pin_toggle(led_obj->hw_pin);
}

8
ports/nrf/modules/machine/modmachine.c
View File

@ -51,8 +51,8 @@
#if MICROPY_PY_MACHINE_TEMP
#include "temp.h"
#endif
#if MICROPY_PY_MACHINE_RTC
#include "rtc.h"
#if MICROPY_PY_MACHINE_RTCOUNTER
#include "rtcounter.h"
#endif
#define PYB_RESET_HARD (0)
@ -213,8 +213,8 @@ STATIC const mp_rom_map_elem_t machine_module_globals_table[] = {
#if MICROPY_PY_MACHINE_ADC
{ MP_ROM_QSTR(MP_QSTR_ADC), MP_ROM_PTR(&machine_adc_type) },
#endif
#if MICROPY_PY_MACHINE_RTC
{ MP_ROM_QSTR(MP_QSTR_RTC), MP_ROM_PTR(&machine_rtc_type) },
#if MICROPY_PY_MACHINE_RTCOUNTER
{ MP_ROM_QSTR(MP_QSTR_RTCounter), MP_ROM_PTR(&machine_rtcounter_type) },
#endif
#if MICROPY_PY_MACHINE_TIMER
{ MP_ROM_QSTR(MP_QSTR_Timer), MP_ROM_PTR(&machine_timer_type) },

50
ports/nrf/modules/machine/pin.c
View File

@ -34,6 +34,7 @@
#include "py/runtime.h"
#include "py/mphal.h"
#include "pin.h"
#include "nrf_gpio.h"
/// \moduleref pyb
/// \class Pin - control I/O pins
@ -101,9 +102,6 @@ STATIC bool pin_class_debug;
#define pin_class_debug (0)
#endif
// Forward declare function
void gpio_irq_event_callback(hal_gpio_event_channel_t channel);
void pin_init0(void) {
MP_STATE_PORT(pin_class_mapper) = mp_const_none;
MP_STATE_PORT(pin_class_map_dict) = mp_const_none;
@ -111,8 +109,6 @@ void pin_init0(void) {
#if PIN_DEBUG
pin_class_debug = false;
#endif
hal_gpio_register_callback(gpio_irq_event_callback);
}
// C API used to convert a user-supplied pin name into an ordinal pin number.
@ -374,9 +370,9 @@ STATIC mp_obj_t pin_obj_init_helper(const pin_obj_t *self, mp_uint_t n_args, con
mp_arg_parse_all(n_args, pos_args, kw_args, MP_ARRAY_SIZE(allowed_args), allowed_args, args);
// get pull mode
uint pull = HAL_GPIO_PULL_DISABLED;
nrf_gpio_pin_pull_t pull = NRF_GPIO_PIN_NOPULL;
if (args[1].u_obj != mp_const_none) {
pull = mp_obj_get_int(args[1].u_obj);
pull = (nrf_gpio_pin_pull_t)mp_obj_get_int(args[1].u_obj);
}
// if given, set the pin value before initialising to prevent glitches
@ -384,10 +380,21 @@ STATIC mp_obj_t pin_obj_init_helper(const pin_obj_t *self, mp_uint_t n_args, con
mp_hal_pin_write(self, mp_obj_is_true(args[3].u_obj));
}
// get io mode
uint mode = args[0].u_int;
if (mode == HAL_GPIO_MODE_OUTPUT || mode == HAL_GPIO_MODE_INPUT) {
hal_gpio_cfg_pin(self->port, self->pin, mode, pull);
nrf_gpio_pin_dir_t mode = (nrf_gpio_pin_dir_t)args[0].u_int;
// Connect input or not
nrf_gpio_pin_input_t input = (mode == NRF_GPIO_PIN_DIR_INPUT) ? NRF_GPIO_PIN_INPUT_CONNECT
: NRF_GPIO_PIN_INPUT_DISCONNECT;
if (mode == NRF_GPIO_PIN_DIR_OUTPUT || mode == NRF_GPIO_PIN_DIR_INPUT) {
nrf_gpio_cfg(self->pin,
mode,
input,
pull,
NRF_GPIO_PIN_S0S1,
NRF_GPIO_PIN_NOSENSE);
} else {
nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError, "invalid pin mode: %d", mode));
}
@ -508,6 +515,7 @@ STATIC mp_obj_t pin_af(mp_obj_t self_in) {
}
STATIC MP_DEFINE_CONST_FUN_OBJ_1(pin_af_obj, pin_af);
/*
STATIC mp_obj_t pin_irq(size_t n_args, const mp_obj_t *pos_args, mp_map_t *kw_args) {
static const mp_arg_t allowed_args[] = {
{ MP_QSTR_handler, MP_ARG_OBJ, {.u_obj = mp_const_none} },
@ -524,7 +532,7 @@ STATIC mp_obj_t pin_irq(size_t n_args, const mp_obj_t *pos_args, mp_map_t *kw_ar
return mp_const_none;
}
STATIC MP_DEFINE_CONST_FUN_OBJ_KW(pin_irq_obj, 1, pin_irq);
*/
STATIC const mp_rom_map_elem_t pin_locals_dict_table[] = {
// instance methods
@ -543,7 +551,7 @@ STATIC const mp_rom_map_elem_t pin_locals_dict_table[] = {
{ MP_ROM_QSTR(MP_QSTR_mode), MP_ROM_PTR(&pin_mode_obj) },
{ MP_ROM_QSTR(MP_QSTR_pull), MP_ROM_PTR(&pin_pull_obj) },
{ MP_ROM_QSTR(MP_QSTR_af), MP_ROM_PTR(&pin_af_obj) },
{ MP_ROM_QSTR(MP_QSTR_irq), MP_ROM_PTR(&pin_irq_obj) },
// { MP_ROM_QSTR(MP_QSTR_irq), MP_ROM_PTR(&pin_irq_obj) },
// class methods
{ MP_ROM_QSTR(MP_QSTR_mapper), MP_ROM_PTR(&pin_mapper_obj) },
@ -557,22 +565,22 @@ STATIC const mp_rom_map_elem_t pin_locals_dict_table[] = {
{ MP_ROM_QSTR(MP_QSTR_cpu), MP_ROM_PTR(&pin_cpu_pins_obj_type) },
// class constants
{ MP_ROM_QSTR(MP_QSTR_IN), MP_ROM_INT(HAL_GPIO_MODE_INPUT) },
{ MP_ROM_QSTR(MP_QSTR_OUT), MP_ROM_INT(HAL_GPIO_MODE_OUTPUT) },
{ MP_ROM_QSTR(MP_QSTR_IN), MP_ROM_INT(NRF_GPIO_PIN_DIR_INPUT) },
{ MP_ROM_QSTR(MP_QSTR_OUT), MP_ROM_INT(NRF_GPIO_PIN_DIR_OUTPUT) },
/*
{ MP_ROM_QSTR(MP_QSTR_OPEN_DRAIN), MP_ROM_INT(GPIO_MODE_OUTPUT_OD) },
{ MP_ROM_QSTR(MP_QSTR_ALT), MP_ROM_INT(GPIO_MODE_AF_PP) },
{ MP_ROM_QSTR(MP_QSTR_ALT_OPEN_DRAIN), MP_ROM_INT(GPIO_MODE_AF_OD) },
{ MP_ROM_QSTR(MP_QSTR_ANALOG), MP_ROM_INT(GPIO_MODE_ANALOG) },
*/
{ MP_ROM_QSTR(MP_QSTR_PULL_DISABLED), MP_ROM_INT(HAL_GPIO_PULL_DISABLED) },
{ MP_ROM_QSTR(MP_QSTR_PULL_UP), MP_ROM_INT(HAL_GPIO_PULL_UP) },
{ MP_ROM_QSTR(MP_QSTR_PULL_DOWN), MP_ROM_INT(HAL_GPIO_PULL_DOWN) },
{ MP_ROM_QSTR(MP_QSTR_PULL_DISABLED), MP_ROM_INT(NRF_GPIO_PIN_NOPULL) },
{ MP_ROM_QSTR(MP_QSTR_PULL_UP), MP_ROM_INT(NRF_GPIO_PIN_PULLUP) },
{ MP_ROM_QSTR(MP_QSTR_PULL_DOWN), MP_ROM_INT(NRF_GPIO_PIN_PULLDOWN) },
/*
// IRQ triggers, can be or'd together
{ MP_ROM_QSTR(MP_QSTR_IRQ_RISING), MP_ROM_INT(HAL_GPIO_POLARITY_EVENT_LOW_TO_HIGH) },
{ MP_ROM_QSTR(MP_QSTR_IRQ_FALLING), MP_ROM_INT(HAL_GPIO_POLARITY_EVENT_HIGH_TO_LOW) },
/*
// legacy class constants
{ MP_ROM_QSTR(MP_QSTR_OUT_PP), MP_ROM_INT(GPIO_MODE_OUTPUT_PP) },
{ MP_ROM_QSTR(MP_QSTR_OUT_OD), MP_ROM_INT(GPIO_MODE_OUTPUT_OD) },
@ -670,10 +678,6 @@ const mp_obj_type_t pin_af_type = {
/******************************************************************************/
// Pin IRQ object
void gpio_irq_event_callback(hal_gpio_event_channel_t channel) {
// printf("### gpio irq received on channel %d\n", (uint16_t)channel);
}
typedef struct _pin_irq_obj_t {
mp_obj_base_t base;
pin_obj_t pin;

264
ports/nrf/modules/machine/pwm.c
View File

@ -3,7 +3,7 @@
*
* The MIT License (MIT)
*
* Copyright (c) 2016 Glenn Ruben Bakke
* Copyright (c) 2016-2018 Glenn Ruben Bakke
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
@ -37,94 +37,81 @@
#include "genhdr/pins.h"
#include "pwm.h"
#if NRF52
#if defined(NRF52_SERIES)
// Use PWM hardware.
#include "hal_pwm.h"
#include "nrfx_pwm.h"
#endif
#ifdef MICROPY_HW_PWM0_NAME
PWM_HandleTypeDef PWMHandle0 = {.instance = NULL};
#endif
typedef enum {
MODE_LOW_HIGH,
MODE_HIGH_LOW
} pwm_mode_t;
STATIC const pyb_pwm_obj_t machine_pwm_obj[] = {
#ifdef MICROPY_HW_PWM0_NAME
{{&machine_hard_pwm_type}, &PWMHandle0},
#else
{{&machine_hard_pwm_type}, NULL},
#endif
typedef struct {
uint8_t pwm_pin;
uint8_t duty;
uint16_t pulse_width;
uint16_t period;
nrf_pwm_clk_t freq;
pwm_mode_t mode;
} machine_pwm_config_t;
typedef struct _machine_hard_pwm_obj_t {
mp_obj_base_t base;
const nrfx_pwm_t * p_pwm;
machine_pwm_config_t * p_config;
} machine_hard_pwm_obj_t;
STATIC const nrfx_pwm_t machine_hard_pwm_instances[] = {
#if NRF52
NRFX_PWM_INSTANCE(0),
NRFX_PWM_INSTANCE(1),
NRFX_PWM_INSTANCE(2),
#elif NRF52840
NRFX_PWM_INSTANCE(3),
#else
NULL
#endif
};
STATIC machine_pwm_config_t hard_configs[MP_ARRAY_SIZE(machine_hard_pwm_instances)];
STATIC const machine_hard_pwm_obj_t machine_hard_pwm_obj[] = {
#if NRF52
{{&machine_hard_pwm_type}, .p_pwm = &machine_hard_pwm_instances[0], .p_config = &hard_configs[0]},
{{&machine_hard_pwm_type}, .p_pwm = &machine_hard_pwm_instances[1], .p_config = &hard_configs[0]},
{{&machine_hard_pwm_type}, .p_pwm = &machine_hard_pwm_instances[2], .p_config = &hard_configs[0]},
#elif NRF52840
{{&machine_hard_pwm_type}, .p_pwm = &machine_hard_pwm_instances[3], .p_config = &hard_configs[0]},
#endif
};
void pwm_init0(void) {
// reset the PWM handles
#ifdef MICROPY_HW_PWM0_NAME
memset(&PWMHandle0, 0, sizeof(PWM_HandleTypeDef));
PWMHandle0.instance = PWM0;
#endif
}
STATIC int pwm_find(mp_obj_t id) {
if (MP_OBJ_IS_STR(id)) {
// given a string id
const char *port = mp_obj_str_get_str(id);
if (0) {
#ifdef MICROPY_HW_PWM0_NAME
} else if (strcmp(port, MICROPY_HW_PWM0_NAME) == 0) {
return 1;
#endif
}
nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError,
"PWM(%s) does not exist", port));
} else {
STATIC int hard_pwm_find(mp_obj_t id) {
if (MP_OBJ_IS_INT(id)) {
// given an integer id
int pwm_id = mp_obj_get_int(id);
if (pwm_id >= 0 && pwm_id <= MP_ARRAY_SIZE(machine_pwm_obj)
&& machine_pwm_obj[pwm_id].pwm != NULL) {
if (pwm_id >= 0 && pwm_id <= MP_ARRAY_SIZE(machine_hard_pwm_obj)) {
return pwm_id;
}
nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError,
"PWM(%d) does not exist", pwm_id));
}
return -1;
}
void pwm_init(PWM_HandleTypeDef *pwm) {
// start pwm
hal_pwm_start(pwm->instance);
}
void pwm_deinit(PWM_HandleTypeDef *pwm) {
// stop pwm
hal_pwm_stop(pwm->instance);
}
STATIC void pwm_print(const mp_print_t *print, PWM_HandleTypeDef *pwm, bool legacy) {
uint pwm_num = 0; // default to PWM0
mp_printf(print, "PWM(%u)", pwm_num);
STATIC void machine_pwm_print(const mp_print_t *print, mp_obj_t self_in, mp_print_kind_t kind) {
machine_hard_pwm_obj_t *self = self_in;
mp_printf(print, "PWM(%u)", self->p_pwm->drv_inst_idx);
}
/******************************************************************************/
/* MicroPython bindings for machine API */
// for make_new
enum {
ARG_NEW_id,
ARG_NEW_pin,
ARG_NEW_freq,
ARG_NEW_period,
ARG_NEW_duty,
ARG_NEW_pulse_width,
ARG_NEW_mode
};
// for init
enum {
ARG_INIT_pin
};
// for freq
enum {
ARG_FREQ_freq
};
STATIC mp_obj_t machine_hard_pwm_make_new(mp_arg_val_t *args);
STATIC void machine_hard_pwm_init(mp_obj_t self, mp_arg_val_t *args);
STATIC void machine_hard_pwm_deinit(mp_obj_t self);
@ -133,6 +120,7 @@ STATIC mp_obj_t machine_hard_pwm_freq(mp_obj_t self, mp_arg_val_t *args);
/* common code for both soft and hard implementations *************************/
STATIC mp_obj_t machine_pwm_make_new(const mp_obj_type_t *type, size_t n_args, size_t n_kw, const mp_obj_t *all_args) {
enum { ARG_id, ARG_pin, ARG_freq, ARG_period, ARG_duty, ARG_pulse_width, ARG_mode };
static const mp_arg_t allowed_args[] = {
{ MP_QSTR_id, MP_ARG_OBJ, {.u_obj = MP_OBJ_NEW_SMALL_INT(-1)} },
{ MP_QSTR_pin, MP_ARG_OBJ, {.u_obj = MP_OBJ_NULL} },
@ -147,7 +135,7 @@ STATIC mp_obj_t machine_pwm_make_new(const mp_obj_type_t *type, size_t n_args, s
mp_arg_val_t args[MP_ARRAY_SIZE(allowed_args)];
mp_arg_parse_all_kw_array(n_args, n_kw, all_args, MP_ARRAY_SIZE(allowed_args), allowed_args, args);
if (args[ARG_NEW_id].u_obj == MP_OBJ_NEW_SMALL_INT(-1)) {
if (args[ARG_id].u_obj == MP_OBJ_NEW_SMALL_INT(-1)) {
// TODO: implement soft PWM
// return machine_soft_pwm_make_new(args);
return mp_const_none;
@ -158,6 +146,7 @@ STATIC mp_obj_t machine_pwm_make_new(const mp_obj_type_t *type, size_t n_args, s
}
STATIC mp_obj_t machine_pwm_init(size_t n_args, const mp_obj_t *pos_args, mp_map_t *kw_args) {
enum { ARG_INIT_pin };
static const mp_arg_t allowed_args[] = {
{ MP_QSTR_pin, MP_ARG_KW_ONLY | MP_ARG_OBJ, {.u_obj = MP_OBJ_NULL} }
};
@ -186,6 +175,7 @@ STATIC mp_obj_t machine_pwm_deinit(mp_obj_t self) {
STATIC MP_DEFINE_CONST_FUN_OBJ_1(machine_pwm_deinit_obj, machine_pwm_deinit);
STATIC mp_obj_t machine_pwm_freq(size_t n_args, const mp_obj_t *pos_args, mp_map_t *kw_args) {
enum { ARG_FREQ_freq };
static const mp_arg_t allowed_args[] = {
{ MP_QSTR_freq, MP_ARG_INT, {.u_int = -1} },
};
@ -222,109 +212,141 @@ STATIC const mp_rom_map_elem_t machine_pwm_locals_dict_table[] = {
{ MP_ROM_QSTR(MP_QSTR_period), MP_ROM_PTR(&mp_machine_pwm_period_obj) },
{ MP_ROM_QSTR(MP_QSTR_duty), MP_ROM_PTR(&mp_machine_pwm_duty_obj) },
{ MP_ROM_QSTR(MP_QSTR_FREQ_16MHZ), MP_ROM_INT(HAL_PWM_FREQ_16Mhz) },
{ MP_ROM_QSTR(MP_QSTR_FREQ_8MHZ), MP_ROM_INT(HAL_PWM_FREQ_8Mhz) },
{ MP_ROM_QSTR(MP_QSTR_FREQ_4MHZ), MP_ROM_INT(HAL_PWM_FREQ_4Mhz) },
{ MP_ROM_QSTR(MP_QSTR_FREQ_2MHZ), MP_ROM_INT(HAL_PWM_FREQ_2Mhz) },
{ MP_ROM_QSTR(MP_QSTR_FREQ_1MHZ), MP_ROM_INT(HAL_PWM_FREQ_1Mhz) },
{ MP_ROM_QSTR(MP_QSTR_FREQ_500KHZ), MP_ROM_INT(HAL_PWM_FREQ_500khz) },
{ MP_ROM_QSTR(MP_QSTR_FREQ_250KHZ), MP_ROM_INT(HAL_PWM_FREQ_250khz) },
{ MP_ROM_QSTR(MP_QSTR_FREQ_125KHZ), MP_ROM_INT(HAL_PWM_FREQ_125khz) },
{ MP_ROM_QSTR(MP_QSTR_FREQ_16MHZ), MP_ROM_INT(NRF_PWM_CLK_16MHz) },
{ MP_ROM_QSTR(MP_QSTR_FREQ_8MHZ), MP_ROM_INT(NRF_PWM_CLK_8MHz) },
{ MP_ROM_QSTR(MP_QSTR_FREQ_4MHZ), MP_ROM_INT(NRF_PWM_CLK_4MHz) },
{ MP_ROM_QSTR(MP_QSTR_FREQ_2MHZ), MP_ROM_INT(NRF_PWM_CLK_2MHz) },
{ MP_ROM_QSTR(MP_QSTR_FREQ_1MHZ), MP_ROM_INT(NRF_PWM_CLK_1MHz) },
{ MP_ROM_QSTR(MP_QSTR_FREQ_500KHZ), MP_ROM_INT(NRF_PWM_CLK_500kHz) },
{ MP_ROM_QSTR(MP_QSTR_FREQ_250KHZ), MP_ROM_INT(NRF_PWM_CLK_250kHz) },
{ MP_ROM_QSTR(MP_QSTR_FREQ_125KHZ), MP_ROM_INT(NRF_PWM_CLK_125kHz) },
{ MP_ROM_QSTR(MP_QSTR_MODE_LOW_HIGH), MP_ROM_INT(HAL_PWM_MODE_LOW_HIGH) },
{ MP_ROM_QSTR(MP_QSTR_MODE_HIGH_LOW), MP_ROM_INT(HAL_PWM_MODE_HIGH_LOW) },
{ MP_ROM_QSTR(MP_QSTR_MODE_LOW_HIGH), MP_ROM_INT(MODE_LOW_HIGH) },
{ MP_ROM_QSTR(MP_QSTR_MODE_HIGH_LOW), MP_ROM_INT(MODE_HIGH_LOW) },
};
STATIC MP_DEFINE_CONST_DICT(machine_pwm_locals_dict, machine_pwm_locals_dict_table);
/* code for hard implementation ***********************************************/
STATIC const machine_hard_pwm_obj_t machine_hard_pwm_obj[] = {
{{&machine_hard_pwm_type}, &machine_pwm_obj[0]},
};
STATIC void machine_hard_pwm_print(const mp_print_t *print, mp_obj_t self_in, mp_print_kind_t kind) {
machine_hard_pwm_obj_t *self = self_in;
pwm_print(print, self->pyb->pwm, false);
}
STATIC mp_obj_t machine_hard_pwm_make_new(mp_arg_val_t *args) {
enum { ARG_id, ARG_pin, ARG_freq, ARG_period, ARG_duty, ARG_pulse_width, ARG_mode };
// get static peripheral object
int pwm_id = pwm_find(args[ARG_NEW_id].u_obj);
int pwm_id = hard_pwm_find(args[ARG_id].u_obj);
const machine_hard_pwm_obj_t *self = &machine_hard_pwm_obj[pwm_id];
// check if PWM pin is set
if (args[ARG_NEW_pin].u_obj != MP_OBJ_NULL) {
pin_obj_t *pin_obj = args[ARG_NEW_pin].u_obj;
self->pyb->pwm->init.pwm_pin = pin_obj->pin;
if (args[ARG_pin].u_obj != MP_OBJ_NULL) {
pin_obj_t *pin_obj = args[ARG_pin].u_obj;
self->p_config->pwm_pin = pin_obj->pin;
} else {
// TODO: raise exception.
}
if (args[ARG_NEW_freq].u_obj != MP_OBJ_NULL) {
self->pyb->pwm->init.freq = mp_obj_get_int(args[ARG_NEW_freq].u_obj);
if (args[ARG_freq].u_obj != MP_OBJ_NULL) {
self->p_config->freq = mp_obj_get_int(args[ARG_freq].u_obj);
} else {
self->pyb->pwm->init.freq = 50; // 50 Hz by default.
self->p_config->freq = 50; // 50 Hz by default.
}
if (args[ARG_NEW_period].u_obj != MP_OBJ_NULL) {
self->pyb->pwm->init.period = mp_obj_get_int(args[ARG_NEW_period].u_obj);
if (args[ARG_period].u_obj != MP_OBJ_NULL) {
self->p_config->period = mp_obj_get_int(args[ARG_period].u_obj);
} else {
nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError,
"PWM period has to be within 16000 frequence cycles", self->pyb->pwm->init.period));
"PWM period has to be within 16000 frequence cycles", self->p_config->period));
}
if (args[ARG_NEW_duty].u_obj != MP_OBJ_NULL) {
self->pyb->pwm->init.duty = mp_obj_get_int(args[ARG_NEW_duty].u_obj);
if (args[ARG_duty].u_obj != MP_OBJ_NULL) {
self->p_config->duty = mp_obj_get_int(args[ARG_duty].u_obj);
} else {
self->pyb->pwm->init.duty = 50; // 50% by default.
self->p_config->duty = 50; // 50% by default.
}
if (args[ARG_NEW_pulse_width].u_obj != MP_OBJ_NULL) {
self->pyb->pwm->init.pulse_width = mp_obj_get_int(args[ARG_NEW_pulse_width].u_obj);
if (args[ARG_pulse_width].u_obj != MP_OBJ_NULL) {
self->p_config->pulse_width = mp_obj_get_int(args[ARG_pulse_width].u_obj);
} else {
self->pyb->pwm->init.pulse_width = 0;
self->p_config->pulse_width = 0;
}
if (args[ARG_NEW_mode].u_obj != MP_OBJ_NULL) {
self->pyb->pwm->init.mode = mp_obj_get_int(args[ARG_NEW_mode].u_obj);
if (args[ARG_mode].u_obj != MP_OBJ_NULL) {
self->p_config->mode = mp_obj_get_int(args[ARG_mode].u_obj);
} else {
self->pyb->pwm->init.mode = HAL_PWM_MODE_HIGH_LOW;
self->p_config->mode = MODE_HIGH_LOW;
}
hal_pwm_init(self->pyb->pwm->instance, &self->pyb->pwm->init);
return MP_OBJ_FROM_PTR(self);
}
STATIC void machine_hard_pwm_init(mp_obj_t self_in, mp_arg_val_t *args) {
machine_hard_pwm_obj_t *self = self_in;
pwm_init(self->pyb->pwm);
machine_hard_pwm_obj_t *self = self_in;
nrfx_pwm_config_t config;
config.output_pins[0] = self->p_config->pwm_pin;
config.output_pins[1] = NRFX_PWM_PIN_NOT_USED;
config.output_pins[2] = NRFX_PWM_PIN_NOT_USED;
config.output_pins[3] = NRFX_PWM_PIN_NOT_USED;
config.irq_priority = 6;
config.base_clock = self->p_config->freq;
config.count_mode = NRF_PWM_MODE_UP;
config.top_value = self->p_config->period;
config.load_mode = NRF_PWM_LOAD_INDIVIDUAL;
config.step_mode = NRF_PWM_STEP_AUTO;
nrfx_pwm_init(self->p_pwm, &config, NULL);
uint16_t pulse_width = ((self->p_config->period * self->p_config->duty) / 100);
// If manual period has been set, override duty-cycle.
if (self->p_config->pulse_width > 0) {
pulse_width = self->p_config->pulse_width;
}
// TODO: Move DMA buffer to global memory.
volatile static uint16_t pwm_seq[4];
if (self->p_config->mode == MODE_HIGH_LOW) {
pwm_seq[0] = self->p_config->period - pulse_width;
pwm_seq[1] = self->p_config->period - pulse_width;
} else {
pwm_seq[0] = self->p_config->period - pulse_width;
pwm_seq[1] = self->p_config->period - pulse_width;
}
pwm_seq[2] = self->p_config->period - pulse_width;
pwm_seq[3] = self->p_config->period - pulse_width;
const nrf_pwm_sequence_t pwm_sequence = {
.values.p_raw = (const uint16_t *)&pwm_seq,
.length = 4,
.repeats = 0,
.end_delay = 0
};
nrfx_pwm_simple_playback(self->p_pwm,
&pwm_sequence,
0, // Loop disabled.
0);
}
STATIC void machine_hard_pwm_deinit(mp_obj_t self_in) {
machine_hard_pwm_obj_t *self = self_in;
pwm_deinit(self->pyb->pwm);
(void)self;
nrfx_pwm_stop(self->p_pwm, true);
nrfx_pwm_uninit(self->p_pwm);
}
STATIC mp_obj_t machine_hard_pwm_freq(mp_obj_t self_in, mp_arg_val_t *args) {
machine_hard_pwm_obj_t *self = self_in;
if (args[ARG_FREQ_freq].u_int != -1) {
self->pyb->pwm->init.freq = args[ARG_FREQ_freq].u_int;
hal_pwm_init(self->pyb->pwm->instance, &self->pyb->pwm->init);
} else {
return MP_OBJ_NEW_SMALL_INT(self->pyb->pwm->init.freq);
}
(void)self;
return mp_const_none;
}
const mp_obj_type_t machine_hard_pwm_type = {
{ &mp_type_type },
.name = MP_QSTR_PWM,
.print = machine_hard_pwm_print,
.print = machine_pwm_print,
.make_new = machine_pwm_make_new,
.locals_dict = (mp_obj_dict_t*)&machine_pwm_locals_dict,
};

14
ports/nrf/modules/machine/pwm.h
View File

@ -3,7 +3,7 @@
*
* The MIT License (MIT)
*
* Copyright (c) 2016 Glenn Ruben Bakke
* Copyright (c) 2016-2018 Glenn Ruben Bakke
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
@ -24,18 +24,6 @@
* THE SOFTWARE.
*/
#include "hal_pwm.h"
typedef struct _pyb_pwm_obj_t {
mp_obj_base_t base;
PWM_HandleTypeDef *pwm;
} pyb_pwm_obj_t;
typedef struct _machine_hard_pwm_obj_t {
mp_obj_base_t base;
const pyb_pwm_obj_t *pyb;
} machine_hard_pwm_obj_t;
void pwm_init0(void);
extern const mp_obj_type_t machine_hard_pwm_type;

178
ports/nrf/modules/machine/rtc.c
View File

@ -1,178 +0,0 @@
/*
* This file is part of the MicroPython project, http://micropython.org/
*
* The MIT License (MIT)
*
* Copyright (c) 2016 Glenn Ruben Bakke
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
#include <stdio.h>
#include <string.h>
#include "py/nlr.h"
#include "py/runtime.h"
#include "py/mphal.h"
#include "rtc.h"
#include "hal_rtc.h"
#if MICROPY_PY_MACHINE_RTC
typedef struct _machine_rtc_obj_t {
mp_obj_base_t base;
hal_rtc_conf_t * p_config;
mp_obj_t callback;
mp_int_t period;
mp_int_t mode;
} machine_rtc_obj_t;
static hal_rtc_conf_t rtc_config0 = {.id = 0};
static hal_rtc_conf_t rtc_config1 = {.id = 1};
#if NRF52
static hal_rtc_conf_t rtc_config2 = {.id = 2};
#endif
STATIC machine_rtc_obj_t machine_rtc_obj[] = {
{{&machine_rtc_type}, &rtc_config0},
{{&machine_rtc_type}, &rtc_config1},
#if NRF52
{{&machine_rtc_type}, &rtc_config2},
#endif
};
STATIC void hal_interrupt_handle(uint8_t id) {
machine_rtc_obj_t * self = &machine_rtc_obj[id];;
mp_call_function_1(self->callback, self);
if (self != NULL) {
hal_rtc_stop(id);
if (self->mode == 1) {
hal_rtc_start(id);
}
}
}
void rtc_init0(void) {
hal_rtc_callback_set(hal_interrupt_handle);
}
STATIC int rtc_find(mp_obj_t id) {
// given an integer id
int rtc_id = mp_obj_get_int(id);
if (rtc_id >= 0 && rtc_id <= MP_ARRAY_SIZE(machine_rtc_obj)
&& machine_rtc_obj[rtc_id].p_config != NULL) {
return rtc_id;
}
nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError,
"RTC(%d) does not exist", rtc_id));
}
STATIC void rtc_print(const mp_print_t *print, mp_obj_t o, mp_print_kind_t kind) {
machine_rtc_obj_t *self = o;
mp_printf(print, "RTC(%u)", self->p_config->id);
}
/******************************************************************************/
/* MicroPython bindings for machine API */
STATIC mp_obj_t machine_rtc_make_new(const mp_obj_type_t *type, size_t n_args, size_t n_kw, const mp_obj_t *all_args) {
static const mp_arg_t allowed_args[] = {
{ MP_QSTR_id, MP_ARG_OBJ, {.u_obj = MP_OBJ_NEW_SMALL_INT(-1)} },
{ MP_QSTR_period, MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = 1000} },
{ MP_QSTR_mode, MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = 1} },
{ MP_QSTR_callback, MP_ARG_KW_ONLY | MP_ARG_OBJ, {.u_obj = mp_const_none} },
};
// parse args
mp_arg_val_t args[MP_ARRAY_SIZE(allowed_args)];
mp_arg_parse_all_kw_array(n_args, n_kw, all_args, MP_ARRAY_SIZE(allowed_args), allowed_args, args);
// get static peripheral object
int rtc_id = rtc_find(args[0].u_obj);
// unconst machine object in order to set a callback.
machine_rtc_obj_t * self = (machine_rtc_obj_t *)&machine_rtc_obj[rtc_id];
self->p_config->period = args[1].u_int;
self->mode = args[2].u_int;
if (args[3].u_obj != mp_const_none) {
self->callback = args[3].u_obj;
}
#ifdef NRF51
self->p_config->irq_priority = 3;
#else
self->p_config->irq_priority = 6;
#endif
hal_rtc_init(self->p_config);
return MP_OBJ_FROM_PTR(self);
}
/// \method start(period)
/// Start the RTC timer. Timeout occurs after number of periods
/// in the configured frequency has been reached.
///
STATIC mp_obj_t machine_rtc_start(mp_obj_t self_in) {
machine_rtc_obj_t * self = MP_OBJ_TO_PTR(self_in);
hal_rtc_start(self->p_config->id);
return mp_const_none;
}
STATIC MP_DEFINE_CONST_FUN_OBJ_1(machine_rtc_start_obj, machine_rtc_start);
/// \method stop()
/// Stop the RTC timer.
///
STATIC mp_obj_t machine_rtc_stop(mp_obj_t self_in) {
machine_rtc_obj_t * self = MP_OBJ_TO_PTR(self_in);
hal_rtc_stop(self->p_config->id);
return mp_const_none;
}
STATIC MP_DEFINE_CONST_FUN_OBJ_1(machine_rtc_stop_obj, machine_rtc_stop);
STATIC const mp_rom_map_elem_t machine_rtc_locals_dict_table[] = {
{ MP_ROM_QSTR(MP_QSTR_start), MP_ROM_PTR(&machine_rtc_start_obj) },
{ MP_ROM_QSTR(MP_QSTR_stop), MP_ROM_PTR(&machine_rtc_stop_obj) },
// constants
{ MP_ROM_QSTR(MP_QSTR_ONESHOT), MP_ROM_INT(0) },
{ MP_ROM_QSTR(MP_QSTR_PERIODIC), MP_ROM_INT(1) },
};
STATIC MP_DEFINE_CONST_DICT(machine_rtc_locals_dict, machine_rtc_locals_dict_table);
const mp_obj_type_t machine_rtc_type = {
{ &mp_type_type },
.name = MP_QSTR_RTC,
.print = rtc_print,
.make_new = machine_rtc_make_new,
.locals_dict = (mp_obj_dict_t*)&machine_rtc_locals_dict
};
#endif // MICROPY_PY_MACHINE_RTC

267
ports/nrf/modules/machine/rtcounter.c Normal file
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@ -0,0 +1,267 @@
/*
* This file is part of the MicroPython project, http://micropython.org/
*
* The MIT License (MIT)
*
* Copyright (c) 2016 Glenn Ruben Bakke
* Copyright (c) 2018 Ayke van Laethem
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
#include "py/nlr.h"
#include "py/runtime.h"
#include "rtcounter.h"
#include "nrfx_rtc.h"
#include "nrf_clock.h"
#if MICROPY_PY_MACHINE_RTCOUNTER
// Count every 125ms (~maximum prescaler setting)
#define RTC_FREQUENCY (8UL)
enum {
RTC_MODE_ONESHOT,
RTC_MODE_PERIODIC,
};
// Volatile part of the RTCounter object.
typedef struct {
mp_obj_t callback;
uint32_t period;
} machine_rtc_config_t;
// Non-volatile part of the RTCounter object.
typedef struct _machine_rtc_obj_t {
mp_obj_base_t base;
const nrfx_rtc_t * p_rtc; // Driver instance
nrfx_rtc_handler_t handler; // interrupt callback
machine_rtc_config_t * config; // pointer to volatile part
} machine_rtc_obj_t;
STATIC const nrfx_rtc_t machine_rtc_instances[] = {
NRFX_RTC_INSTANCE(0),
NRFX_RTC_INSTANCE(1),
#if NRF52
NRFX_RTC_INSTANCE(2),
#endif
};
STATIC machine_rtc_config_t configs[MP_ARRAY_SIZE(machine_rtc_instances)];
STATIC void interrupt_handler0(nrfx_rtc_int_type_t int_type);
STATIC void interrupt_handler1(nrfx_rtc_int_type_t int_type);
#if NRF52
STATIC void interrupt_handler2(nrfx_rtc_int_type_t int_type);
#endif
STATIC const machine_rtc_obj_t machine_rtc_obj[] = {
{{&machine_rtcounter_type}, .p_rtc = &machine_rtc_instances[0], .handler=interrupt_handler0, .config=&configs[0]},
{{&machine_rtcounter_type}, .p_rtc = &machine_rtc_instances[1], .handler=interrupt_handler1, .config=&configs[1]},
#if NRF52
{{&machine_rtcounter_type}, .p_rtc = &machine_rtc_instances[2], .handler=interrupt_handler2, .config=&configs[2]},
#endif
};
STATIC void interrupt_handler(size_t instance_id) {
const machine_rtc_obj_t * self = &machine_rtc_obj[instance_id];
machine_rtc_config_t *config = self->config;
if (config->callback != NULL) {
mp_call_function_1((mp_obj_t)config->callback, (mp_obj_t)self);
}
if (config->period == 0) {
nrfx_rtc_cc_disable(self->p_rtc, 0);
} else { // periodic
uint32_t val = nrfx_rtc_counter_get(self->p_rtc) + config->period;
nrfx_rtc_cc_set(self->p_rtc, 0, val, true);
}
}
STATIC void interrupt_handler0(nrfx_rtc_int_type_t int_type) {
interrupt_handler(0);
}
STATIC void interrupt_handler1(nrfx_rtc_int_type_t int_type) {
interrupt_handler(1);
}
#if NRF52
STATIC void interrupt_handler2(nrfx_rtc_int_type_t int_type) {
interrupt_handler(2);
}
#endif
void rtc_init0(void) {
}
STATIC int rtc_find(mp_obj_t id) {
// given an integer id
int rtc_id = mp_obj_get_int(id);
if (rtc_id >= 0 && rtc_id <= MP_ARRAY_SIZE(machine_rtc_obj)) {
return rtc_id;
}
nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError,
"RTCounter(%d) does not exist", rtc_id));
}
STATIC void rtc_print(const mp_print_t *print, mp_obj_t self_in, mp_print_kind_t kind) {
machine_rtc_obj_t *self = self_in;
mp_printf(print, "RTCounter(%u)", self->p_rtc->instance_id);
}
/******************************************************************************/
/* MicroPython bindings for machine API */
const nrfx_rtc_config_t machine_rtc_config = {
.prescaler = RTC_FREQ_TO_PRESCALER(RTC_FREQUENCY),
.reliable = 0,
.tick_latency = 0, // ignored when reliable == 0
#ifdef NRF51
.interrupt_priority = 3,
#else
.interrupt_priority = 6,
#endif
};
STATIC mp_obj_t machine_rtc_make_new(const mp_obj_type_t *type, size_t n_args, size_t n_kw, const mp_obj_t *all_args) {
enum { ARG_id, ARG_period, ARG_mode, ARG_callback };
static const mp_arg_t allowed_args[] = {
{ MP_QSTR_id, MP_ARG_OBJ, {.u_obj = MP_OBJ_NEW_SMALL_INT(-1)} },
{ MP_QSTR_period, MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = RTC_FREQUENCY} }, // 1 second
{ MP_QSTR_mode, MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = RTC_MODE_PERIODIC} },
{ MP_QSTR_callback, MP_ARG_KW_ONLY | MP_ARG_OBJ, {.u_obj = mp_const_none} },
};
// parse args
mp_arg_val_t args[MP_ARRAY_SIZE(allowed_args)];
mp_arg_parse_all_kw_array(n_args, n_kw, all_args, MP_ARRAY_SIZE(allowed_args), allowed_args, args);
int rtc_id = rtc_find(args[ARG_id].u_obj);
// const and non-const part of the RTC object.
const machine_rtc_obj_t * self = &machine_rtc_obj[rtc_id];
machine_rtc_config_t *config = self->config;
if (args[ARG_callback].u_obj == mp_const_none) {
config->callback = NULL;
} else if (MP_OBJ_IS_FUN(args[ARG_callback].u_obj)) {
config->callback = args[ARG_callback].u_obj;
} else {
mp_raise_ValueError("callback must be a function");
}
// Periodic or one-shot
if (args[ARG_mode].u_int == RTC_MODE_ONESHOT) {
// One-shot
config->period = 0;
} else {
// Period between the intervals
config->period = args[ARG_period].u_int;
}
// Start the low-frequency clock (if it hasn't been started already)
if (!nrf_clock_lf_is_running()) {
nrf_clock_task_trigger(NRF_CLOCK_TASK_LFCLKSTART);
}
// Make sure it's uninitialized.
nrfx_rtc_uninit(self->p_rtc);
nrfx_rtc_counter_clear(self->p_rtc);
// Initialize and set the correct IRQ.
nrfx_rtc_init(self->p_rtc, &machine_rtc_config, self->handler);
nrfx_rtc_cc_set(self->p_rtc, 0 /*channel*/, args[ARG_period].u_int, true /*enable irq*/);
return MP_OBJ_FROM_PTR(self);
}
/// \method start()
/// Start the RTCounter. Timeout occurs after number of periods
/// in the configured frequency has been reached.
///
STATIC mp_obj_t machine_rtc_start(mp_obj_t self_in) {
machine_rtc_obj_t * self = MP_OBJ_TO_PTR(self_in);
nrfx_rtc_enable(self->p_rtc);
return mp_const_none;
}
STATIC MP_DEFINE_CONST_FUN_OBJ_1(machine_rtc_start_obj, machine_rtc_start);
/// \method stop()
/// Stop the RTCounter.
///
STATIC mp_obj_t machine_rtc_stop(mp_obj_t self_in) {
machine_rtc_obj_t * self = MP_OBJ_TO_PTR(self_in);
nrfx_rtc_disable(self->p_rtc);
return mp_const_none;
}
STATIC MP_DEFINE_CONST_FUN_OBJ_1(machine_rtc_stop_obj, machine_rtc_stop);
/// \method counter()
/// Return the current counter value. Wraps around after about 24 days
/// with the current prescaler (2^24 / 8 = 2097152 seconds).
///
STATIC mp_obj_t machine_rtc_counter(mp_obj_t self_in) {
machine_rtc_obj_t * self = MP_OBJ_TO_PTR(self_in);
uint32_t counter = nrfx_rtc_counter_get(self->p_rtc);
return MP_OBJ_NEW_SMALL_INT(counter);
}
STATIC MP_DEFINE_CONST_FUN_OBJ_1(machine_rtc_counter_obj, machine_rtc_counter);
/// \method deinit()
/// Free resources associated with this RTC.
///
STATIC mp_obj_t machine_rtc_deinit(mp_obj_t self_in) {
machine_rtc_obj_t * self = MP_OBJ_TO_PTR(self_in);
nrfx_rtc_uninit(self->p_rtc);
return mp_const_none;
}
STATIC MP_DEFINE_CONST_FUN_OBJ_1(machine_rtc_deinit_obj, machine_rtc_deinit);
STATIC const mp_rom_map_elem_t machine_rtc_locals_dict_table[] = {
{ MP_ROM_QSTR(MP_QSTR_start), MP_ROM_PTR(&machine_rtc_start_obj) },
{ MP_ROM_QSTR(MP_QSTR_stop), MP_ROM_PTR(&machine_rtc_stop_obj) },
{ MP_ROM_QSTR(MP_QSTR_counter), MP_ROM_PTR(&machine_rtc_counter_obj) },
{ MP_ROM_QSTR(MP_QSTR_deinit), MP_ROM_PTR(&machine_rtc_deinit_obj) },
// constants
{ MP_ROM_QSTR(MP_QSTR_ONESHOT), MP_ROM_INT(RTC_MODE_ONESHOT) },
{ MP_ROM_QSTR(MP_QSTR_PERIODIC), MP_ROM_INT(RTC_MODE_PERIODIC) },
{ MP_ROM_QSTR(MP_QSTR_FREQUENCY), MP_ROM_INT(RTC_FREQUENCY) },
};
STATIC MP_DEFINE_CONST_DICT(machine_rtc_locals_dict, machine_rtc_locals_dict_table);
const mp_obj_type_t machine_rtcounter_type = {
{ &mp_type_type },
.name = MP_QSTR_RTCounter,
.print = rtc_print,
.make_new = machine_rtc_make_new,
.locals_dict = (mp_obj_dict_t*)&machine_rtc_locals_dict
};
#endif // MICROPY_PY_MACHINE_RTCOUNTER

10
ports/nrf/modules/machine/rtc.h → ports/nrf/modules/machine/rtcounter.h
View File

@ -24,13 +24,11 @@
* THE SOFTWARE.
*/
#ifndef RTC_H__
#define RTC_H__
#ifndef RTCOUNTER_H__
#define RTCOUNTER_H__
#include "hal_rtc.h"
extern const mp_obj_type_t machine_rtc_type;
extern const mp_obj_type_t machine_rtcounter_type;
void rtc_init0(void);
#endif // RTC_H__
#endif // RTCOUNTER_H__

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