284 lines
7.2 KiB
C
284 lines
7.2 KiB
C
// SPDX-License-Identifier: GPL-2.0
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// Copyright (C) 2020-2021 Martin Whitaker.
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//
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// Derived from memtest86+ pci.c:
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//
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// MemTest86+ V5.00 Specific code (GPL V2.0)
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// By Samuel DEMEULEMEESTER, sdemeule@memtest.org
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// http://www.x86-secret.com - http://www.memtest.org
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// ----------------------------------------------------
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// pci.c - MemTest-86 Version 3.2
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//
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// Released under version 2 of the Gnu Public License.
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// By Chris Brady
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#include <stdbool.h>
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#include <stdint.h>
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#include "boot.h"
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#include "bootparams.h"
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#include "cpuid.h"
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#include "io.h"
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#include "pci.h"
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#include "unistd.h"
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//------------------------------------------------------------------------------
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// Constants
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//------------------------------------------------------------------------------
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#define PCI_CLASS_DEVICE 0x0a
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#define PCI_CLASS_BRIDGE_HOST 0x0600
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//------------------------------------------------------------------------------
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// Types
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//------------------------------------------------------------------------------
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typedef enum {
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PCI_CONFIG_TYPE_NONE = 0,
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PCI_CONFIG_TYPE_1 = 1,
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PCI_CONFIG_TYPE_2 = 2
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} pci_config_type_t;
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//------------------------------------------------------------------------------
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// Private Variables
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//------------------------------------------------------------------------------
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static pci_config_type_t pci_config_type = PCI_CONFIG_TYPE_NONE;
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//------------------------------------------------------------------------------
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// Private Functions
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//------------------------------------------------------------------------------
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static bool pci_sanity_check(void)
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{
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// Do a trivial check to make certain we can see a host bridge.
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// There are reportedly some buggy chipsets from Intel and
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// Compaq where this test does not work, I will worry about
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// that when we support them.
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return pci_config_read16(0, 0, 0, PCI_CLASS_DEVICE) == PCI_CLASS_BRIDGE_HOST;
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}
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static void probe_config_type(void)
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{
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uint8_t tmpCFB;
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uint32_t tmpCF8;
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if (cpuid_info.vendor_id.str[0] == 'A' && cpuid_info.version.family == 0xf) {
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pci_config_type = PCI_CONFIG_TYPE_1;
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return;
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}
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// Check if configuration type 1 works.
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pci_config_type = PCI_CONFIG_TYPE_1;
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tmpCFB = inb(0xcfb);
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outb(0x01, 0xcfb);
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tmpCF8 = inl(0xcf8);
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outl(0x80000000, 0xcf8);
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if (inl(0xcf8) == 0x80000000 && pci_sanity_check()) {
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outl(tmpCF8, 0xcf8);
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outb(tmpCFB, 0xcfb);
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return;
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}
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outl(tmpCF8, 0xcf8);
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// Check if configuration type 2 works.
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pci_config_type = PCI_CONFIG_TYPE_2;
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outb(0x00, 0xcfb);
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outb(0x00, 0xcf8);
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outb(0x00, 0xcfa);
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if (inb(0xcf8) == 0x00 && inb(0xcfa) == 0x00 && pci_sanity_check()) {
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outb(tmpCFB, 0xcfb);
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return;
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}
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outb(tmpCFB, 0xcfb);
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// Nothing worked.
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pci_config_type = PCI_CONFIG_TYPE_NONE;
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}
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static void set_pci_config1_addr(int bus, int dev, int func, int reg)
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{
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uint32_t addr = 0x80000000
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| (reg & 0xf00) << 16
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| (bus & 0xff) << 16
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| (dev & 0x1f) << 11
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| (func & 0x07) << 8
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| (reg & 0xfc);
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outl(addr, 0xcf8);
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}
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static void set_pci_config2_bus_func(int bus, int func)
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{
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outb(0xf0 | (func & 0x7) << 1, 0xcf8);
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outb(bus, 0xcfa);
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}
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static int pci_config2_access_addr(int dev, int reg)
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{
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return 0xc000 | (dev & 0x1f) << 8 | (reg & 0xff);
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}
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//------------------------------------------------------------------------------
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// Public Functions
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//------------------------------------------------------------------------------
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void pci_init(void)
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{
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const boot_params_t *boot_params = (boot_params_t *)boot_params_addr;
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if (boot_params->efi_info.loader_signature) {
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// On UEFI systems we can assume configuration type 1.
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pci_config_type = PCI_CONFIG_TYPE_1;
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} else {
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probe_config_type();
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}
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}
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uint8_t pci_config_read8(int bus, int dev, int func, int reg)
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{
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uint8_t value;
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switch (pci_config_type) {
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case PCI_CONFIG_TYPE_1:
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set_pci_config1_addr(bus, dev, func, reg);
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return inb(0xcfc + (reg & 0x3));
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case PCI_CONFIG_TYPE_2:
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set_pci_config2_bus_func(bus, func);
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value = inb(pci_config2_access_addr(dev, reg));
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outb(0, 0xcf8);
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return value;
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default:
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return 0xFF;
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}
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}
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uint16_t pci_config_read16(int bus, int dev, int func, int reg)
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{
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uint16_t value;
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switch (pci_config_type) {
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case PCI_CONFIG_TYPE_1:
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set_pci_config1_addr(bus, dev, func, reg);
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return inw(0xcfc + (reg & 0x2));
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case PCI_CONFIG_TYPE_2:
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set_pci_config2_bus_func(bus, func);
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value = inw(pci_config2_access_addr(dev, reg));
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outb(0, 0xcf8);
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return value;
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default:
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return 0xFFFF;
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}
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}
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uint32_t pci_config_read32(int bus, int dev, int func, int reg)
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{
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uint32_t value;
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switch (pci_config_type) {
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case PCI_CONFIG_TYPE_1:
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set_pci_config1_addr(bus, dev, func, reg);
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return inl(0xcfc);
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case PCI_CONFIG_TYPE_2:
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set_pci_config2_bus_func(bus, func);
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value = inl(pci_config2_access_addr(dev, reg));
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outb(0, 0xcf8);
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return value;
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default:
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return 0xFFFFFFFF;
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}
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}
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void pci_config_write8(int bus, int dev, int func, int reg, uint8_t value)
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{
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switch (pci_config_type)
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{
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case PCI_CONFIG_TYPE_1:
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set_pci_config1_addr(bus, dev, func, reg);
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outb(value, 0xcfc + (reg & 0x3));
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break;
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case PCI_CONFIG_TYPE_2:
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set_pci_config2_bus_func(bus, func);
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outb(value, pci_config2_access_addr(dev, reg));
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outb(0, 0xcf8);
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break;
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default:
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break;
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}
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}
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void pci_config_write16(int bus, int dev, int func, int reg, uint16_t value)
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{
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switch (pci_config_type)
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{
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case PCI_CONFIG_TYPE_1:
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set_pci_config1_addr(bus, dev, func, reg);
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outw(value, 0xcfc + (reg & 0x2));
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break;
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case PCI_CONFIG_TYPE_2:
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set_pci_config2_bus_func(bus, func);
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outw(value, pci_config2_access_addr(dev, reg));
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outb(0, 0xcf8);
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break;
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default:
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break;
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}
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}
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void pci_config_write32(int bus, int dev, int func, int reg, uint32_t value)
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{
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switch (pci_config_type)
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{
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case PCI_CONFIG_TYPE_1:
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set_pci_config1_addr(bus, dev, func, reg);
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outl(value, 0xcfc);
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break;
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case PCI_CONFIG_TYPE_2:
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set_pci_config2_bus_func(bus, func);
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outl(value, pci_config2_access_addr(dev, reg));
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outb(0, 0xcf8);
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break;
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default:
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break;
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}
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}
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// -------------
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// LPC Functions
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// -------------
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void lpc_outb(uint8_t cmd, uint8_t data)
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{
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outb(cmd, 0x2E);
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usleep(100);
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outb(data, 0x2F);
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usleep(100);
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}
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uint8_t lpc_inb(uint8_t reg)
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{
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outb(reg, 0x2E);
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usleep(100);
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return inb(0x2F);
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}
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// ---------------------------------------
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// AMD System Management Network Functions
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// ---------------------------------------
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uint32_t amd_smn_read(uint32_t adr)
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{
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pci_config_write32(0, 0, 0, 0x60, adr);
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return pci_config_read32(0, 0, 0, 0x64);
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}
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void amd_smn_write(uint32_t adr, uint32_t data)
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{
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pci_config_write32(0, 0, 0, 0x60, adr);
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pci_config_write32(0, 0, 0, 0x64, data);
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}
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