178 lines
5.6 KiB
C
178 lines
5.6 KiB
C
#ifndef _SERIAL_REG_H
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#define _SERIAL_REG_H
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/**
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* \file
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*
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* Provides the TTY interface. It provides an 80x25 VT100 compatible
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* display via Serial/UART.
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*
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*//*
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* Copyright (C) 2004-2022 Sam Demeulemeester.
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*/
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#define SERIAL_DEFAULT_BAUDRATE 115200
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#define SERIAL_DEFAULT_BITS 8
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#define SERIAL_DEFAULT_PARITY 0
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#define SERIAL_PORT_0x3F8 0
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#define SERIAL_PORT_0x2F8 1
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#define SERIAL_PORT_0x3E8 2
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#define SERIAL_PORT_0x2E8 3
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static const uint16_t serial_base_ports[] = { 0x3f8, 0x2f8, 0x3e8, 0x2e8 };
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struct serial_port {
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bool enable;
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bool is_mmio;
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int parity;
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int bits;
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int baudrate;
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int reg_width;
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int refclk;
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uintptr_t base_addr;
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};
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/*
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* Definitions for VT100 commands
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*/
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#define TTY_CLEAR_SCREEN "\x1b[2J"
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#define TTY_DISABLE_CURSOR "\x1b[?25l"
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#define TTY_NORMAL "\x1b[0m"
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#define TTY_BOLD "\x1b[1m"
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#define TTY_UNDERLINE "\x1b[4m"
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#define TTY_INVERSE "\x1b[7m"
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/*
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* Definitions for the Base UART Registers
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*/
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#define UART_REF_CLK 1843200
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#define UART_RX 0 /* In: Receive buffer (DLAB=0) */
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#define UART_TX 0 /* Out: Transmit buffer (DLAB=0) */
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#define UART_DLL 0 /* Out: Divisor Latch Low (DLAB=1) */
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#define UART_DLM 1 /* Out: Divisor Latch High (DLAB=1) */
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#define UART_IER 1 /* Out: Interrupt Enable Register */
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#define UART_IIR 2 /* In: Interrupt ID Register */
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#define UART_FCR 2 /* Out: FIFO Control Register */
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#define UART_EFR 2 /* I/O: Extended Features Register */
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/* (DLAB=1, 16C660 only) */
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#define UART_LCR 3 /* Out: Line Control Register */
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#define UART_MCR 4 /* Out: Modem Control Register */
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#define UART_LSR 5 /* In: Line Status Register */
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#define UART_MSR 6 /* In: Modem Status Register */
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#define UART_SCR 7 /* I/O: Scratch Register */
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/*
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* Definitions for the Line Control Register
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*/
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#define UART_LCR_DLAB 0x80 /* Divisor latch access bit */
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#define UART_LCR_SBC 0x40 /* Set break control */
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#define UART_LCR_SPAR 0x20 /* Stick parity (?) */
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#define UART_LCR_EPAR 0x10 /* Even parity select */
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#define UART_LCR_PARITY 0x08 /* Parity Enable */
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#define UART_LCR_STOP 0x04 /* Stop bits: 0=1 stop bit, 1= 2 stop bits */
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#define UART_LCR_WLEN5 0x00 /* Wordlength: 5 bits */
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#define UART_LCR_WLEN6 0x01 /* Wordlength: 6 bits */
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#define UART_LCR_WLEN7 0x02 /* Wordlength: 7 bits */
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#define UART_LCR_WLEN8 0x03 /* Wordlength: 8 bits */
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/*
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* Definitions for the Line Status Register
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*/
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#define UART_LSR_TEMT 0x40 /* Transmitter empty */
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#define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */
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#define UART_LSR_BI 0x10 /* Break interrupt indicator */
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#define UART_LSR_FE 0x08 /* Frame error indicator */
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#define UART_LSR_PE 0x04 /* Parity error indicator */
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#define UART_LSR_OE 0x02 /* Overrun error indicator */
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#define UART_LSR_DR 0x01 /* Receiver data ready */
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/*
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* Definitions for the Interrupt Identification Register
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*/
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#define UART_IIR_NO_INT 0x01 /* No interrupts pending */
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#define UART_IIR_ID 0x06 /* Mask for the interrupt ID */
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#define UART_IIR_MSI 0x00 /* Modem status interrupt */
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#define UART_IIR_THRI 0x02 /* Transmitter holding register empty */
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#define UART_IIR_RDI 0x04 /* Receiver data interrupt */
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#define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */
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/*
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* Definitions for the Interrupt Enable Register
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*/
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#define UART_IER_MS 0x08 /* Enable Modem status interrupt */
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#define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */
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#define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */
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#define UART_IER_RDI 0x01 /* Enable receiver data interrupt */
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/*
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* Definitions for the Modem Control Register
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*/
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#define UART_MCR_LOOP 0x10 /* Enable loopback test mode */
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#define UART_MCR_OUT2 0x08 /* Out2 complement */
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#define UART_MCR_OUT1 0x04 /* Out1 complement */
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#define UART_MCR_RTS 0x02 /* RTS complement */
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#define UART_MCR_DTR 0x01 /* DTR complement */
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/*
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* Definitions for the Modem Status Register
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*/
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#define UART_MSR_DCD 0x80 /* Data Carrier Detect */
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#define UART_MSR_RI 0x40 /* Ring Indicator */
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#define UART_MSR_DSR 0x20 /* Data Set Ready */
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#define UART_MSR_CTS 0x10 /* Clear to Send */
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#define UART_MSR_DDCD 0x08 /* Delta DCD */
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#define UART_MSR_TERI 0x04 /* Trailing edge ring indicator */
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#define UART_MSR_DDSR 0x02 /* Delta DSR */
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#define UART_MSR_DCTS 0x01 /* Delta CTS */
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#define UART_MSR_ANY_DELTA 0x0F /* Any of the delta bits! */
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/*
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* Definitions for the Extended Features Register
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* (StarTech 16C660 only, when DLAB=1)
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*/
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#define UART_EFR_CTS 0x80 /* CTS flow control */
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#define UART_EFR_RTS 0x40 /* RTS flow control */
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#define UART_EFR_SCD 0x20 /* Special character detect */
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#define UART_EFR_ENI 0x10 /* Enhanced Interrupt */
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#define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
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#define tty_full_redraw() \
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tty_send_region(0, 0, 24, 79);
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#define tty_partial_redraw() \
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tty_send_region(1, 34, 5, 79); \
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tty_send_region(7, 0, 8, 79);
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#define tty_error_redraw() \
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tty_send_region(10, 0, 23, 79);
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#define tty_normal() \
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serial_echo_print(TTY_NORMAL);
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#define tty_inverse() \
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serial_echo_print(TTY_INVERSE);
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#define tty_disable_cursor() \
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serial_echo_print(TTY_DISABLE_CURSOR);
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#define tty_clear_screen() \
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serial_echo_print(TTY_CLEAR_SCREEN);
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void tty_init(void);
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void tty_print(int y, int x, const char *p);
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void tty_send_region(int start_row, int start_col, int end_row, int end_col);
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char tty_get_key(void);
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#endif /* _SERIAL_REG_H */
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