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• 9239710e60 Various Cleanup #1 Change terminology from Intel-based 'MCH' (Memory Controller Hub) to more universal 'IMC' (Integrated Memory Controller) Integrate imc_type var into imc struct. Remove previously created AMD SNM header file Sam Demeulemeester 2023-05-11 01:02:35 +0200
• 64276e407a Add IMC reading for AMD Zen4 'Raphael' AM5 CPUs Sam Demeulemeester 2023-05-11 00:29:07 +0200
• bd3991fd96 Add support for Intel Rocket Lake (Core 11th Gen) and AMD Vermeer Sam Demeulemeester 2023-05-10 22:33:40 +0200
• 0894a68a35 Add IMC Reading support for Intel ADL&RPL CPUs (Core Gen12&13) Sam Demeulemeester 2023-05-09 00:29:44 +0200
• 8e11c4b12b Change 'IMC' to 'MCH' in Makefiles to match actual mch/ directory Sam Demeulemeester 2023-05-07 23:55:14 +0200
• 7330efd772 Add IMC Read support for AMD Zen/Zen2 CPUs Sam Demeulemeester 2023-05-07 22:56:31 +0200
• a30f0a2df6 Move AMD SMN Registers & offsets to a specific header file Sam Demeulemeester 2023-05-07 22:52:55 +0200
• 5d7c78701b Fix hard-lock on Intel SNB/IVB due to wrong access type on MCHBAR pointer Sam Demeulemeester 2023-03-31 16:28:51 +0200
• 079c708c23 Add IMC read support for Intel SNB/IVB (2nd/3rd gen Core) Sam Demeulemeester 2023-03-30 18:12:21 +0200
• dde2db874a Add IMC support for Intel Core 6/7/8/9th Gen (SKL/KBL/CFL/CML) This is a bit more complex than Haswell and below because MMIO switched to 64-bit with Skylake (lot of) betatesting needed Sam Demeulemeester 2023-03-08 23:33:02 +0100
• 5ed07750ca Small typos & code fixes Sam Demeulemeester 2023-03-08 23:29:01 +0100
• e7836ee917 Statically init 'imc' struct to generate string relocation record Sam Demeulemeester 2023-03-07 21:46:47 +0100
• 12b1df7128 Better Makefile and padding fixes Sam Demeulemeester 2023-03-07 21:17:59 +0100
• 54f0f36c3e Remove old include from Makefiles Sam Demeulemeester 2023-03-07 00:18:12 +0100
• f5640a5854 Add an option to disable MCH registers polling Sam Demeulemeester 2023-03-07 00:13:52 +0100
• 8a5b85ebf4 First Intel HSW IMC implementation Sam Demeulemeester 2023-03-07 00:05:25 +0100
• af2a9c65f7 Add Intel HSW and fix new files encoding Sam Demeulemeester 2023-03-06 22:06:45 +0100
• e3e3537b25 Change directory name from 'chipsets' to 'mch' (Memory Controller Hub) Sam Demeulemeester 2023-03-06 21:55:43 +0100
• e90abd7a78 First functions skeleton for reading IMC/ECC Registers Sam Demeulemeester 2023-02-20 00:05:35 +0100
• 37799a4f87 Merge branch 'x86fr/memctrl' of https://github.com/memtest86plus/memtest86plus into x86fr/memctrl #280 Sam Demeulemeester 2023-05-12 00:31:19 +0200
• 81126354b3 Various Cleanup 2 Sam Demeulemeester 2023-05-11 23:52:37 +0200
• 0fc1b8f429 Various Cleanup #1 Change terminology from Intel-based 'MCH' (Memory Controller Hub) to more universal 'IMC' (Integrated Memory Controller) Integrate imc_type var into imc struct. Remove previously created AMD SNM header file Sam Demeulemeester 2023-05-11 01:02:35 +0200
• 715713a9fc Add IMC reading for AMD Zen4 'Raphael' AM5 CPUs Sam Demeulemeester 2023-05-11 00:29:07 +0200
• f18bb2f31c Add support for Intel Rocket Lake (Core 11th Gen) and AMD Vermeer Sam Demeulemeester 2023-05-10 22:33:40 +0200
• f61fd461f8 Add IMC Reading support for Intel ADL&RPL CPUs (Core Gen12&13) Sam Demeulemeester 2023-05-09 00:29:44 +0200
• d768f76698 Change 'IMC' to 'MCH' in Makefiles to match actual mch/ directory Sam Demeulemeester 2023-05-07 23:55:14 +0200
• f85e3a3dea Add IMC Read support for AMD Zen/Zen2 CPUs Sam Demeulemeester 2023-05-07 22:56:31 +0200
• b6bb25c464 Move AMD SMN Registers & offsets to a specific header file Sam Demeulemeester 2023-05-07 22:52:55 +0200
• cb698049f3 Fix hard-lock on Intel SNB/IVB due to wrong access type on MCHBAR pointer Sam Demeulemeester 2023-03-31 16:28:51 +0200
• e01d460287 [BROKEN] Add IMC read support for Intel SNB/IVB (2nd/3rd gen Core) Sam Demeulemeester 2023-03-30 18:12:21 +0200
• baab888552 Add IMC support for Intel Core 6/7/8/9th Gen (SKL/KBL/CFL/CML) This is a bit more complex than Haswell and below because MMIO switched to 64-bit with Skylake (lot of) betatesting needed Sam Demeulemeester 2023-03-08 23:33:02 +0100
• 6332bb5a18 Small typos & code fixes Sam Demeulemeester 2023-03-08 23:29:01 +0100
• f36c23a42f Statically init 'imc' struct to generate string relocation record Sam Demeulemeester 2023-03-07 21:46:47 +0100
• 91ca866b3d Better Makefile and padding fixes Sam Demeulemeester 2023-03-07 21:17:59 +0100
• 126d89ba4a Remove old include from Makefiles Sam Demeulemeester 2023-03-07 00:18:12 +0100
• 0a882a12b4 Add an option to disable MCH registers polling Sam Demeulemeester 2023-03-07 00:13:52 +0100
• 6c257de997 First Intel HSW IMC implementation Sam Demeulemeester 2023-03-07 00:05:25 +0100
• 75c2e10cd2 Add Intel HSW and fix new files encoding Sam Demeulemeester 2023-03-06 22:06:45 +0100
• 040c6672ff Change directory name from 'chipsets' to 'mch' (Memory Controller Hub) Sam Demeulemeester 2023-03-06 21:55:43 +0100
• 21e2dad3f3 First functions skeleton for reading IMC/ECC Registers Sam Demeulemeester 2023-02-20 00:05:35 +0100
• 52cbf821a1 Various Cleanup 2 Sam Demeulemeester 2023-05-11 23:52:37 +0200
• 36899b7997 Various Cleanup #1 Change terminology from Intel-based 'MCH' (Memory Controller Hub) to more universal 'IMC' (Integrated Memory Controller) Integrate imc_type var into imc struct. Remove previously created AMD SNM header file Sam Demeulemeester 2023-05-11 01:02:35 +0200
• ebfa7d4eeb Add IMC reading for AMD Zen4 'Raphael' AM5 CPUs Sam Demeulemeester 2023-05-11 00:29:07 +0200
• 19fb1f7a14 Add support for Intel Rocket Lake (Core 11th Gen) and AMD Vermeer Sam Demeulemeester 2023-05-10 22:33:40 +0200
• 4fa329f224 Add IMC Reading support for Intel ADL&RPL CPUs (Core Gen12&13) Sam Demeulemeester 2023-05-09 00:29:44 +0200
• f7d75c97b1 Change 'IMC' to 'MCH' in Makefiles to match actual mch/ directory Sam Demeulemeester 2023-05-07 23:55:14 +0200
• 768e874f64 Add IMC Read support for AMD Zen/Zen2 CPUs Sam Demeulemeester 2023-05-07 22:56:31 +0200
• de21442046 Move AMD SMN Registers & offsets to a specific header file Sam Demeulemeester 2023-05-07 22:52:55 +0200
• fdd0f89304 Display DDR5 SPD5 Hub memory modules temperature #304 Vladimir Rutsky 2023-05-07 21:44:13 +0200
• 5dcd424ea7 Bump version to v6.20 v6.20 Sam Demeulemeester 2023-05-07 16:55:03 +0200
• 86623ad9d1 Fix typo in README.md #300 Sam Demeulemeester 2023-05-02 01:06:23 +0200
• 866a80eebd Add support for 8/16/32-bit MMIO stride and move ref clk setting to config.c Sam Demeulemeester 2023-05-02 00:46:26 +0200
• 1f1fe5bfe8 Generalize the SMBus IO Enable quirk on all Intel ICHs This has been tested safe on every ICH since the very first one by CPU-Z. It also solves various SMBus access issues on Mobile PCHs (like #157) Sam Demeulemeester 2023-04-26 00:42:52 +0200
• bbe8b45bab Add support for MMIO UART console Sam Demeulemeester 2023-04-24 19:50:34 +0200
• 0fd2e4c37a Add support for Intel AlderLake-N CPUs Sam Demeulemeester 2023-04-24 00:29:37 +0200
• fa4e903509 Fix APIC Timer detection fail on some modern mobile/embedded PCH On some modern ULV cores (eg: Gracemont), the 2 following I/O reads to check APIC Timer working status are fused in the frontend, leading to the same value being reported twice and the code falling back to the (unusually disabled on these platforms) PIT timer. Sam Demeulemeester 2023-04-23 22:45:11 +0200
• cb37ec7d60 cpuinfo: Add support for Vortex86EX Jonathan Teh 2023-04-04 23:59:58 +0100
• 2d1d868425 Disabled clang as a compiler alongside gcc. #292 Kimon Hoffmann 2023-03-31 16:58:35 +0200
• 68a2190d4d Make sure the build workflow actually uses the chosen compiler. Kimon Hoffmann 2023-03-31 16:50:55 +0200
• 66f06915c1 Fix hard-lock on Intel SNB/IVB due to wrong access type on MCHBAR pointer Sam Demeulemeester 2023-03-31 16:28:51 +0200
• 01c76f5421 Enable using custom objcopy during build. #291 Kimon Hoffmann 2023-03-31 13:56:27 +0200
• 186fd2c194 cpuinfo: Add support for Vortex86 Jonathan Teh 2023-03-30 23:37:17 +0100
• d594da609f [BROKEN] Add IMC read support for Intel SNB/IVB (2nd/3rd gen Core) Sam Demeulemeester 2023-03-30 18:12:21 +0200
• bfbb167a72
  Bump actions/stale from 7 to 8 (#287) dependabot[bot] 2023-03-29 18:34:20 +0200
• 79bb781431 Better handling of big FAIL banned in case of errors Sam Demeulemeester 2023-03-29 18:29:59 +0200
• c6b04e5414 Display big banner only once Sam Demeulemeester 2023-03-29 17:58:12 +0200
• 65edba2942
  Bump actions/stale from 7 to 8 #287 dependabot[bot] 2023-03-23 14:08:10 +0000
• 5cbcd2046b Add 'Jade Star' & 'InnoDisk' JEDEC Manufacturers Sam Demeulemeester 2023-03-09 23:08:01 +0100
• 6fd0b3535b Makefile: Remove $AS, use $@ #281 Kyle Guinn 2023-03-08 23:10:26 -0600
• 704df3ce6e Add IMC support for Intel Core 6/7/8/9th Gen (SKL/KBL/CFL/CML) This is a bit more complex than Haswell and below because MMIO switched to 64-bit with Skylake (lot of) betatesting needed Sam Demeulemeester 2023-03-08 23:33:02 +0100
• e8bba22728 Small typos & code fixes Sam Demeulemeester 2023-03-08 23:29:01 +0100
• 82588d17e7 Statically init 'imc' struct to generate string relocation record Sam Demeulemeester 2023-03-07 21:46:47 +0100
• 21c08b0285 Better Makefile and padding fixes Sam Demeulemeester 2023-03-07 21:17:59 +0100
• bf0dae04bc Remove deprecated ubuntu-18.04 job Sam Demeulemeester 2023-03-07 00:34:31 +0100
• 30cfc9c7e6 Remove GitHub Job for Ubuntu 18.04 Sam Demeulemeester 2023-03-07 00:32:40 +0100
• 84014f9b4d Remove old include from Makefiles Sam Demeulemeester 2023-03-07 00:18:12 +0100
• 9e70e75be6 Add an option to disable MCH registers polling Sam Demeulemeester 2023-03-07 00:13:52 +0100
• e6d5b57633 First Intel HSW IMC implementation Sam Demeulemeester 2023-03-07 00:05:25 +0100
• 8c35ea1599 Add Intel HSW and fix new files encoding Sam Demeulemeester 2023-03-06 22:06:45 +0100
• 36e4b00417 Change directory name from 'chipsets' to 'mch' (Memory Controller Hub) Sam Demeulemeester 2023-03-06 21:55:43 +0100
• dcca756e48
  [cpuinfo] Fix old CPUs (P5/P6-class) name and cache info (#267) Jonathan Teh 2023-03-03 12:21:27 +0000
• e38156c40c Revert debug option #267 Sam Demeulemeester 2023-02-27 18:57:14 +0100
• 48ea1e229f Add 'Transmeta' and 'IDT' in CPU names for older CPUs Sam Demeulemeester 2023-02-26 18:37:23 +0100
• ee8d69a7d8 Add 'Intel' in CPU names for older CPUs Sam Demeulemeester 2023-02-26 17:23:59 +0100
• 30cc418639 ASM spaces to tab conversion #277 x86fr/nox2apic Sam Demeulemeester 2023-02-25 16:37:43 +0100
• c9386b9e45 Revert pre-enabled x2APIC by BIOS to xAPIC Sam Demeulemeester 2023-02-25 16:13:06 +0100
• 4be5734034 Avoid forward declaration for get_cpu_temp_type() #276 Jonathan Teh 2023-02-24 00:44:18 +0000
• 67bad70d56 temperature: Refactor to separate detection and read Jonathan Teh 2023-02-23 23:55:45 +0000
• 262aac4f85
  [SMBUS] Add support for ALi M1533/1535/1543C (#273) Sam Demeulemeester 2023-02-20 18:31:33 +0100
• e29eacbe3d [SMBUS] Add support for ALi M1533/1535/1543C #273 Sam Demeulemeester 2023-02-20 18:27:35 +0100
• 00fc1bb230 First functions skeleton for reading IMC/ECC Registers Sam Demeulemeester 2023-02-20 00:05:35 +0100
• 66bd82f12a
  [SMBus] Add support for ALi M1563 Southbridge (#272) Sam Demeulemeester 2023-02-19 17:29:56 +0100
• cf71162102 [SMBus] Add support for ALi M1563 (#126) #272 Sam Demeulemeester 2023-02-18 20:59:35 +0100
• ee0c400821 [SMBUS] Add support for VIA VT8233 Southbridge Sam Demeulemeester 2023-02-18 19:01:59 +0100
• e1fc02bfe0 [SMBUS] Add support for VIA VT8233A Southbridge Sam Demeulemeester 2023-02-18 18:58:34 +0100
• a1d046fc3a Fix a typo in README.md (serial console baud rate) Sam Demeulemeester 2023-02-18 18:51:02 +0100
• 1a38f513de
  [Temperature] Add support for CPUs with specific TjMax (#269) Sam Demeulemeester 2023-02-18 18:43:38 +0100
• e3a30e6ba2 var declaration fix #269 Sam Demeulemeester 2023-02-18 18:41:31 +0100
• 131646ddd4 [Temperature] Add support for CPUs with specific TjMax Solve an issue where reading MSR_IA32_TEMPERATURE_TARGET makes the system crash Sam Demeulemeester 2023-02-13 23:53:57 +0100
• 22663f89bb
  Add support for AMD K8 temperature reporting. (#268) Sam Demeulemeester 2023-02-13 22:29:17 +0100