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Switch Address Tests from SEQ to ONE for Faster Error Detection on HCC CPUs (#485)

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* Change Address tests from SEQ to ONE for (much) faster startup on HCC CPUs
This change will dramatically decreases the time needed to find the first fault on high core count CPUs by switching the address tests from all cores to one core.
There is probably no (or very very few) cases where a computer will be allowed to pass basic POST if all cores can't reach all areas of the RAM, so this is probably the way to go

* Removed and excluded mt8plus binary and switched Test #1 to ONE
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Sam Demeulemeester 2025-02-06 14:14:38 +01:00 committed by GitHub
parent e5c4800e58
commit 9053696e12
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2 changed files with 4 additions and 3 deletions
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1
.gitignore vendored
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@ -13,6 +13,7 @@ gdbscript
memtest_shared_debug.lds
# Binaries
mt86plus
memtest_shared
memtest_shared.bin
*.bin

6
tests/tests.c
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@ -50,9 +50,9 @@
test_pattern_t test_list[NUM_TEST_PATTERNS] = {
// ena, cpu, stgs, itrs, errs, description
{ true, SEQ, 1, 6, 0, "[Address test, walking ones, no cache] "},
{false, SEQ, 1, 6, 0, "[Address test, own address in window] "},
{ true, SEQ, 2, 6, 0, "[Address test, own address + window] "},
{ true, ONE, 1, 6, 0, "[Address test, walking ones, no cache] "},
{false, ONE, 1, 6, 0, "[Address test, own address in window] "},
{ true, ONE, 2, 6, 0, "[Address test, own address + window] "},
{ true, PAR, 1, 6, 0, "[Moving inversions, 1s & 0s] "},
{ true, PAR, 1, 3, 0, "[Moving inversions, 8 bit pattern] "},
{ true, PAR, 1, 30, 0, "[Moving inversions, random pattern] "},