mirror of
https://github.com/memtest86plus/memtest86plus
synced 2025-03-13 17:33:14 +03:00
Rework AP startup based on how it's done in Linux.
This commit is contained in:
Martin Whitaker
parent
503aea321d
commit
29b8bbece8
172
system/smp.c
172
system/smp.c
@ -19,6 +19,7 @@
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#include "bootparams.h"
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#include "efi.h"
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#include "cpuid.h"
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#include "memsize.h"
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#include "pmem.h"
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#include "string.h"
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@ -26,6 +27,8 @@
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#include "smp.h"
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#define SEQUENTIAL_AP_START 0
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//------------------------------------------------------------------------------
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// Constants
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//------------------------------------------------------------------------------
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@ -34,39 +37,11 @@
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// APIC registers
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#define APICR_ID 0x02
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#define APICR_ESR 0x28
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#define APICR_ICRLO 0x30
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#define APICR_ICRHI 0x31
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// APIC destination shorthands
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#define APIC_DEST_DEST 0
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#define APIC_DEST_LOCAL 1
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#define APIC_DEST_ALL_INC 2
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#define APIC_DEST_ALL_EXC 3
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// APIC IPI Command Register format
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#define APIC_ICRHI_RESERVED 0x00ffffff
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#define APIC_ICRHI_DEST_MASK 0xff000000
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#define APIC_ICRHI_DEST_OFFSET 24
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#define APIC_ICRLO_RESERVED 0xfff32000
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#define APIC_ICRLO_DEST_MASK 0x000c0000
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#define APIC_ICRLO_DEST_OFFSET 18
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#define APIC_ICRLO_TRIGGER_MASK 0x00008000
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#define APIC_ICRLO_TRIGGER_OFFSET 15
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#define APIC_ICRLO_LEVEL_MASK 0x00004000
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#define APIC_ICRLO_LEVEL_OFFSET 14
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#define APIC_ICRLO_STATUS_MASK 0x00001000
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#define APIC_ICRLO_STATUS_OFFSET 12
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#define APIC_ICRLO_DESTMODE_MASK 0x00000800
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#define APIC_ICRLO_DESTMODE_OFFSET 11
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#define APIC_ICRLO_DELMODE_MASK 0x00000700
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#define APIC_ICRLO_DELMODE_OFFSET 8
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#define APIC_ICRLO_VECTOR_MASK 0x000000ff
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#define APIC_ICRLO_VECTOR_OFFSET 0
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#define APIC_REG_ID 0x02
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#define APIC_REG_VER 0x03
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#define APIC_REG_ESR 0x28
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#define APIC_REG_ICRLO 0x30
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#define APIC_REG_ICRHI 0x31
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// APIC trigger types
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@ -126,7 +101,7 @@
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// Types
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//------------------------------------------------------------------------------
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typedef uint32_t apic_register_t[4];
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typedef volatile uint32_t apic_register_t[4];
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typedef struct {
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uint32_t signature; // "_MP_"
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@ -234,7 +209,7 @@ typedef struct {
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static const efi_guid_t EFI_ACPI_1_RDSP_GUID = { 0xeb9d2d30, 0x2d88, 0x11d3, {0x9a, 0x16, 0x00, 0x90, 0x27, 0x3f, 0xc1, 0x4d} };
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static const efi_guid_t EFI_ACPI_2_RDSP_GUID = { 0x8868e871, 0xe4f1, 0x11d3, {0xbc, 0x22, 0x00, 0x80, 0xc7, 0x3c, 0x88, 0x81} };
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static volatile apic_register_t *apic = NULL;
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static apic_register_t *apic = NULL;
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static uint8_t apic_id_to_cpu_num[MAX_APIC_IDS];
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@ -260,43 +235,19 @@ uintptr_t rsdp_addr = 0;
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static int my_apic_id(void)
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{
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return (apic[APICR_ID][0]) >> 24;
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return apic[APIC_REG_ID][0] >> 24;
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}
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static void apic_write(unsigned reg, uint32_t val)
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static void apic_write(int reg, uint32_t val)
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{
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apic[reg][0] = val;
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}
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static uint32_t apic_read(unsigned reg)
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static uint32_t apic_read(int reg)
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{
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return apic[reg][0];
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}
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static bool send_ipi(unsigned apic_id, unsigned trigger, unsigned level, unsigned mode, uint8_t vector)
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{
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uint32_t v;
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v = apic_read(APICR_ICRHI) & 0x00ffffff;
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apic_write(APICR_ICRHI, v | (apic_id << 24));
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v = apic_read(APICR_ICRLO) & ~0xcdfff;
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v |= APIC_DEST_DEST << APIC_ICRLO_DEST_OFFSET;
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v |= trigger << APIC_ICRLO_TRIGGER_OFFSET;
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v |= level << APIC_ICRLO_LEVEL_OFFSET;
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v |= mode << APIC_ICRLO_DELMODE_OFFSET;
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v |= vector;
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apic_write(APICR_ICRLO, v);
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for (int time = 0; time < 100; time++) {
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usleep(1);
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if (~apic_read(APICR_ICRLO) & APIC_ICRLO_STATUS_MASK) {
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return true;
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}
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}
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return false;
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}
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static int checksum(const void *data, int length)
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{
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uint8_t sum = 0;
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@ -611,30 +562,83 @@ static bool find_cpus_in_rsdp(void)
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return false;
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}
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static bool send_ipi(int apic_id, int trigger, int level, int mode, uint8_t vector, int delay_before_poll)
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{
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apic_write(APIC_REG_ICRHI, apic_id << 24);
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apic_write(APIC_REG_ICRLO, trigger << 15 | level << 14 | mode << 8 | vector);
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usleep(delay_before_poll);
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// Wait for send complete or timeout after 100ms.
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int timeout = 1000;
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while (timeout > 0) {
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bool send_pending = (apic_read(APIC_REG_ICRLO) & 0x00001000);
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if (!send_pending) {
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return true;
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}
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usleep(100);
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timeout--;
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}
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return false;
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}
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static uint32_t read_apic_esr(bool is_p5)
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{
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if (!is_p5) {
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apic_write(APIC_REG_ESR, 0);
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}
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return apic_read(APIC_REG_ESR);
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}
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static bool start_cpu(int cpu_num)
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{
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// This implements the universal algorithm described in section B.4 of the Intel Multiprocessor specification.
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// This is based on the method used in Linux 5.14. We don't support non-integrated APICs, so can simplify it a bit.
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int apic_id = cpu_num_to_apic_id[cpu_num];
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// Pulse the INIT IPI.
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apic_write(APICR_ESR, 0);
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if (!send_ipi(apic_id, APIC_TRIGGER_LEVEL, 1, APIC_DELMODE_INIT, 0)) {
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return false;
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}
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if (!send_ipi(apic_id, APIC_TRIGGER_LEVEL, 0, APIC_DELMODE_INIT, 0)) {
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return false;
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uint32_t apic_ver = apic_read(APIC_REG_VER);
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uint32_t max_lvt = (apic_ver >> 16) & 0x7f;
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bool is_p5 = (max_lvt == 3);
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bool use_long_delays = true;
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if ((cpuid_info.vendor_id.str[0] == 'G' && cpuid_info.version.family == 6) // Intel P6 or later
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|| (cpuid_info.vendor_id.str[0] == 'A' && cpuid_info.version.family >= 15)) { // AMD Hammer or later
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use_long_delays = false;
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}
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usleep(10000);
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// Clear APIC errors.
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(void)read_apic_esr(is_p5);
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// Pulse the INIT IPI.
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if (!send_ipi(apic_id, APIC_TRIGGER_LEVEL, 1, APIC_DELMODE_INIT, 0, 0)) {
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return false;
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}
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if (use_long_delays) {
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usleep(10*1000); // 10ms
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}
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if (!send_ipi(apic_id, APIC_TRIGGER_LEVEL, 0, APIC_DELMODE_INIT, 0, 0)) {
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return false;
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}
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// Send two STARTUP_IPIs.
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for (int num_sipi = 0; num_sipi < 2; num_sipi++) {
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apic_write(APICR_ESR, 0);
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if (!send_ipi(apic_id, 0, 0, APIC_DELMODE_STARTUP, AP_TRAMPOLINE_PAGE)) {
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// Clear APIC errors.
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(void)read_apic_esr(is_p5);
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// Send the STARTUP IPI.
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if (!send_ipi(apic_id, 0, 0, APIC_DELMODE_STARTUP, AP_TRAMPOLINE_PAGE, use_long_delays ? 300 : 10)) {
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return false;
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}
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// Give the other CPU some time to accept the IPI.
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usleep(use_long_delays ? 200 : 10);
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// Check the IPI was accepted.
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uint32_t status = read_apic_esr(is_p5) & 0xef;
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if (status != 0) {
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return false;
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}
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usleep(200);
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}
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return true;
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@ -658,6 +662,7 @@ void smp_init(bool smp_enable)
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if (smp_enable) {
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(void)(find_cpus_in_rsdp() || find_cpus_in_floating_mp_struct());
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}
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for (int i = 0; i < num_available_cpus; i++) {
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@ -688,9 +693,23 @@ int smp_start(cpu_state_t cpu_state[MAX_CPUS])
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return cpu_num;
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}
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}
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#if SEQUENTIAL_AP_START
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int timeout = 10000;
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while (timeout > 0) {
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if (cpu_state[cpu_num] == CPU_STATE_RUNNING) break;
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usleep(100);
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timeout--;
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}
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if (cpu_state[cpu_num] != CPU_STATE_RUNNING) {
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return cpu_num;
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}
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#endif
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}
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int timeout = 100000;
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#if SEQUENTIAL_AP_START
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return 0;
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#else
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int timeout = 10000;
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while (timeout > 0) {
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for (cpu_num = 1; cpu_num < num_available_cpus; cpu_num++) {
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if (cpu_state[cpu_num] == CPU_STATE_ENABLED) break;
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@ -698,10 +717,11 @@ int smp_start(cpu_state_t cpu_state[MAX_CPUS])
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if (cpu_num == num_available_cpus) {
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return 0;
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}
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usleep(10);
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usleep(100);
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timeout--;
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}
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return cpu_num;
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#endif
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}
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int smp_my_cpu_num(void)
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