verilog syntax: clarify that also refers to systemverilog,

...and make sure it also takes .sv files as well.

Signed-off-by: Andrew Borodin <aborodin@vmail.ru>
This commit is contained in:
Purdea Andrei 2020-06-01 22:30:02 +03:00 committed by Andrew Borodin
parent 06f2c6093e
commit f32614ae7f
2 changed files with 3 additions and 2 deletions

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@ -235,7 +235,7 @@ include cabal.syntax
file ..\*\\.(?i:n)$ Nemerle\sProgram
include nemerle.syntax
file ..\*\\.(?i:v)$ Verilog\sDevice\sDescription
file ..\*\\.(?i:(v|sv))$ Verilog/SystemVerilog\sDevice\sDescription
include verilog.syntax
file ..\*\\.(?i:hdl|vhdl?)$ VHDL\sDevice\sDescription

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@ -1,5 +1,6 @@
# This is Cooledit syntax-file for verilog
# This is Cooledit syntax-file for Verilog and SystemVerilog
# Created by Andres Farfan, <nafraf@linuxmail.org>
# Updated by Andrei Purdea, <andrei@purdea.ro>
# Feel free to copy & modify this.
# 09/2004