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https://github.com/proski/madwifi
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a71559e552
It's more reliable than a table of all device IDs. git-svn-id: http://madwifi-project.org/svn/madwifi/trunk@4014 0192ed92-7a03-0410-a25b-9323aeb14dbd
568 lines
20 KiB
C
568 lines
20 KiB
C
/*-
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* Copyright (c) 2007 Michael Taylor
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer,
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without modification.
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* 2. Redistributions in binary form must reproduce at minimum a disclaimer
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* similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
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* redistribution must be conditioned upon including a substantially
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* similar Disclaimer requirement for further binary redistribution.
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* 3. Neither the names of the above-listed copyright holders nor the names
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* of any contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* Alternatively, this software may be distributed under the terms of the
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* GNU General Public License ("GPL") version 2 as published by the Free
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* Software Foundation.
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*
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* NO WARRANTY
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
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* AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
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* OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
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* IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
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* THE POSSIBILITY OF SUCH DAMAGES.
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*
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* $Id: foo mtaylor $
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*/
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/* This file provides some wrapper functions that invoke functions in
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* if_ath_hal.h. Since all the functions in the generated file, if_ath_hal.h
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* have locks to protect them... no further locking is required in these
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* additional helper functions. Mostly these just provide a series of nicknames
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* for specific sets of arguments to HAL functions that are commonly needed. */
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#ifndef _IF_ATH_HAL_EXTENSIONS_H_
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#define _IF_ATH_HAL_EXTENSIONS_H_
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#include <linux/types.h>
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#define AR5K_PHY_AGCSIZE 0x9850
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#define AR5K_PHY_AGCSIZE_DESIRED 0x0ff00000
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#define AR5K_PHY_AGCSIZE_DESIRED_S 20
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#define AR5K_PHY_SIG 0x9858
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#define AR5K_PHY_SIG_FIRSTEP 0x0003f000
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#define AR5K_PHY_SIG_FIRSTEP_S 12
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#define AR5K_PHY_SIG_FIRPWR 0x03fc0000
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#define AR5K_PHY_SIG_FIRPWR_S 18
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#define AR5K_PHY_AGCCOARSE 0x985c
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#define AR5K_PHY_AGCCOARSE_LO 0x00007f80
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#define AR5K_PHY_AGCCOARSE_LO_S 7
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#define AR5K_PHY_AGCCOARSE_HI 0x003f8000
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#define AR5K_PHY_AGCCOARSE_HI_S 15
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#define AR5K_PHY_WEAK_OFDM_HIGH 0x9868
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#define AR5K_PHY_WEAK_OFDM_HIGH_M1 0x00fe0000
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#define AR5K_PHY_WEAK_OFDM_HIGH_M1_S 17
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#define AR5K_PHY_WEAK_OFDM_HIGH_M2 0x7f000000
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#define AR5K_PHY_WEAK_OFDM_HIGH_M2_S 24
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#define AR5K_PHY_WEAK_OFDM_HIGH_M2_COUNT 0x0000001f
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#define AR5K_PHY_WEAK_OFDM_HIGH_M2_COUNT_S 0
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#define AR5K_PHY_WEAK_OFDM_HIGH_M1_OFF 127
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#define AR5K_PHY_WEAK_OFDM_HIGH_M1_ON 77
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#define AR5K_PHY_WEAK_OFDM_HIGH_M2_OFF 127
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#define AR5K_PHY_WEAK_OFDM_HIGH_M2_ON 64
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#define AR5K_PHY_WEAK_OFDM_HIGH_M2_COUNT_OFF 31
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#define AR5K_PHY_WEAK_OFDM_HIGH_M2_COUNT_ON 16
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/* NB: comparing defaults for these registers vs. patent, it appears this
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* is baseband processor stuff from table 2. */
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#define AR5K_PHY_WEAK_OFDM_LOW 0x986c
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#define AR5K_PHY_WEAK_OFDM_LOW_M1 0x001fc000
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#define AR5K_PHY_WEAK_OFDM_LOW_M1_S 14
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#define AR5K_PHY_WEAK_OFDM_LOW_M2 0x0fe00000
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#define AR5K_PHY_WEAK_OFDM_LOW_M2_S 21
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#define AR5K_PHY_WEAK_OFDM_LOW_M2_COUNT 0x00003f00
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#define AR5K_PHY_WEAK_OFDM_LOW_M2_COUNT_S 8
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#define AR5K_PHY_WEAK_OFDM_LOW_SELFCOR 0x00000001
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#define AR5K_PHY_WEAK_OFDM_LOW_SELFCOR_S 0
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#define AR5K_PHY_WEAK_OFDM_LOW_M1_OFF 127
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#define AR5K_PHY_WEAK_OFDM_LOW_M1_ON 50
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#define AR5K_PHY_WEAK_OFDM_LOW_M2_OFF 127
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#define AR5K_PHY_WEAK_OFDM_LOW_M2_ON 40
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#define AR5K_PHY_WEAK_OFDM_LOW_M2_COUNT_OFF 63
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#define AR5K_PHY_WEAK_OFDM_LOW_M2_COUNT_ON 48
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#define AR5K_PHY_WEAK_OFDM_LOW_SELFCOR_OFF 0
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#define AR5K_PHY_WEAK_OFDM_LOW_SELFCOR_ON 1
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#define AR5K_PHY_SPUR 0x9924
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#define AR5K_PHY_SPUR_THRESH 0x000000fe
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#define AR5K_PHY_SPUR_THRESH_S 1
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#define AR5K_PHY_WEAK_CCK 0xa208
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#define AR5K_PHY_WEAK_CCK_THRESH 0x0000000f
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#define AR5K_PHY_WEAK_CCK_THRESH_S 0
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#define AR5K_PHY_WEAK_CCK_THRESH_ON 6
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#define AR5K_PHY_WEAK_CCK_THRESH_OFF 8
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#define DEFAULT_AR5K_PHY_AGCSIZE_DESIRED -34
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#define DEFAULT_AR5K_PHY_AGCCOARSE_HI -18
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#define DEFAULT_AR5K_PHY_AGCCOARSE_LO -52
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#define DEFAULT_AR5K_PHY_SIG_FIRPWR -70
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/* NB: I can never make up my mind which is right. */
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#define DEFAULT_ENABLE_AR5K_PHY_WEAK_OFDM_11BG 1
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#define DEFAULT_ENABLE_AR5K_PHY_WEAK_OFDM_11A 1
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#define IS_CHAN_ANY(ah) \
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(((struct ieee80211com *)ah->ah_sc)->ic_bsschan == IEEE80211_CHAN_ANYC)
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#define IS_BG_OR_ANY(ah) \
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(IS_CHAN_ANY(ah) || (!(ieee80211_chan2mode(((struct ieee80211com *)ah->ah_sc)->ic_bsschan) & \
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(IEEE80211_MODE_11A | IEEE80211_MODE_TURBO_A))))
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#define DEFAULT_ENABLE_AR5K_PHY_WEAK_OFDM (IS_BG_OR_ANY(ah) ? \
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DEFAULT_ENABLE_AR5K_PHY_WEAK_OFDM_11BG : \
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DEFAULT_ENABLE_AR5K_PHY_WEAK_OFDM_11A \
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)
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#define DEFAULT_ENABLE_AR5K_PHY_WEAK_OFDM_HIGH DEFAULT_ENABLE_AR5K_PHY_WEAK_OFDM
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#define DEFAULT_ENABLE_AR5K_PHY_WEAK_OFDM_LOW DEFAULT_ENABLE_AR5K_PHY_WEAK_OFDM
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#define DEFAULT_ENABLE_AR5K_PHY_WEAK_CCK 0
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#define DEFAULT_AR5K_PHY_SPUR_THRESH 2
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#define DEFAULT_AR5K_PHY_SIG_FIRSTEP 0
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/*
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* Transmit configuration register
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*/
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#define AR5K_TXCFG 0x0030 /* Register Address */
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#define AR5K_TXCFG_SDMAMR 0x00000007 /* DMA size */
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#define AR5K_TXCFG_SDMAMR_S 0
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/*
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* Receive configuration register
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*/
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#define AR5K_RXCFG 0x0034 /* Register Address */
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#define AR5K_RXCFG_SDMAMW 0x00000007 /* DMA size */
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#define AR5K_RXCFG_SDMAMW_S 0
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/*
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* Second station id register (MAC address in upper 16 bits)
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*/
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#define AR5K_STA_ID1 0x8004 /* Register Address */
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#define AR5K_STA_ID1_AP 0x00010000 /* Set AP mode */
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#define AR5K_STA_ID1_ADHOC 0x00020000 /* Set Ad-Hoc mode */
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#define AR5K_STA_ID1_PWR_SV 0x00040000 /* Power save reporting (?) */
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#define AR5K_STA_ID1_NO_KEYSRCH 0x00080000 /* No key search */
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#define AR5K_STA_ID1_NO_PSPOLL 0x00100000 /* No power save polling [5210] */
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#define AR5K_STA_ID1_PCF_5211 0x00100000 /* Enable PCF on [5211+] */
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#define AR5K_STA_ID1_PCF_5210 0x00200000 /* Enable PCF on [5210] */
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#define AR5K_STA_ID1_PCF (ah->ah_version == AR5K_AR5210 ? \
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AR5K_STA_ID1_PCF_5210 : AR5K_STA_ID1_PCF_5211)
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#define AR5K_STA_ID1_DEFAULT_ANTENNA 0x00200000 /* Use default antenna */
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#define AR5K_STA_ID1_DESC_ANTENNA 0x00400000 /* Update antenna from descriptor */
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#define AR5K_STA_ID1_RTS_DEF_ANTENNA 0x00800000 /* Use default antenna for RTS (?) */
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#define AR5K_STA_ID1_ACKCTS_6MB 0x01000000 /* Use 6Mbit/s for ACK/CTS (?) */
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#define AR5K_STA_ID1_BASE_RATE_11B 0x02000000 /* Use 11b base rate (for ACK/CTS ?) [5211+] */
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/*
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* PCU beacon control register
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*/
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#define AR5K_BEACON_5210 0x8024
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#define AR5K_BEACON_5211 0x8020
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/*
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* Next beacon time register
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*/
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#define AR5K_TIMER0_5210 0x802c
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#define AR5K_TIMER0_5211 0x8028
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/*
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* Next DMA beacon alert register
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*/
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#define AR5K_TIMER1_5210 0x8030
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#define AR5K_TIMER1_5211 0x802c
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/*
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* Next software beacon alert register
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*/
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#define AR5K_TIMER2_5210 0x8034
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#define AR5K_TIMER2_5211 0x8030
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/*
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* Next ATIM window time register
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*/
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#define AR5K_TIMER3_5210 0x8038
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#define AR5K_TIMER3_5211 0x8034
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enum ath5k_srev_type {
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AR5K_VERSION_VER,
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AR5K_VERSION_RAD,
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};
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struct ath5k_srev_name {
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const char *sr_name;
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enum ath5k_srev_type sr_type;
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u_int sr_val;
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};
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#define AR5K_SREV_UNKNOWN 0xffff
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#define AR5K_SREV_VER_AR5210 0x00
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#define AR5K_SREV_VER_AR5311 0x10
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#define AR5K_SREV_VER_AR5311A 0x20
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#define AR5K_SREV_VER_AR5311B 0x30
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#define AR5K_SREV_VER_AR5211 0x40
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#define AR5K_SREV_VER_AR5212 0x50
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#define AR5K_SREV_VER_AR5213 0x55
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#define AR5K_SREV_VER_AR5213A 0x59
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#define AR5K_SREV_VER_AR2413 0x78
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#define AR5K_SREV_VER_AR2414 0x79
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#define AR5K_SREV_VER_AR2424 0xa0 /* PCI-E */
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#define AR5K_SREV_VER_AR5424 0xa3 /* PCI-E */
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#define AR5K_SREV_VER_AR5413 0xa4
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#define AR5K_SREV_VER_AR5414 0xa5
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#define AR5K_SREV_VER_AR5416 0xc0 /* PCI-E */
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#define AR5K_SREV_VER_AR5418 0xca /* PCI-E */
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#define AR5K_SREV_VER_AR2425 0xe2 /* PCI-E */
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#define AR5K_SREV_RAD_5110 0x00
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#define AR5K_SREV_RAD_5111 0x10
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#define AR5K_SREV_RAD_5111A 0x15
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#define AR5K_SREV_RAD_2111 0x20
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#define AR5K_SREV_RAD_5112 0x30
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#define AR5K_SREV_RAD_5112A 0x35
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#define AR5K_SREV_RAD_2112 0x40
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#define AR5K_SREV_RAD_2112A 0x45
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#define AR5K_SREV_RAD_SC0 0x56 /* Found on 2413/2414 */
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#define AR5K_SREV_RAD_SC1 0x63 /* Found on 5413/5414 */
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#define AR5K_SREV_RAD_SC2 0xa2 /* Found on 2424-5/5424 */
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#define AR5K_SREV_RAD_5133 0xc0 /* MIMO found on 5418 */
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#define ATH_SREV_FROM_AH(_ah) ((_ah)->ah_macVersion << 4 | (_ah)->ah_macRev)
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/*
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* DMA size definitions (2^(n+2))
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*/
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enum ath5k_dmasize {
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AR5K_DMASIZE_4B = 0,
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AR5K_DMASIZE_8B,
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AR5K_DMASIZE_16B,
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AR5K_DMASIZE_32B,
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AR5K_DMASIZE_64B,
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AR5K_DMASIZE_128B,
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AR5K_DMASIZE_256B,
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AR5K_DMASIZE_512B
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};
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int ath_set_ack_bitrate(struct ath_softc *sc, int);
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int ar_device(struct ath_softc *sc);
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const char * ath5k_chip_name(enum ath5k_srev_type type, u_int16_t val);
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void ath_hw_beacon_stop(struct ath_softc *sc);
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int ath_hw_check_atim(struct ath_softc *sc, int window, int intval);
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static inline unsigned long field_width(unsigned long mask, unsigned long shift)
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{
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unsigned long r = 0;
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unsigned long x = mask >> shift;
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if ( 0 == mask ) return 0;
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#if BITS_PER_LONG >= 64
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if ( x & (~0UL<<32) ) { x >>= 32; r += 32; }
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#endif
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if ( x & 0xffff0000 ) { x >>= 16; r += 16; }
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if ( x & 0x0000ff00 ) { x >>= 8; r += 8; }
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if ( x & 0x000000f0 ) { x >>= 4; r += 4; }
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if ( x & 0x0000000c ) { x >>= 2; r += 2; }
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if ( x & 0x00000002 ) { r += 1; }
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return r+1;
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}
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static inline u_int32_t get_field(struct ath_hal *ah, u_int32_t reg, u_int32_t mask, u_int32_t shift, int is_signed) {
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unsigned long x = ((OS_REG_READ(ah, reg) & mask) >> shift);
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if (is_signed) {
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unsigned long c =(-1) << (field_width(mask, shift)-1);
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return (x + c) ^ c;
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}
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return x;
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}
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static inline void set_field(struct ath_hal *ah, u_int32_t reg, u_int32_t mask, u_int32_t shift, u_int32_t value) {
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OS_REG_WRITE(ah, reg,
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(OS_REG_READ(ah, reg) & ~mask) |
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((value << shift) & mask));
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}
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static inline u_int32_t field_eq(struct ath_hal *ah, u_int32_t reg,
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u_int32_t mask, u_int32_t shift,
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u_int32_t value, int is_signed) {
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return (get_field(ah, reg, mask, shift, is_signed) & (mask >> shift)) ==
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(value & (mask >> shift));
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}
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static inline void override_warning(struct ath_hal *ah, const char *name,
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u_int32_t reg, u_int32_t mask,
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u_int32_t shift, u_int32_t expected, int is_signed) {
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if (!field_eq(ah, reg, mask, shift, expected, is_signed))
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printk("%s: Correcting 0x%04x[%s] from 0x%x (%d) to 0x%x (%d).\n",
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SC_DEV_NAME(ah->ah_sc),
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reg,
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name,
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(get_field(ah, reg, mask, shift, is_signed) & (mask >> shift)),
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get_field(ah, reg, mask, shift, is_signed),
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(expected & (mask >> shift)), /* not sign extended */
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expected);
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#if 0 /* NB: For checking to see if HAL is fixed or not */
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else {
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printk("%s: Keeping 0x%04x[%s] - 0x%x (%d).\n",
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SC_DEV_NAME(ah->ah_sc),
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reg,
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name,
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(get_field(ah, reg, mask, shift, is_signed) & (mask >> shift)),
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get_field(ah, reg, mask, shift, is_signed));
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}
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#endif
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}
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static inline void verification_warning(struct ath_hal *ah, const char *name,
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u_int32_t reg, u_int32_t mask,
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u_int32_t shift, u_int32_t expected, int is_signed) {
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int ret = field_eq(ah, reg, mask, shift, expected, is_signed);
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if (!ret) {
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printk("%s: %s verification of %s default value "
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"[found=0x%x (%d) expected=0x%x (%d)].\n",
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SC_DEV_NAME(ah->ah_sc),
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(ret ? "PASSED" : "FAILED"),
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name,
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(get_field(ah, reg, mask, shift, is_signed) & (mask >> shift)),
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get_field(ah, reg, mask, shift, is_signed),
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(expected & (mask >> shift)), /* not sign extended */
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expected);
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ath_hal_print_decoded_register(ah, NULL, reg,
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OS_REG_READ(ah, reg), OS_REG_READ(ah, reg), 0);
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}
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}
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#define GET_FIELD(ah, __reg, __mask, __signed) \
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get_field(ah, __reg, __mask, __mask ## _S, __signed)
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#define SET_FIELD(ah, __reg, __mask, __value) \
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set_field(ah, __reg, __mask, __mask ## _S, __value);
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#define FIELD_EQ(ah, __reg, __mask, __value, __signed) \
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field_eq(ah, __reg, __mask, __mask ## _S, __value, __signed)
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#if 0 /* NB: These are working at this point, and HAL tweaks them a lot */
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#define OVERRIDE_WARNING(ah, __reg, __mask, __expected, __signed) \
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override_warning(ah, #__mask, __reg, __mask, __mask ## _S, __expected, __signed)
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#else
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#define OVERRIDE_WARNING(ah, __reg, __mask, __expected, __signed)
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#endif
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#define VERIFICATION_WARNING(ah, __reg, __mask, __signed) \
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verification_warning(ah, #__mask, __reg, __mask, __mask ## _S, DEFAULT_ ## __mask, __signed)
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#define VERIFICATION_WARNING_SW(ah, __reg, __mask, __signed) \
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verification_warning(ah, #__mask, __reg, __mask, __mask ## _S, DEFAULT_ENABLE_ ## __reg ? __mask ## _ON : __mask ## _OFF, __signed)
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static inline void ath_hal_set_noise_immunity(struct ath_hal *ah,
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int agc_desired_size,
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int agc_coarse_hi,
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int agc_coarse_lo,
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int sig_firpwr)
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{
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ATH_HAL_LOCK_IRQ(ah->ah_sc);
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ath_hal_set_function(__func__);
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ath_hal_set_device(SC_DEV_NAME(ah->ah_sc));
|
|
|
|
#if 0 /* NB: These are working at this point, and HAL tweaks them a lot */
|
|
OVERRIDE_WARNING(ah, AR5K_PHY_AGCSIZE, AR5K_PHY_AGCSIZE_DESIRED, agc_desired_size, 1);
|
|
OVERRIDE_WARNING(ah, AR5K_PHY_AGCCOARSE, AR5K_PHY_AGCCOARSE_LO, agc_coarse_lo, 1);
|
|
OVERRIDE_WARNING(ah, AR5K_PHY_AGCCOARSE, AR5K_PHY_AGCCOARSE_HI, agc_coarse_hi, 1);
|
|
OVERRIDE_WARNING(ah, AR5K_PHY_SIG, AR5K_PHY_SIG_FIRPWR, sig_firpwr, 1);
|
|
#endif
|
|
|
|
SET_FIELD(ah, AR5K_PHY_AGCSIZE, AR5K_PHY_AGCSIZE_DESIRED, agc_desired_size);
|
|
SET_FIELD(ah, AR5K_PHY_AGCCOARSE, AR5K_PHY_AGCCOARSE_LO, agc_coarse_lo);
|
|
SET_FIELD(ah, AR5K_PHY_AGCCOARSE, AR5K_PHY_AGCCOARSE_HI, agc_coarse_hi);
|
|
SET_FIELD(ah, AR5K_PHY_SIG, AR5K_PHY_SIG_FIRPWR, sig_firpwr);
|
|
|
|
ath_hal_set_function(NULL);
|
|
ath_hal_set_device(NULL);
|
|
ATH_HAL_UNLOCK_IRQ(ah->ah_sc);
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|
}
|
|
|
|
static inline void ath_hal_set_ofdm_weak_det(struct ath_hal *ah,
|
|
int low_m1, int low_m2, int low_m2_count, int low_self_corr,
|
|
int high_m1, int high_m2, int high_m2_count)
|
|
{
|
|
ATH_HAL_LOCK_IRQ(ah->ah_sc);
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|
ath_hal_set_function(__func__);
|
|
ath_hal_set_device(SC_DEV_NAME(ah->ah_sc));
|
|
|
|
OVERRIDE_WARNING(ah, AR5K_PHY_WEAK_OFDM_LOW, AR5K_PHY_WEAK_OFDM_LOW_M1, low_m1, 0);
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|
OVERRIDE_WARNING(ah, AR5K_PHY_WEAK_OFDM_LOW, AR5K_PHY_WEAK_OFDM_LOW_M2, low_m2, 0);
|
|
OVERRIDE_WARNING(ah, AR5K_PHY_WEAK_OFDM_LOW, AR5K_PHY_WEAK_OFDM_LOW_M2_COUNT, low_m2_count, 0);
|
|
OVERRIDE_WARNING(ah, AR5K_PHY_WEAK_OFDM_LOW, AR5K_PHY_WEAK_OFDM_LOW_SELFCOR, low_self_corr, 0);
|
|
OVERRIDE_WARNING(ah, AR5K_PHY_WEAK_OFDM_HIGH, AR5K_PHY_WEAK_OFDM_HIGH_M1, high_m1, 0);
|
|
OVERRIDE_WARNING(ah, AR5K_PHY_WEAK_OFDM_HIGH, AR5K_PHY_WEAK_OFDM_HIGH_M2, high_m2, 0);
|
|
OVERRIDE_WARNING(ah, AR5K_PHY_WEAK_OFDM_HIGH, AR5K_PHY_WEAK_OFDM_HIGH_M2_COUNT, high_m2_count, 0);
|
|
|
|
SET_FIELD(ah, AR5K_PHY_WEAK_OFDM_LOW, AR5K_PHY_WEAK_OFDM_LOW_M1, low_m1);
|
|
SET_FIELD(ah, AR5K_PHY_WEAK_OFDM_LOW, AR5K_PHY_WEAK_OFDM_LOW_M2, low_m2);
|
|
SET_FIELD(ah, AR5K_PHY_WEAK_OFDM_LOW, AR5K_PHY_WEAK_OFDM_LOW_M2_COUNT, low_m2_count);
|
|
SET_FIELD(ah, AR5K_PHY_WEAK_OFDM_LOW, AR5K_PHY_WEAK_OFDM_LOW_SELFCOR, low_self_corr);
|
|
SET_FIELD(ah, AR5K_PHY_WEAK_OFDM_HIGH, AR5K_PHY_WEAK_OFDM_HIGH_M1, high_m1);
|
|
SET_FIELD(ah, AR5K_PHY_WEAK_OFDM_HIGH, AR5K_PHY_WEAK_OFDM_HIGH_M2, high_m2);
|
|
SET_FIELD(ah, AR5K_PHY_WEAK_OFDM_HIGH, AR5K_PHY_WEAK_OFDM_HIGH_M2_COUNT, high_m2_count);
|
|
|
|
ath_hal_set_function(NULL);
|
|
ath_hal_set_device(NULL);
|
|
ATH_HAL_UNLOCK_IRQ(ah->ah_sc);
|
|
}
|
|
|
|
static inline void ath_hal_set_cck_weak_det(struct ath_hal *ah, int thresh)
|
|
{
|
|
ATH_HAL_LOCK_IRQ(ah->ah_sc);
|
|
ath_hal_set_function(__func__);
|
|
ath_hal_set_device(SC_DEV_NAME(ah->ah_sc));
|
|
|
|
OVERRIDE_WARNING(ah, AR5K_PHY_WEAK_CCK, AR5K_PHY_WEAK_CCK_THRESH, thresh, 0);
|
|
|
|
SET_FIELD(ah, AR5K_PHY_WEAK_CCK, AR5K_PHY_WEAK_CCK_THRESH, thresh);
|
|
|
|
ath_hal_set_function(NULL);
|
|
ath_hal_set_device(NULL);
|
|
ATH_HAL_UNLOCK_IRQ(ah->ah_sc);
|
|
}
|
|
|
|
static inline void ath_hal_set_sig_firstep(struct ath_hal *ah, int firstep)
|
|
{
|
|
ATH_HAL_LOCK_IRQ(ah->ah_sc);
|
|
ath_hal_set_function(__func__);
|
|
ath_hal_set_device(SC_DEV_NAME(ah->ah_sc));
|
|
|
|
OVERRIDE_WARNING(ah, AR5K_PHY_SIG, AR5K_PHY_SIG_FIRSTEP, firstep, 0);
|
|
|
|
SET_FIELD(ah, AR5K_PHY_SIG, AR5K_PHY_SIG_FIRSTEP, firstep);
|
|
|
|
ath_hal_set_function(NULL);
|
|
ath_hal_set_device(NULL);
|
|
ATH_HAL_UNLOCK_IRQ(ah->ah_sc);
|
|
}
|
|
|
|
static inline void ath_hal_set_spur_immunity(struct ath_hal *ah, int thresh)
|
|
{
|
|
ATH_HAL_LOCK_IRQ(ah->ah_sc);
|
|
ath_hal_set_function(__func__);
|
|
ath_hal_set_device(SC_DEV_NAME(ah->ah_sc));
|
|
|
|
OVERRIDE_WARNING(ah, AR5K_PHY_SPUR, AR5K_PHY_SPUR_THRESH, thresh, 0);
|
|
|
|
SET_FIELD(ah, AR5K_PHY_SPUR, AR5K_PHY_SPUR_THRESH, thresh);
|
|
|
|
ath_hal_set_function(NULL);
|
|
ath_hal_set_device(NULL);
|
|
ATH_HAL_UNLOCK_IRQ(ah->ah_sc);
|
|
}
|
|
|
|
static inline void ath_hal_restore_default_noise_immunity(struct ath_hal *ah) {
|
|
|
|
ath_hal_set_noise_immunity(ah,
|
|
DEFAULT_AR5K_PHY_AGCSIZE_DESIRED,
|
|
DEFAULT_AR5K_PHY_AGCCOARSE_HI,
|
|
DEFAULT_AR5K_PHY_AGCCOARSE_LO,
|
|
DEFAULT_AR5K_PHY_SIG_FIRPWR);
|
|
}
|
|
|
|
static inline void ath_hal_enable_ofdm_weak_det(struct ath_hal *ah, int enable) {
|
|
if (enable)
|
|
ath_hal_set_ofdm_weak_det(ah,
|
|
AR5K_PHY_WEAK_OFDM_LOW_M1_ON,
|
|
AR5K_PHY_WEAK_OFDM_LOW_M2_ON,
|
|
AR5K_PHY_WEAK_OFDM_LOW_M2_COUNT_ON,
|
|
AR5K_PHY_WEAK_OFDM_LOW_SELFCOR_ON,
|
|
AR5K_PHY_WEAK_OFDM_HIGH_M1_ON,
|
|
AR5K_PHY_WEAK_OFDM_HIGH_M2_ON,
|
|
AR5K_PHY_WEAK_OFDM_HIGH_M2_COUNT_ON);
|
|
else
|
|
ath_hal_set_ofdm_weak_det(ah,
|
|
AR5K_PHY_WEAK_OFDM_LOW_M1_OFF,
|
|
AR5K_PHY_WEAK_OFDM_LOW_M2_OFF,
|
|
AR5K_PHY_WEAK_OFDM_LOW_M2_COUNT_OFF,
|
|
AR5K_PHY_WEAK_OFDM_LOW_SELFCOR_OFF,
|
|
AR5K_PHY_WEAK_OFDM_HIGH_M1_OFF,
|
|
AR5K_PHY_WEAK_OFDM_HIGH_M2_OFF,
|
|
AR5K_PHY_WEAK_OFDM_HIGH_M2_COUNT_OFF);
|
|
}
|
|
|
|
static inline void ath_hal_enable_cck_weak_det(struct ath_hal *ah, int enable) {
|
|
ath_hal_set_cck_weak_det(ah, enable
|
|
? AR5K_PHY_WEAK_CCK_THRESH_ON
|
|
: AR5K_PHY_WEAK_CCK_THRESH_OFF);
|
|
}
|
|
|
|
static inline void ath_hal_restore_default_ofdm_weak_det(struct ath_hal *ah) {
|
|
ath_hal_enable_ofdm_weak_det(ah, DEFAULT_ENABLE_AR5K_PHY_WEAK_OFDM);
|
|
}
|
|
|
|
static inline void ath_hal_restore_default_cck_weak_det(struct ath_hal *ah) {
|
|
ath_hal_enable_cck_weak_det(ah, DEFAULT_ENABLE_AR5K_PHY_WEAK_CCK);
|
|
}
|
|
|
|
static inline void ath_hal_restore_default_sig_firstep(struct ath_hal *ah) {
|
|
|
|
ath_hal_set_sig_firstep(ah,
|
|
DEFAULT_AR5K_PHY_SIG_FIRSTEP);
|
|
}
|
|
|
|
static inline void ath_hal_restore_default_spur_immunity(struct ath_hal *ah) {
|
|
|
|
ath_hal_set_spur_immunity(ah,
|
|
DEFAULT_AR5K_PHY_SPUR_THRESH);
|
|
}
|
|
|
|
static inline void ath_hal_restore_default_intmit(struct ath_hal *ah) {
|
|
ath_hal_restore_default_noise_immunity(ah);
|
|
ath_hal_restore_default_ofdm_weak_det(ah);
|
|
ath_hal_restore_default_cck_weak_det(ah);
|
|
ath_hal_restore_default_sig_firstep(ah);
|
|
ath_hal_restore_default_spur_immunity(ah);
|
|
|
|
}
|
|
|
|
static inline void ath_hal_verify_default_intmit(struct ath_hal *ah) {
|
|
/* Just a list of all the fields above, for sanity checks... */
|
|
VERIFICATION_WARNING(ah, AR5K_PHY_AGCSIZE, AR5K_PHY_AGCSIZE_DESIRED, 1);
|
|
VERIFICATION_WARNING(ah, AR5K_PHY_AGCCOARSE, AR5K_PHY_AGCCOARSE_LO, 1);
|
|
VERIFICATION_WARNING(ah, AR5K_PHY_AGCCOARSE, AR5K_PHY_AGCCOARSE_HI, 1);
|
|
VERIFICATION_WARNING(ah, AR5K_PHY_SIG, AR5K_PHY_SIG_FIRPWR, 1);
|
|
VERIFICATION_WARNING_SW(ah, AR5K_PHY_WEAK_OFDM_LOW, AR5K_PHY_WEAK_OFDM_LOW_M1, 0);
|
|
VERIFICATION_WARNING_SW(ah, AR5K_PHY_WEAK_OFDM_LOW, AR5K_PHY_WEAK_OFDM_LOW_M2, 0);
|
|
VERIFICATION_WARNING_SW(ah, AR5K_PHY_WEAK_OFDM_LOW, AR5K_PHY_WEAK_OFDM_LOW_M2_COUNT, 0);
|
|
VERIFICATION_WARNING_SW(ah, AR5K_PHY_WEAK_OFDM_LOW, AR5K_PHY_WEAK_OFDM_LOW_SELFCOR, 0);
|
|
VERIFICATION_WARNING_SW(ah, AR5K_PHY_WEAK_OFDM_HIGH, AR5K_PHY_WEAK_OFDM_HIGH_M1, 0);
|
|
VERIFICATION_WARNING_SW(ah, AR5K_PHY_WEAK_OFDM_HIGH, AR5K_PHY_WEAK_OFDM_HIGH_M2, 0);
|
|
VERIFICATION_WARNING_SW(ah, AR5K_PHY_WEAK_OFDM_HIGH, AR5K_PHY_WEAK_OFDM_HIGH_M2_COUNT, 0);
|
|
VERIFICATION_WARNING_SW(ah, AR5K_PHY_WEAK_CCK, AR5K_PHY_WEAK_CCK_THRESH, 0);
|
|
VERIFICATION_WARNING(ah, AR5K_PHY_SIG, AR5K_PHY_SIG_FIRSTEP, 0);
|
|
VERIFICATION_WARNING(ah, AR5K_PHY_SPUR, AR5K_PHY_SPUR_THRESH, 0);
|
|
}
|
|
|
|
static inline void ath_hal_set_dmasize_pcie(struct ath_hal *ah) {
|
|
SET_FIELD(ah, AR5K_TXCFG, AR5K_TXCFG_SDMAMR, AR5K_DMASIZE_128B);
|
|
SET_FIELD(ah, AR5K_RXCFG, AR5K_RXCFG_SDMAMW, AR5K_DMASIZE_128B);
|
|
}
|
|
|
|
#endif /* _IF_ATH_HAL_EXTENSIONS_H_ */
|