mirror of
https://github.com/proski/madwifi
synced 2024-11-29 17:53:12 +03:00
c0c7d05e2f
It strikes me that we should always reset the hardware through a common function, though. Ticket: http://madwifi.org/ticket/705 Original Patch: Signed-off-by: Tjalling Hattink <tjalling.hattink@ti-wmc.nl> git-svn-id: http://madwifi-project.org/svn/madwifi/trunk@2843 0192ed92-7a03-0410-a25b-9323aeb14dbd
758 lines
28 KiB
C
758 lines
28 KiB
C
/*-
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* Copyright (c) 2002-2005 Sam Leffler, Errno Consulting
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer,
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without modification.
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* 2. Redistributions in binary form must reproduce at minimum a disclaimer
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* similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
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* redistribution must be conditioned upon including a substantially
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* similar Disclaimer requirement for further binary redistribution.
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* 3. Neither the names of the above-listed copyright holders nor the names
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* of any contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* Alternatively, this software may be distributed under the terms of the
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* GNU General Public License ("GPL") version 2 as published by the Free
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* Software Foundation.
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*
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* NO WARRANTY
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
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* AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
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* OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
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* IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
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* THE POSSIBILITY OF SUCH DAMAGES.
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*
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* $Id$
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*/
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/*
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* Defintions for the Atheros Wireless LAN controller driver.
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*/
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#ifndef _DEV_ATH_ATHVAR_H
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#define _DEV_ATH_ATHVAR_H
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#include "ah.h"
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#include "ah_desc.h"
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#include "ah_os.h"
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#include "if_athioctl.h"
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#include "net80211/ieee80211.h" /* XXX for WME_NUM_AC */
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#include <asm/io.h>
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#include <linux/list.h>
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/*
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* Deduce if tasklets are available. If not then
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* fall back to using the immediate work queue.
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*/
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#include <linux/interrupt.h>
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#ifdef DECLARE_TASKLET /* native tasklets */
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#define ATH_TQ_STRUCT tasklet_struct
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#define ATH_INIT_TQUEUE(a,b,c) tasklet_init((a), (b), (unsigned long)(c))
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#define ATH_SCHEDULE_TQUEUE(a,b) tasklet_schedule((a))
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typedef unsigned long TQUEUE_ARG;
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#define mark_bh(a) do {} while (0)
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#else /* immediate work queue */
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#define ATH_TQ_STRUCT tq_struct
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#define ATH_INIT_TQUEUE(a,b,c) INIT_TQUEUE(a,b,c)
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#define ATH_SCHEDULE_TQUEUE(a,b) do { \
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*(b) |= queue_task((a), &tq_immediate); \
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} while (0)
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typedef void *TQUEUE_ARG;
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#define tasklet_disable(t) do { (void) t; local_bh_disable(); } while (0)
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#define tasklet_enable(t) do { (void) t; local_bh_enable(); } while (0)
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#endif /* !DECLARE_TASKLET */
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#include <linux/sched.h>
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#if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,41)
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#include <linux/tqueue.h>
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#define work_struct tq_struct
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#define schedule_work(t) schedule_task((t))
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#define flush_scheduled_work() flush_scheduled_tasks()
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#define ATH_INIT_WORK(t, f) do { \
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memset((t), 0, sizeof(struct tq_struct)); \
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(t)->routine = (void (*)(void*)) (f); \
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(t)->data=(void *) (t); \
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} while (0)
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#else
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#include <linux/workqueue.h>
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#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20)
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#define ATH_INIT_WORK(_t, _f) INIT_WORK((_t), (void (*)(void *))(_f), (_t));
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#else
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#define ATH_INIT_WORK(_t, _f) INIT_WORK((_t), (_f));
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#endif
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#endif /* KERNEL_VERSION < 2.5.41 */
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/*
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* Guess how the interrupt handler should work.
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*/
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#if !defined(IRQ_NONE)
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typedef void irqreturn_t;
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#define IRQ_NONE
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#define IRQ_HANDLED
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#endif /* !defined(IRQ_NONE) */
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#ifndef SET_MODULE_OWNER
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#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,23)
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#define SET_MODULE_OWNER(dev) do { \
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dev->owner = THIS_MODULE; \
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} while (0)
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#else
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#define SET_MODULE_OWNER(dev) do { } while (0)
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#endif
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#endif
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#ifndef SET_NETDEV_DEV
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#define SET_NETDEV_DEV(ndev, pdev)
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#endif
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#ifdef to_net_dev
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#define ATH_GET_NETDEV_DEV(ndev) ((ndev)->dev.parent)
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#else
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#define ATH_GET_NETDEV_DEV(ndev) ((ndev)->class_dev.dev)
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#endif
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#ifndef NETDEV_TX_OK
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#define NETDEV_TX_OK 0
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#define NETDEV_TX_BUSY 1
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#endif
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#if LINUX_VERSION_CODE < KERNEL_VERSION(2,4,23)
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static inline struct net_device *_alloc_netdev(int sizeof_priv, const char *mask,
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void (*setup)(struct net_device *))
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{
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struct net_device *dev;
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int alloc_size;
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/* ensure 32-byte alignment of the private area */
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alloc_size = sizeof (*dev) + sizeof_priv + 31;
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dev = (struct net_device *) kmalloc (alloc_size, GFP_KERNEL);
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if (dev == NULL)
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{
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printk(KERN_ERR "alloc_dev: Unable to allocate device memory.\n");
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return NULL;
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}
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memset(dev, 0, alloc_size);
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if (sizeof_priv)
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dev->priv = (void *) (((long)(dev + 1) + 31) & ~31);
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setup(dev);
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strcpy(dev->name, mask);
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return dev;
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}
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/* Avoid name collision - some vendor kernels backport alloc_netdev() */
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#undef alloc_netdev
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#define alloc_netdev(s,m,d) _alloc_netdev(s, m, d)
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/* Some vendors backport PDE, so make it a macro here */
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#undef PDE
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#define PDE(inode) ((struct proc_dir_entry *)(inode)->u.generic_ip)
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#endif
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/*
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* Macro to expand scalars to 64-bit objects
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*/
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#define ito64(x) (sizeof(x)==8) ? (((unsigned long long int)(x)) & (0xff)) : \
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(sizeof(x)==16) ? (((unsigned long long int)(x)) & 0xffff) : \
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((sizeof(x)==32) ? (((unsigned long long int)(x)) & 0xffffffff): (unsigned long long int)(x))
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/*
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* Deal with the sysctl handler api changing.
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*/
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#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,8)
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#define ATH_SYSCTL_DECL(f, ctl, write, filp, buffer, lenp, ppos) \
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f(ctl_table *ctl, int write, struct file *filp, \
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void __user *buffer, size_t *lenp)
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#define ATH_SYSCTL_PROC_DOINTVEC(ctl, write, filp, buffer, lenp, ppos) \
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proc_dointvec(ctl, write, filp, buffer, lenp)
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#else /* LINUX_VERSION_CODE < KERNEL_VERSION(2,6,8) */
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#define ATH_SYSCTL_DECL(f, ctl, write, filp, buffer, lenp, ppos) \
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f(ctl_table *ctl, int write, struct file *filp, \
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void __user *buffer, size_t *lenp, loff_t *ppos)
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#define ATH_SYSCTL_PROC_DOINTVEC(ctl, write, filp, buffer, lenp, ppos) \
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proc_dointvec(ctl, write, filp, buffer, lenp, ppos)
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#endif
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#define ATH_TIMEOUT 1000
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#define ATH_DFS_WAIT_POLL_PERIOD 2 /* 2 seconds */
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#define ATH_LONG_CALINTERVAL 30 /* 30 seconds between calibrations */
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#define ATH_SHORT_CALINTERVAL 1 /* 1 second between calibrations */
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/*
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* Maximum acceptable MTU
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* MAXFRAMEBODY - WEP - QOS - RSN/WPA:
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* 2312 - 8 - 2 - 12 = 2290
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*/
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#define ATH_MAX_MTU 2290
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#define ATH_MIN_MTU 32
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#define ATH_RXBUF 40 /* number of RX buffers */
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#define ATH_TXBUF 200 /* number of TX buffers */
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#define ATH_BCBUF 4 /* number of beacon buffers */
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/* free buffer threshold to restart net dev */
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#define ATH_TXBUF_FREE_THRESHOLD (ATH_TXBUF / 20)
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#define TAIL_DROP_COUNT 50 /* maximum number of queued frames allowed */
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/*
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* dynamic turbo specific macros.
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*/
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#define ATH_TURBO_UP_THRESH 750000 /* bytes/sec */
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#define ATH_TURBO_DN_THRESH 1000000 /* bytes/sec */
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#define ATH_TURBO_PERIOD_HOLD 1 /* in seconds */
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/*
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* The only case where we see skbuff chains is due to FF aggregation in
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* the driver.
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*/
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#ifdef ATH_SUPERG_FF
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#define ATH_TXDESC 2 /* number of descriptors per buffer */
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#else
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#define ATH_TXDESC 1 /* number of descriptors per buffer */
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#endif
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#define ATH_TXMAXTRY 11 /* max number of transmit attempts */
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/* Compress settings */
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#define ATH_COMP_THRESHOLD 256 /* no compression for frames
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longer than this threshold */
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#define ATH_COMP_PROC_NO_COMP_NO_CCS 3
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#define ATH_COMP_PROC_NO_COMP_ADD_CCS 2
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#define ATH_COMP_PROC_COMP_NO_OPTIAML 1
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#define ATH_COMP_PROC_COMP_OPTIMAL 0
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#define ATH_DEFAULT_COMP_PROC ATH_COMP_PROC_COMP_OPTIMAL
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#define INVALID_DECOMP_INDEX 0xFFFF
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#define WEP_IV_FIELD_SIZE 4 /* wep IV field size */
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#define WEP_ICV_FIELD_SIZE 4 /* wep ICV field size */
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#define AES_ICV_FIELD_SIZE 8 /* AES ICV field size */
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#define EXT_IV_FIELD_SIZE 4 /* ext IV field size */
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/* XR specific macros */
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#define XR_DEFAULT_GRPPOLL_RATE_STR "0.25 1 1 3 3 6 6 20"
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#define GRPPOLL_RATE_STR_LEN 64
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#define XR_SLOT_DELAY 30 /* in usec */
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#define XR_AIFS 0
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#define XR_NUM_RATES 5
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#define XR_NUM_SUP_RATES 8
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/* XR uplink should have same cwmin/cwmax value */
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#define XR_CWMIN_CWMAX 7
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#define XR_DATA_AIFS 3
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#define XR_DATA_CWMIN 31
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#define XR_DATA_CWMAX 1023
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/* pick the threshold so that we meet most of the regulatory constraints */
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#define XR_FRAGMENTATION_THRESHOLD 540
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#define XR_TELEC_FRAGMENTATION_THRESHOLD 442
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#define XR_MAX_GRP_POLL_PERIOD 1000 /* Maximum Group Poll Periodicity */
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#define XR_DEFAULT_POLL_INTERVAL 100
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#define XR_MIN_POLL_INTERVAL 30
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#define XR_MAX_POLL_INTERVAL 1000
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#define XR_DEFAULT_POLL_COUNT 32
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#define XR_MIN_POLL_COUNT 16
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#define XR_MAX_POLL_COUNT 64
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#define XR_POLL_UPDATE_PERIOD 10 /* number of XR beacons */
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#define XR_GRPPOLL_PERIOD_FACTOR 5 /* factor used in calculating grp poll interval */
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#define XR_4MS_FRAG_THRESHOLD 128 /* fragmentation threshold for 4msec frame limit */
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/*
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* Maximum Values in ms for group poll periodicty
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*/
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#define GRP_POLL_PERIOD_NO_XR_STA_MAX 100
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#define GRP_POLL_PERIOD_XR_STA_MAX 30
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/*
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* Percentage of the configured poll periodicity
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*/
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#define GRP_POLL_PERIOD_FACTOR_XR_STA 30 /* When XR Stations associated freq is 30% higher */
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#define A_MAX(a,b) ((a) > (b) ? (a) : (b))
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/*
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* Macros to obtain the Group Poll Periodicity in various situations
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*
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* Curerntly there are the two cases
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* (a) When there are no XR STAs associated
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* (b) When there is atleast one XR STA associated
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*/
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#define GRP_POLL_PERIOD_NO_XR_STA(sc) (sc->sc_xrpollint)
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#define GRP_POLL_PERIOD_XR_STA(sc) \
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A_MAX(GRP_POLL_PERIOD_FACTOR_XR_STA * (sc->sc_xrpollint / 100), GRP_POLL_PERIOD_XR_STA_MAX)
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/*
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* When there are no XR STAs and a valid double chirp is received then the Group Polls are
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* transmitted for 10 seconds from the time of the last valid double double-chirp
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*/
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#define NO_XR_STA_GRPPOLL_TX_DUR 10000
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/*
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* The key cache is used for h/w cipher state and also for
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* tracking station state such as the current tx antenna.
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* We also setup a mapping table between key cache slot indices
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* and station state to short-circuit node lookups on rx.
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* Different parts have different size key caches. We handle
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* up to ATH_KEYMAX entries (could dynamically allocate state).
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*/
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#define ATH_KEYMAX 128 /* max key cache size we handle */
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#define ATH_KEYBYTES (ATH_KEYMAX / NBBY) /* storage space in bytes */
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#ifdef ATH_REVERSE_ENGINEERING
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#define MIN_REGISTER_ADDRESS 0x0000 /* PCI register addresses are taken as releative to the appropriate BAR */
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#define MAX_REGISTER_ADDRESS 0xc000 /* AR5212/AR5213 seems to have a 48k address range */
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#define MAX_REGISTER_NAME_LEN 32 /* Maximum length of register nicknames in debug output */
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#define UNKNOWN_NAME "(unknown)" /* Name used when reading/listing undocumented registers */
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#endif /* #ifdef ATH_REVERSE_ENGINEERING */
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/*
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* Convert from net80211 layer values to Ath layer values. Hopefully this will
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* be optimised away when the two constants are the same.
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*/
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typedef unsigned int ath_keyix_t;
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#define ATH_KEY(_keyix) ((_keyix == IEEE80211_KEYIX_NONE) ? HAL_TXKEYIX_INVALID : _keyix)
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#define ATH_MIN_FF_RATE 12000 /* min rate for ff aggregation in kbps */
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#define ATH_MIN_FF_RATE 12000 /* min rate for ff aggregation in kbps */
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struct ath_buf;
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typedef STAILQ_HEAD(, ath_buf) ath_bufhead;
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/* driver-specific node state */
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struct ath_node {
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struct ieee80211_node an_node; /* base class */
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u_int16_t an_decomp_index; /* decompression mask index */
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u_int32_t an_avgrssi; /* average rssi over all rx frames */
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u_int8_t an_prevdatarix; /* rate ix of last data frame */
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u_int16_t an_minffrate; /* min rate in kbps for ff to aggregate */
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HAL_NODE_STATS an_halstats; /* rssi statistics used by hal */
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struct ath_buf *an_tx_ffbuf[WME_NUM_AC]; /* ff staging area */
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ath_bufhead an_uapsd_q; /* U-APSD delivery queue */
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int an_uapsd_qdepth; /* U-APSD delivery queue depth */
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ath_bufhead an_uapsd_overflowq; /* U-APSD overflow queue (for > MaxSp frames) */
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int an_uapsd_overflowqdepth; /* U-APSD overflow queue depth */
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spinlock_t an_uapsd_lock; /* U-APSD delivery queue lock */
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/* variable-length rate control state follows */
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};
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#define ATH_NODE(_n) ((struct ath_node *)(_n))
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#define ATH_NODE_CONST(ni) ((const struct ath_node *)(ni))
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#define ATH_NODE_UAPSD_LOCK_INIT(_an) spin_lock_init(&(_an)->an_uapsd_lock)
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#define ATH_NODE_UAPSD_LOCK_IRQ(_an) do { \
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unsigned long __an_uapsd_lockflags; \
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spin_lock_irqsave(&(_an)->an_uapsd_lock, __an_uapsd_lockflags);
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#define ATH_NODE_UAPSD_UNLOCK_IRQ(_an) \
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spin_unlock_irqrestore(&(_an)->an_uapsd_lock, __an_uapsd_lockflags); \
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} while (0)
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#define ATH_NODE_UAPSD_UNLOCK_IRQ_EARLY(_an) \
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spin_unlock_irqrestore(&(_an)->an_uapsd_lock, __an_uapsd_lockflags);
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#define ATH_RSSI_LPF_LEN 10
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#define ATH_RSSI_DUMMY_MARKER 0x127
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#define ATH_EP_MUL(x, mul) ((x) * (mul))
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#define ATH_RSSI_IN(x) (ATH_EP_MUL((x), HAL_RSSI_EP_MULTIPLIER))
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#define ATH_LPF_RSSI(x, y, len) \
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((x != ATH_RSSI_DUMMY_MARKER) ? (((x) * ((len) - 1) + (y)) / (len)) : (y))
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#define ATH_RSSI_LPF(x, y) do { \
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if ((y) >= -20) \
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x = ATH_LPF_RSSI((x), ATH_RSSI_IN((y)), ATH_RSSI_LPF_LEN); \
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} while (0)
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#define ATH_ANTENNA_DIFF 2 /* Num frames difference in
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* tx to flip default recv
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* antenna
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*/
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struct ath_buf {
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/* FFXXX: convert both list types to TAILQ to save a field? */
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STAILQ_ENTRY(ath_buf) bf_list;
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#ifdef ATH_SUPERG_FF
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TAILQ_ENTRY(ath_buf) bf_stagelist; /* fast-frame staging list */
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#endif
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struct ath_desc *bf_desc; /* virtual addr of desc */
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struct ath_desc_status bf_dsstatus; /* tx/rx descriptor status */
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dma_addr_t bf_daddr; /* physical addr of desc */
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struct sk_buff *bf_skb; /* skbuff for buf */
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dma_addr_t bf_skbaddr; /* physical addr of skb data - always used by one desc*/
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struct ieee80211_node *bf_node; /* pointer to the node */
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u_int32_t bf_status; /* status flags */
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u_int16_t bf_flags; /* tx descriptor flags */
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u_int64_t bf_tsf;
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int16_t bf_channoise;
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#ifdef ATH_SUPERG_FF
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/* XXX: combine this with bf_skbaddr if it ever changes to accommodate
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* multiple segments.
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*/
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u_int16_t bf_numdescff; /* number of descs used for FF (these are extra) */
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u_int32_t bf_queueage; /* "age" of txq when this buffer placed on stageq */
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dma_addr_t bf_skbaddrff[ATH_TXDESC - 1]; /* extra addrs for FF */
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#endif
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};
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/*
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* reset the rx buffer.
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* any new fields added to the athbuf and require
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* reset need to be added to this macro.
|
|
* currently bf_status is the only one that
|
|
* requires reset.
|
|
*/
|
|
#define ATH_RXBUF_RESET(bf) bf->bf_status=0
|
|
|
|
/* XXX: only managed for rx at the moment */
|
|
#define ATH_BUFSTATUS_DONE 0x00000001 /* hw processing complete, desc processed by hal */
|
|
#define ATH_BUFSTATUS_RADAR_DONE 0x00000002 /* marker to indicate a PHYERR for radar pulse
|
|
has already been handled. We may receive
|
|
multiple interrupts before the rx_tasklet
|
|
clears the queue */
|
|
/* DMA state for tx/rx descriptors. */
|
|
struct ath_descdma {
|
|
const char *dd_name;
|
|
struct ath_desc *dd_desc; /* descriptors */
|
|
dma_addr_t dd_desc_paddr; /* physical addr of dd_desc */
|
|
size_t dd_desc_len; /* size of dd_desc */
|
|
struct ath_buf *dd_bufptr; /* associated buffers */
|
|
};
|
|
|
|
struct ath_hal;
|
|
struct ath_desc;
|
|
struct ath_ratectrl;
|
|
struct ath_tx99;
|
|
struct proc_dir_entry;
|
|
|
|
/*
|
|
* Data transmit queue state. One of these exists for each
|
|
* hardware transmit queue. Packets sent to us from above
|
|
* are assigned to queues based on their priority. Not all
|
|
* devices support a complete set of hardware transmit queues.
|
|
* For those devices the array sc_ac2q will map multiple
|
|
* priorities to fewer hardware queues (typically all to one
|
|
* hardware queue).
|
|
*/
|
|
struct ath_txq {
|
|
u_int axq_qnum; /* hardware q number */
|
|
u_int32_t *axq_link; /* link ptr in last TX desc */
|
|
STAILQ_HEAD(, ath_buf) axq_q; /* transmit queue */
|
|
spinlock_t axq_lock; /* lock on q and link */
|
|
int axq_depth; /* queue depth */
|
|
u_int32_t axq_totalqueued; /* total ever queued */
|
|
u_int axq_intrcnt; /* count to determine if descriptor
|
|
* should generate int on this txq.
|
|
*/
|
|
/*
|
|
* Staging queue for frames awaiting a fast-frame pairing.
|
|
*/
|
|
TAILQ_HEAD(axq_headtype, ath_buf) axq_stageq;
|
|
|
|
/* scratch compression buffer */
|
|
char *axq_compbuf; /* scratch comp buffer */
|
|
dma_addr_t axq_compbufp; /* scratch comp buffer (phys)*/
|
|
u_int axq_compbufsz; /* scratch comp buffer size */
|
|
};
|
|
|
|
/* driver-specific vap state */
|
|
struct ath_vap {
|
|
struct ieee80211vap av_vap; /* base class */
|
|
int (*av_newstate)(struct ieee80211vap *, enum ieee80211_state, int);
|
|
/* XXX beacon state */
|
|
struct ath_buf *av_bcbuf; /* beacon buffer */
|
|
struct ieee80211_beacon_offsets av_boff;/* dynamic update state */
|
|
int av_bslot; /* beacon slot index */
|
|
struct ath_txq av_mcastq; /* multicast transmit queue */
|
|
u_int8_t av_dfswait_run;
|
|
};
|
|
#define ATH_VAP(_v) ((struct ath_vap *)(_v))
|
|
|
|
#define ATH_BEACON_AIFS_DEFAULT 0 /* Default aifs for ap beacon q */
|
|
#define ATH_BEACON_CWMIN_DEFAULT 0 /* Default cwmin for ap beacon q */
|
|
#define ATH_BEACON_CWMAX_DEFAULT 0 /* Default cwmax for ap beacon q */
|
|
|
|
#define ATH_TXQ_INTR_PERIOD 5 /* axq_intrcnt period for intr gen */
|
|
#define ATH_TXQ_LOCK_INIT(_tq) spin_lock_init(&(_tq)->axq_lock)
|
|
#define ATH_TXQ_LOCK_DESTROY(_tq)
|
|
#define ATH_TXQ_LOCK_IRQ(_tq) do { \
|
|
unsigned long __axq_lockflags; \
|
|
spin_lock_irqsave(&(_tq)->axq_lock, __axq_lockflags);
|
|
#define ATH_TXQ_UNLOCK_IRQ(_tq) \
|
|
spin_unlock_irqrestore(&(_tq)->axq_lock, __axq_lockflags); \
|
|
} while (0)
|
|
#define ATH_TXQ_UNLOCK_IRQ_EARLY(_tq) \
|
|
spin_unlock_irqrestore(&(_tq)->axq_lock, __axq_lockflags);
|
|
#define ATH_TXQ_LOCK_IRQ_INSIDE(_tq) spin_lock(&(_tq)->axq_lock);
|
|
#define ATH_TXQ_UNLOCK_IRQ_INSIDE(_tq) spin_unlock(&(_tq)->axq_lock);
|
|
|
|
#define ATH_TXQ_LOCK_ASSERT(_tq) \
|
|
KASSERT(spin_is_locked(&(_tq)->axq_lock), ("txq not locked!"))
|
|
|
|
#define ATH_TXQ_INSERT_TAIL(_tq, _elm, _field) do { \
|
|
STAILQ_INSERT_TAIL( &(_tq)->axq_q, (_elm), _field); \
|
|
(_tq)->axq_depth++; \
|
|
(_tq)->axq_totalqueued++; \
|
|
} while (0)
|
|
#define ATH_TXQ_REMOVE_HEAD(_tq, _field) do { \
|
|
STAILQ_REMOVE_HEAD(&(_tq)->axq_q, _field); \
|
|
(_tq)->axq_depth--; \
|
|
} while (0)
|
|
/* move buffers from MCASTQ to CABQ */
|
|
#define ATH_TXQ_MOVE_MCASTQ(_tqs,_tqd) do { \
|
|
(_tqd)->axq_depth += (_tqs)->axq_depth; \
|
|
(_tqd)->axq_totalqueued += (_tqs)->axq_totalqueued; \
|
|
(_tqd)->axq_link = (_tqs)->axq_link; \
|
|
STAILQ_CONCAT(&(_tqd)->axq_q, &(_tqs)->axq_q); \
|
|
(_tqs)->axq_depth=0; \
|
|
(_tqs)->axq_totalqueued = 0; \
|
|
(_tqs)->axq_link = NULL; \
|
|
} while (0)
|
|
|
|
/*
|
|
* concat buffers from one queue to other
|
|
*/
|
|
#define ATH_TXQ_MOVE_Q(_tqs,_tqd) ATH_TXQ_MOVE_MCASTQ(_tqs,_tqd)
|
|
|
|
#define BSTUCK_THRESH 10 /* # of stuck beacons before resetting NB: this is a guess*/
|
|
|
|
struct ath_softc {
|
|
struct ieee80211com sc_ic; /* NB: must be first */
|
|
struct net_device *sc_dev;
|
|
void __iomem *sc_iobase; /* address of the device */
|
|
struct semaphore sc_lock; /* dev-level lock */
|
|
struct net_device_stats sc_devstats; /* device statistics */
|
|
struct ath_stats sc_stats; /* private statistics */
|
|
int devid;
|
|
int sc_debug;
|
|
void (*sc_recv_mgmt)(struct ieee80211_node *, struct sk_buff *, int, int, u_int64_t);
|
|
void (*sc_node_cleanup)(struct ieee80211_node *);
|
|
void (*sc_node_free)(struct ieee80211_node *);
|
|
void *sc_bdev; /* associated bus device */
|
|
struct ath_hal *sc_ah; /* Atheros HAL */
|
|
spinlock_t sc_hal_lock; /* hardware access lock */
|
|
struct ath_ratectrl *sc_rc; /* tx rate control support */
|
|
struct ath_tx99 *sc_tx99; /* tx99 support */
|
|
void (*sc_setdefantenna)(struct ath_softc *, u_int);
|
|
unsigned int sc_invalid:1, /* being detached */
|
|
sc_mrretry:1, /* multi-rate retry support */
|
|
sc_softled:1, /* enable LED gpio status */
|
|
sc_splitmic:1, /* split TKIP MIC keys */
|
|
sc_needmib:1, /* enable MIB stats intr */
|
|
sc_hasdiversity:1, /* rx diversity available */
|
|
sc_diversity:1, /* enable rx diversity */
|
|
sc_olddiversity:1, /* diversity setting before XR enable */
|
|
sc_hasveol:1, /* tx VEOL support */
|
|
sc_hastpc:1, /* per-packet TPC support */
|
|
sc_dturbo:1, /* dynamic turbo capable */
|
|
sc_dturbo_switch:1, /* turbo switch mode*/
|
|
sc_dturbo_hold:1, /* dynamic turbo hold state */
|
|
sc_rate_recn_state:1, /* dynamic turbo state recmded by ratectrl */
|
|
sc_ignore_ar:1, /* ignore AR during transition */
|
|
sc_ledstate:1, /* LED on/off state */
|
|
sc_blinking:1, /* LED blink operation active */
|
|
sc_beacons:1, /* beacons running */
|
|
sc_hasbmask:1, /* bssid mask support */
|
|
sc_mcastkey:1, /* mcast key cache search */
|
|
sc_hastsfadd:1, /* tsf adjust support */
|
|
sc_scanning:1, /* scanning active */
|
|
sc_nostabeacons:1, /* no beacons for station */
|
|
sc_xrgrppoll:1, /* xr group polls are active */
|
|
sc_syncbeacon:1, /* sync/resync beacon timers */
|
|
sc_hasclrkey:1, /* CLR key supported */
|
|
sc_devstopped:1, /* stopped due to of no tx bufs */
|
|
sc_stagbeacons:1, /* use staggered beacons */
|
|
sc_dfswait:1, /* waiting on channel for radar detect */
|
|
sc_ackrate:1, /* send acks at high bitrate */
|
|
sc_hasintmit:1; /* Interference mitigation */
|
|
/* rate tables */
|
|
const HAL_RATE_TABLE *sc_rates[IEEE80211_MODE_MAX];
|
|
const HAL_RATE_TABLE *sc_currates; /* current rate table */
|
|
const HAL_RATE_TABLE *sc_xr_rates; /* XR rate table */
|
|
const HAL_RATE_TABLE *sc_half_rates; /* half rate table */
|
|
const HAL_RATE_TABLE *sc_quarter_rates; /* quarter rate table */
|
|
HAL_OPMODE sc_opmode; /* current hal operating mode */
|
|
enum ieee80211_phymode sc_curmode; /* current phy mode */
|
|
u_int16_t sc_curtxpow; /* current tx power limit */
|
|
u_int16_t sc_curaid; /* current association id */
|
|
HAL_CHANNEL sc_curchan; /* current h/w channel */
|
|
u_int8_t sc_curbssid[IEEE80211_ADDR_LEN];
|
|
u_int8_t sc_rixmap[256]; /* IEEE to h/w rate table ix */
|
|
struct {
|
|
u_int8_t ieeerate; /* IEEE rate */
|
|
u_int8_t flags; /* radiotap flags */
|
|
u_int16_t ledon; /* softled on time */
|
|
u_int16_t ledoff; /* softled off time */
|
|
} sc_hwmap[32]; /* h/w rate ix mappings */
|
|
u_int8_t sc_minrateix; /* min h/w rate index */
|
|
u_int8_t sc_protrix; /* protection rate index */
|
|
u_int8_t sc_mcastantenna; /* Multicast antenna number */
|
|
u_int8_t sc_txantenna; /* data tx antenna (fixed or auto) */
|
|
u_int16_t sc_nvaps; /* # of active virtual APs */
|
|
u_int8_t sc_nstavaps; /* # of active station VAPs */
|
|
u_int8_t sc_nmonvaps; /* # of monitor VAPs */
|
|
u_int8_t sc_nbcnvaps; /* # of vaps sending beacons */
|
|
u_int sc_fftxqmin; /* aggregation threshold */
|
|
HAL_INT sc_imask; /* interrupt mask copy */
|
|
u_int sc_keymax; /* size of key cache */
|
|
u_int8_t sc_keymap[ATH_KEYBYTES]; /* key use bit map */
|
|
struct ieee80211_node *sc_keyixmap[ATH_KEYMAX];/* key ix->node map */
|
|
u_int8_t sc_bssidmask[IEEE80211_ADDR_LEN];
|
|
|
|
u_int sc_ledpin; /* GPIO pin for driving LED */
|
|
u_int sc_ledon; /* pin setting for LED on */
|
|
u_int sc_ledidle; /* idle polling interval */
|
|
int sc_ledevent; /* time of last LED event */
|
|
u_int8_t sc_rxrate; /* current rx rate for LED */
|
|
u_int8_t sc_txrate; /* current tx rate for LED */
|
|
u_int16_t sc_ledoff; /* off time for current blink */
|
|
struct timer_list sc_ledtimer; /* led off timer */
|
|
struct timer_list sc_dfswaittimer; /* dfs wait timer */
|
|
|
|
struct ATH_TQ_STRUCT sc_fataltq; /* fatal error intr tasklet */
|
|
|
|
int sc_rxbufsize; /* rx size based on mtu */
|
|
struct ath_descdma sc_rxdma; /* RX descriptors */
|
|
ath_bufhead sc_rxbuf; /* receive buffer */
|
|
struct ath_buf *sc_rxbufcur; /* current rx buffer */
|
|
u_int32_t *sc_rxlink; /* link ptr in last RX desc */
|
|
spinlock_t sc_rxbuflock;
|
|
struct ATH_TQ_STRUCT sc_rxtq; /* rx intr tasklet */
|
|
struct ATH_TQ_STRUCT sc_rxorntq; /* rxorn intr tasklet */
|
|
u_int8_t sc_defant; /* current default antenna */
|
|
u_int8_t sc_rxotherant; /* RXs on non-default antenna */
|
|
u_int16_t sc_cachelsz; /* cache line size */
|
|
|
|
struct ath_descdma sc_txdma; /* TX descriptors */
|
|
ath_bufhead sc_txbuf; /* transmit buffer */
|
|
spinlock_t sc_txbuflock; /* txbuf lock */
|
|
u_int sc_txqsetup; /* h/w queues setup */
|
|
u_int sc_txintrperiod; /* tx interrupt batching */
|
|
struct ath_txq sc_txq[HAL_NUM_TX_QUEUES];
|
|
struct ath_txq *sc_ac2q[WME_NUM_AC]; /* WME AC -> h/w qnum */
|
|
struct ATH_TQ_STRUCT sc_txtq; /* tx intr tasklet */
|
|
u_int8_t sc_grppoll_str[GRPPOLL_RATE_STR_LEN];
|
|
struct ath_descdma sc_bdma; /* beacon descriptors */
|
|
ath_bufhead sc_bbuf; /* beacon buffers */
|
|
u_int sc_bhalq; /* HAL q for outgoing beacons */
|
|
u_int sc_bmisscount; /* missed beacon transmits */
|
|
u_int32_t sc_ant_tx[8]; /* recent tx frames/antenna */
|
|
struct ath_txq *sc_cabq; /* tx q for cab frames */
|
|
struct ath_txq sc_grpplq; /* tx q for XR group polls */
|
|
struct ath_txq *sc_xrtxq; /* tx q for XR data */
|
|
struct ath_descdma sc_grppolldma; /* TX descriptors for grppoll */
|
|
ath_bufhead sc_grppollbuf; /* transmit buffers for grouppoll */
|
|
u_int16_t sc_xrpollint; /* xr poll interval */
|
|
u_int16_t sc_xrpollcount; /* xr poll count */
|
|
struct ath_txq *sc_uapsdq; /* tx q for uapsd */
|
|
struct ATH_TQ_STRUCT sc_bmisstq; /* bmiss intr tasklet */
|
|
struct ATH_TQ_STRUCT sc_bstucktq; /* beacon stuck intr tasklet */
|
|
enum {
|
|
OK, /* no change needed */
|
|
UPDATE, /* update pending */
|
|
COMMIT /* beacon sent, commit change */
|
|
} sc_updateslot; /* slot time update fsm */
|
|
int sc_slotupdate; /* slot to next advance fsm */
|
|
struct ieee80211vap *sc_bslot[ATH_BCBUF];/* beacon xmit slots */
|
|
int sc_bnext; /* next slot for beacon xmit */
|
|
|
|
struct timer_list sc_cal_ch; /* calibration timer */
|
|
HAL_NODE_STATS sc_halstats; /* station-mode rssi stats */
|
|
|
|
struct ctl_table_header *sc_sysctl_header;
|
|
struct ctl_table *sc_sysctls;
|
|
|
|
u_int16_t sc_reapcount; /* # of tx buffers reaped after net dev stopped */
|
|
struct timer_list sc_mib_enable;
|
|
|
|
#ifdef ATH_REVERSE_ENGINEERING
|
|
u_int8_t register_snapshot[MAX_REGISTER_ADDRESS];
|
|
#endif /* #ifdef ATH_REVERSE_ENGINEERING */
|
|
|
|
#ifdef ATH_SUPERG_DYNTURBO
|
|
struct timer_list sc_dturbo_switch_mode;/* AP scan timer */
|
|
u_int32_t sc_dturbo_tcount; /* beacon intval count */
|
|
u_int32_t sc_dturbo_hold_max; /* hold count before switching to base*/
|
|
u_int16_t sc_dturbo_hold_count; /* hold count before switching to base*/
|
|
u_int16_t sc_dturbo_turbo_tmin; /* min turbo count */
|
|
u_int32_t sc_dturbo_bytes; /* bandwidth stats */
|
|
u_int32_t sc_dturbo_base_tmin; /* min time in base */
|
|
u_int32_t sc_dturbo_turbo_tmax; /* max time in turbo */
|
|
u_int32_t sc_dturbo_bw_base; /* bandwidth threshold */
|
|
u_int32_t sc_dturbo_bw_turbo; /* bandwidth threshold */
|
|
#endif
|
|
u_int sc_slottimeconf; /* manual override for slottime */
|
|
u_int64_t sc_tsf; /* TSF at last rx interrupt */
|
|
};
|
|
|
|
typedef void (*ath_callback) (struct ath_softc *);
|
|
#define ATH_TXQ_SETUP(sc, i) ((sc)->sc_txqsetup & (1 << i))
|
|
|
|
#define ATH_TXBUF_LOCK_INIT(_sc) spin_lock_init(&(_sc)->sc_txbuflock)
|
|
#define ATH_TXBUF_LOCK_DESTROY(_sc)
|
|
#define ATH_TXBUF_LOCK_IRQ(_sc) do { \
|
|
unsigned long __txbuflockflags; \
|
|
spin_lock_irqsave(&(_sc)->sc_txbuflock, __txbuflockflags);
|
|
#define ATH_TXBUF_UNLOCK_IRQ(_sc) \
|
|
spin_unlock_irqrestore(&(_sc)->sc_txbuflock, __txbuflockflags); \
|
|
} while (0)
|
|
#define ATH_TXBUF_UNLOCK_IRQ_EARLY(_sc) \
|
|
spin_unlock_irqrestore(&(_sc)->sc_txbuflock, __txbuflockflags);
|
|
|
|
#define ATH_TXBUF_LOCK_ASSERT(_sc) \
|
|
KASSERT(spin_is_locked(&(_sc)->sc_txbuflock), ("txbuf not locked!"))
|
|
|
|
|
|
#define ATH_RXBUF_LOCK_INIT(_sc) spin_lock_init(&(_sc)->sc_rxbuflock)
|
|
#define ATH_RXBUF_LOCK_DESTROY(_sc)
|
|
#define ATH_RXBUF_LOCK_IRQ(_sc) do { \
|
|
unsigned long __rxbuflockflags; \
|
|
spin_lock_irqsave(&(_sc)->sc_rxbuflock, __rxbuflockflags);
|
|
#define ATH_RXBUF_UNLOCK_IRQ(_sc) \
|
|
spin_unlock_irqrestore(&(_sc)->sc_rxbuflock, __rxbuflockflags); \
|
|
} while (0)
|
|
#define ATH_RXBUF_UNLOCK_IRQ_EARLY(_sc) \
|
|
spin_unlock_irqrestore(&(_sc)->sc_rxbuflock, __rxbuflockflags);
|
|
|
|
/* Protects the device from concurrent accesses */
|
|
#define ATH_LOCK_INIT(_sc) init_MUTEX(&(_sc)->sc_lock)
|
|
#define ATH_LOCK_DESTROY(_sc)
|
|
#define ATH_LOCK(_sc) down(&(_sc)->sc_lock)
|
|
#define ATH_UNLOCK(_sc) up(&(_sc)->sc_lock)
|
|
|
|
int ath_attach(u_int16_t, struct net_device *, HAL_BUS_TAG);
|
|
int ath_detach(struct net_device *);
|
|
void ath_resume(struct net_device *);
|
|
void ath_suspend(struct net_device *);
|
|
#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,19)
|
|
irqreturn_t ath_intr(int, void *);
|
|
#else
|
|
irqreturn_t ath_intr(int, void *, struct pt_regs *);
|
|
#endif
|
|
int ath_ioctl_ethtool(struct ath_softc *, int, void __user *);
|
|
void bus_read_cachesize(struct ath_softc *, u_int8_t *);
|
|
void ath_sysctl_register(void);
|
|
void ath_sysctl_unregister(void);
|
|
|
|
#endif /* _DEV_ATH_ATHVAR_H */
|