mirror of https://github.com/proski/madwifi
178 lines
6.7 KiB
C
178 lines
6.7 KiB
C
/*
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* Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
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* Copyright (c) 2002-2008 Atheros Communications, Inc.
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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* $Id: ar5212desc.h,v 1.4 2008/11/10 04:08:03 sam Exp $
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*/
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#ifndef _ATH_AR5212_DESC_H_
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#define _ATH_AR5212_DESC_H_
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/*
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* Hardware-specific descriptor structures.
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*/
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#include "ah_desc.h"
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/*
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* AR5212-specific tx/rx descriptor definition.
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*/
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struct ar5212_desc {
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uint32_t ds_link; /* link pointer */
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uint32_t ds_data; /* data buffer pointer */
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uint32_t ds_ctl0; /* DMA control 0 */
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uint32_t ds_ctl1; /* DMA control 1 */
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union {
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struct { /* xmit format */
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uint32_t ctl2; /* DMA control 2 */
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uint32_t ctl3; /* DMA control 3 */
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uint32_t status0;/* DMA status 0 */
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uint32_t status1;/* DMA status 1 */
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} tx;
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struct { /* recv format */
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uint32_t status0;/* DMA status 0 */
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uint32_t status1;/* DMA status 1 */
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} rx;
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} u;
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} __packed;
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#define AR5212DESC(_ds) ((struct ar5212_desc *)(_ds))
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#define AR5212DESC_CONST(_ds) ((const struct ar5212_desc *)(_ds))
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#define ds_ctl2 u.tx.ctl2
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#define ds_ctl3 u.tx.ctl3
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#define ds_txstatus0 u.tx.status0
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#define ds_txstatus1 u.tx.status1
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#define ds_rxstatus0 u.rx.status0
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#define ds_rxstatus1 u.rx.status1
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/* TX ds_ctl0 */
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#define AR_FrameLen 0x00000fff /* frame length */
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/* bits 12-15 are reserved */
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#define AR_XmitPower 0x003f0000 /* transmit power control */
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#define AR_XmitPower_S 16
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#define AR_RTSCTSEnable 0x00400000 /* RTS/CTS protocol enable */
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#define AR_VEOL 0x00800000 /* virtual end-of-list */
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#define AR_ClearDestMask 0x01000000 /* Clear destination mask bit */
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#define AR_AntModeXmit 0x1e000000 /* TX antenna seslection */
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#define AR_AntModeXmit_S 25
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#define AR_TxInterReq 0x20000000 /* TX interrupt request */
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#define AR_DestIdxValid 0x40000000 /* destination index valid */
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#define AR_CTSEnable 0x80000000 /* precede frame with CTS */
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/* TX ds_ctl1 */
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#define AR_BufLen 0x00000fff /* data buffer length */
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#define AR_More 0x00001000 /* more desc in this frame */
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#define AR_DestIdx 0x000fe000 /* destination table index */
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#define AR_DestIdx_S 13
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#define AR_FrmType 0x00f00000 /* frame type indication */
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#define AR_FrmType_S 20
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#define AR_NoAck 0x01000000 /* No ACK flag */
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#define AR_CompProc 0x06000000 /* compression processing */
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#define AR_CompProc_S 25
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#define AR_CompIVLen 0x18000000 /* length of frame IV */
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#define AR_CompIVLen_S 27
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#define AR_CompICVLen 0x60000000 /* length of frame ICV */
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#define AR_CompICVLen_S 29
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/* bit 31 is reserved */
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/* TX ds_ctl2 */
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#define AR_RTSCTSDuration 0x00007fff /* RTS/CTS duration */
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#define AR_RTSCTSDuration_S 0
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#define AR_DurUpdateEna 0x00008000 /* frame duration update ctl */
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#define AR_XmitDataTries0 0x000f0000 /* series 0 max attempts */
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#define AR_XmitDataTries0_S 16
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#define AR_XmitDataTries1 0x00f00000 /* series 1 max attempts */
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#define AR_XmitDataTries1_S 20
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#define AR_XmitDataTries2 0x0f000000 /* series 2 max attempts */
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#define AR_XmitDataTries2_S 24
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#define AR_XmitDataTries3 0xf0000000 /* series 3 max attempts */
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#define AR_XmitDataTries3_S 28
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/* TX ds_ctl3 */
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#define AR_XmitRate0 0x0000001f /* series 0 tx rate */
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#define AR_XmitRate0_S 0
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#define AR_XmitRate1 0x000003e0 /* series 1 tx rate */
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#define AR_XmitRate1_S 5
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#define AR_XmitRate2 0x00007c00 /* series 2 tx rate */
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#define AR_XmitRate2_S 10
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#define AR_XmitRate3 0x000f8000 /* series 3 tx rate */
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#define AR_XmitRate3_S 15
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#define AR_RTSCTSRate 0x01f00000 /* RTS or CTS rate */
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#define AR_RTSCTSRate_S 20
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/* bits 25-31 are reserved */
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/* RX ds_ctl1 */
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/* AR_BufLen 0x00000fff data buffer length */
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/* bit 12 is reserved */
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#define AR_RxInterReq 0x00002000 /* RX interrupt request */
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/* bits 14-31 are reserved */
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/* TX ds_txstatus0 */
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#define AR_FrmXmitOK 0x00000001 /* TX success */
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#define AR_ExcessiveRetries 0x00000002 /* excessive retries */
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#define AR_FIFOUnderrun 0x00000004 /* TX FIFO underrun */
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#define AR_Filtered 0x00000008 /* TX filter indication */
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#define AR_RTSFailCnt 0x000000f0 /* RTS failure count */
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#define AR_RTSFailCnt_S 4
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#define AR_DataFailCnt 0x00000f00 /* Data failure count */
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#define AR_DataFailCnt_S 8
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#define AR_VirtCollCnt 0x0000f000 /* virtual collision count */
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#define AR_VirtCollCnt_S 12
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#define AR_SendTimestamp 0xffff0000 /* TX timestamp */
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#define AR_SendTimestamp_S 16
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/* RX ds_rxstatus0 */
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#define AR_DataLen 0x00000fff /* RX data length */
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/* AR_More 0x00001000 more desc in this frame */
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#define AR_DecompCRCErr 0x00002000 /* decompression CRC error */
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/* bit 14 is reserved */
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#define AR_RcvRate 0x000f8000 /* reception rate */
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#define AR_RcvRate_S 15
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#define AR_RcvSigStrength 0x0ff00000 /* receive signal strength */
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#define AR_RcvSigStrength_S 20
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#define AR_RcvAntenna 0xf0000000 /* receive antenaa */
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#define AR_RcvAntenna_S 28
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/* TX ds_txstatus1 */
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#define AR_Done 0x00000001 /* descripter complete */
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#define AR_SeqNum 0x00001ffe /* TX sequence number */
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#define AR_SeqNum_S 1
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#define AR_AckSigStrength 0x001fe000 /* strength of ACK */
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#define AR_AckSigStrength_S 13
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#define AR_FinalTSIndex 0x00600000 /* final TX attempt series ix */
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#define AR_FinalTSIndex_S 21
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#define AR_CompSuccess 0x00800000 /* compression status */
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#define AR_XmitAtenna 0x01000000 /* transmit antenna */
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/* bits 25-31 are reserved */
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/* RX ds_rxstatus1 */
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/* AR_Done 0x00000001 descripter complete */
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#define AR_FrmRcvOK 0x00000002 /* frame reception success */
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#define AR_CRCErr 0x00000004 /* CRC error */
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#define AR_DecryptCRCErr 0x00000008 /* Decryption CRC fiailure */
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#define AR_PHYErr 0x00000010 /* PHY error */
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#define AR_MichaelErr 0x00000020 /* Michae MIC decrypt error */
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/* bits 6-7 are reserved */
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#define AR_KeyIdxValid 0x00000100 /* decryption key index valid */
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#define AR_KeyIdx 0x0000fe00 /* Decryption key index */
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#define AR_KeyIdx_S 9
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#define AR_RcvTimestamp 0x7fff0000 /* timestamp */
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#define AR_RcvTimestamp_S 16
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#define AR_KeyCacheMiss 0x80000000 /* key cache miss indication */
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/* NB: phy error code overlays key index and valid fields */
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#define AR_PHYErrCode 0x0000ff00 /* PHY error code */
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#define AR_PHYErrCode_S 8
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#endif /* _ATH_AR5212_DESC_H_ */
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