mirror of https://github.com/proski/madwifi
463 lines
14 KiB
C
463 lines
14 KiB
C
/*
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* Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
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* Copyright (c) 2002-2008 Atheros Communications, Inc.
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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* $Id: ah_eeprom_v3.h,v 1.2 2008/11/10 04:08:00 sam Exp $
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*/
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#ifndef _ATH_AH_EEPROM_V3_H_
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#define _ATH_AH_EEPROM_V3_H_
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#include "ah_eeprom.h"
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/* EEPROM defines for Version 2 & 3 AR5211 chips */
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#define AR_EEPROM_RFSILENT 0x0f /* RF Silent/Clock Run Enable */
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#define AR_EEPROM_MAC(i) (0x1d+(i)) /* MAC address word */
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#define AR_EEPROM_MAGIC 0x3d /* magic number */
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#define AR_EEPROM_PROTECT 0x3f /* EEPROM protect bits */
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#define AR_EEPROM_PROTECT_PCIE 0x01 /* EEPROM protect bits for Condor/Swan*/
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#define AR_EEPROM_REG_DOMAIN 0xbf /* current regulatory domain */
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#define AR_EEPROM_ATHEROS_BASE 0xc0 /* Base of Atheros-specific data */
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#define AR_EEPROM_ATHEROS(i) (AR_EEPROM_ATHEROS_BASE+(i))
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#define AR_EEPROM_ATHEROS_MAX (0x400-AR_EEPROM_ATHEROS_BASE)
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#define AR_EEPROM_VERSION AR_EEPROM_ATHEROS(1)
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/* FLASH(EEPROM) Defines for AR531X chips */
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#define AR_EEPROM_SIZE_LOWER 0x1b /* size info -- lower */
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#define AR_EEPROM_SIZE_UPPER 0x1c /* size info -- upper */
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#define AR_EEPROM_SIZE_UPPER_MASK 0xfff0
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#define AR_EEPROM_SIZE_UPPER_SHIFT 4
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#define AR_EEPROM_SIZE_ENDLOC_SHIFT 12
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#define AR_EEPROM_ATHEROS_MAX_LOC 0x400
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#define AR_EEPROM_ATHEROS_MAX_OFF (AR_EEPROM_ATHEROS_MAX_LOC-AR_EEPROM_ATHEROS_BASE)
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/* regulatory capabilities offsets */
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#define AR_EEPROM_REG_CAPABILITIES_OFFSET 0xCA
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#define AR_EEPROM_REG_CAPABILITIES_OFFSET_PRE4_0 0xCF /* prior to 4.0 */
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/* regulatory capabilities */
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#define AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND 0x0040
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#define AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN 0x0080
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#define AR_EEPROM_EEREGCAP_EN_KK_U2 0x0100
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#define AR_EEPROM_EEREGCAP_EN_KK_MIDBAND 0x0200
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#define AR_EEPROM_EEREGCAP_EN_KK_U1_ODD 0x0400
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#define AR_EEPROM_EEREGCAP_EN_KK_NEW_11A 0x0800
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/* regulatory capabilities prior to eeprom version 4.0 */
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#define AR_EEPROM_EEREGCAP_EN_KK_U1_ODD_PRE4_0 0x4000
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#define AR_EEPROM_EEREGCAP_EN_KK_NEW_11A_PRE4_0 0x8000
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/*
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* AR2413 (includes AR5413)
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*/
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#define AR_EEPROM_SERIAL_NUM_OFFSET 0xB0 /* EEPROM serial number */
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#define AR_EEPROM_SERIAL_NUM_SIZE 12 /* EEPROM serial number size */
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#define AR_EEPROM_CAPABILITIES_OFFSET 0xC9 /* EEPROM Location of capabilities */
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#define AR_EEPROM_EEPCAP_COMPRESS_DIS 0x0001
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#define AR_EEPROM_EEPCAP_AES_DIS 0x0002
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#define AR_EEPROM_EEPCAP_FASTFRAME_DIS 0x0004
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#define AR_EEPROM_EEPCAP_BURST_DIS 0x0008
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#define AR_EEPROM_EEPCAP_MAXQCU 0x01F0
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#define AR_EEPROM_EEPCAP_MAXQCU_S 4
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#define AR_EEPROM_EEPCAP_HEAVY_CLIP_EN 0x0200
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#define AR_EEPROM_EEPCAP_KC_ENTRIES 0xF000
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#define AR_EEPROM_EEPCAP_KC_ENTRIES_S 12
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/* XXX used to index various EEPROM-derived data structures */
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enum {
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headerInfo11A = 0,
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headerInfo11B = 1,
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headerInfo11G = 2,
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};
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#define GROUPS_OFFSET3_2 0x100 /* groups offset for ver3.2 and earlier */
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#define GROUPS_OFFSET3_3 0x150 /* groups offset for ver3.3 */
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/* relative offset of GROUPi to GROUPS_OFFSET */
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#define GROUP1_OFFSET 0x0
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#define GROUP2_OFFSET 0x5
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#define GROUP3_OFFSET 0x37
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#define GROUP4_OFFSET 0x46
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#define GROUP5_OFFSET 0x55
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#define GROUP6_OFFSET 0x65
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#define GROUP7_OFFSET 0x69
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#define GROUP8_OFFSET 0x6f
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/* RF silent fields in EEPROM */
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#define AR_EEPROM_RFSILENT_GPIO_SEL 0x001c
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#define AR_EEPROM_RFSILENT_GPIO_SEL_S 2
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#define AR_EEPROM_RFSILENT_POLARITY 0x0002
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#define AR_EEPROM_RFSILENT_POLARITY_S 1
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/* Protect Bits RP is read protect, WP is write protect */
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#define AR_EEPROM_PROTECT_RP_0_31 0x0001
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#define AR_EEPROM_PROTECT_WP_0_31 0x0002
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#define AR_EEPROM_PROTECT_RP_32_63 0x0004
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#define AR_EEPROM_PROTECT_WP_32_63 0x0008
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#define AR_EEPROM_PROTECT_RP_64_127 0x0010
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#define AR_EEPROM_PROTECT_WP_64_127 0x0020
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#define AR_EEPROM_PROTECT_RP_128_191 0x0040
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#define AR_EEPROM_PROTECT_WP_128_191 0x0080
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#define AR_EEPROM_PROTECT_RP_192_207 0x0100
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#define AR_EEPROM_PROTECT_WP_192_207 0x0200
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#define AR_EEPROM_PROTECT_RP_208_223 0x0400
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#define AR_EEPROM_PROTECT_WP_208_223 0x0800
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#define AR_EEPROM_PROTECT_RP_224_239 0x1000
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#define AR_EEPROM_PROTECT_WP_224_239 0x2000
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#define AR_EEPROM_PROTECT_RP_240_255 0x4000
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#define AR_EEPROM_PROTECT_WP_240_255 0x8000
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#define AR_EEPROM_MODAL_SPURS 5
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#define AR_SPUR_5413_1 1640 /* Freq 2464 */
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#define AR_SPUR_5413_2 1200 /* Freq 2420 */
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/*
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* EEPROM fixed point conversion scale factors.
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* NB: if you change one be sure to keep the other in sync.
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*/
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#define EEP_SCALE 100 /* conversion scale to avoid fp arith */
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#define EEP_DELTA 10 /* SCALE/10, to avoid arith divide */
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#define PWR_MIN 0
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#define PWR_MAX 3150 /* 31.5 * SCALE */
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#define PWR_STEP 50 /* 0.5 * SCALE */
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/* Keep 2 above defines together */
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#define NUM_11A_EEPROM_CHANNELS 10
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#define NUM_2_4_EEPROM_CHANNELS 3
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#define NUM_PCDAC_VALUES 11
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#define NUM_TEST_FREQUENCIES 8
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#define NUM_EDGES 8
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#define NUM_INTERCEPTS 11
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#define FREQ_MASK 0x7f
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#define FREQ_MASK_3_3 0xff /* expanded in version 3.3 */
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#define PCDAC_MASK 0x3f
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#define POWER_MASK 0x3f
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#define NON_EDGE_FLAG_MASK 0x40
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#define CHANNEL_POWER_INFO 8
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#define OBDB_UNSET 0xffff
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#define CHANNEL_UNUSED 0xff
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#define SCALE_OC_DELTA(_x) (((_x) * 2) / 10)
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/* Used during pcdac table construction */
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#define PCDAC_START 1
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#define PCDAC_STOP 63
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#define PCDAC_STEP 1
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#define PWR_TABLE_SIZE 64
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#define MAX_RATE_POWER 63
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/* Used during power/rate table construction */
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#define NUM_CTLS 16
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#define NUM_CTLS_3_3 32 /* expanded in version 3.3 */
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#define NUM_CTLS_MAX NUM_CTLS_3_3
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typedef struct fullPcdacStruct {
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uint16_t channelValue;
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uint16_t pcdacMin;
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uint16_t pcdacMax;
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uint16_t numPcdacValues;
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uint16_t PcdacValues[64];
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/* power is 32bit since in dest it is scaled */
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int16_t PwrValues[64];
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} FULL_PCDAC_STRUCT;
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typedef struct dataPerChannel {
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uint16_t channelValue;
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uint16_t pcdacMin;
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uint16_t pcdacMax;
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uint16_t numPcdacValues;
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uint16_t PcdacValues[NUM_PCDAC_VALUES];
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/* NB: power is 32bit since in dest it is scaled */
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int16_t PwrValues[NUM_PCDAC_VALUES];
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} DATA_PER_CHANNEL;
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/* points to the appropriate pcdac structs in the above struct based on mode */
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typedef struct pcdacsEeprom {
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const uint16_t *pChannelList;
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uint16_t numChannels;
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const DATA_PER_CHANNEL *pDataPerChannel;
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} PCDACS_EEPROM;
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typedef struct trgtPowerInfo {
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uint16_t twicePwr54;
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uint16_t twicePwr48;
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uint16_t twicePwr36;
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uint16_t twicePwr6_24;
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uint16_t testChannel;
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} TRGT_POWER_INFO;
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typedef struct trgtPowerAllModes {
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uint16_t numTargetPwr_11a;
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TRGT_POWER_INFO trgtPwr_11a[NUM_TEST_FREQUENCIES];
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uint16_t numTargetPwr_11g;
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TRGT_POWER_INFO trgtPwr_11g[3];
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uint16_t numTargetPwr_11b;
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TRGT_POWER_INFO trgtPwr_11b[2];
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} TRGT_POWER_ALL_MODES;
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typedef struct cornerCalInfo {
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uint16_t gSel;
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uint16_t pd84;
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uint16_t pd90;
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uint16_t clip;
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} CORNER_CAL_INFO;
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/*
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* EEPROM version 4 definitions
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*/
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#define NUM_XPD_PER_CHANNEL 4
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#define NUM_POINTS_XPD0 4
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#define NUM_POINTS_XPD3 3
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#define IDEAL_10dB_INTERCEPT_2G 35
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#define IDEAL_10dB_INTERCEPT_5G 55
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#define TENX_OFDM_CCK_DELTA_INIT 15 /* power 1.5 dbm */
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#define TENX_CH14_FILTER_CCK_DELTA_INIT 15 /* power 1.5 dbm */
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#define CCK_OFDM_GAIN_DELTA 15
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#define NUM_TARGET_POWER_LOCATIONS_11B 4
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#define NUM_TARGET_POWER_LOCATIONS_11G 6
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typedef struct {
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uint16_t xpd_gain;
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uint16_t numPcdacs;
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uint16_t pcdac[NUM_POINTS_XPD0];
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int16_t pwr_t4[NUM_POINTS_XPD0]; /* or gainF */
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} EXPN_DATA_PER_XPD_5112;
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typedef struct {
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uint16_t channelValue;
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int16_t maxPower_t4;
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EXPN_DATA_PER_XPD_5112 pDataPerXPD[NUM_XPD_PER_CHANNEL];
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} EXPN_DATA_PER_CHANNEL_5112;
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typedef struct {
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uint16_t *pChannels;
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uint16_t numChannels;
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uint16_t xpdMask; /* mask of permitted xpd_gains */
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EXPN_DATA_PER_CHANNEL_5112 *pDataPerChannel;
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} EEPROM_POWER_EXPN_5112;
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typedef struct {
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uint16_t channelValue;
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uint16_t pcd1_xg0;
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int16_t pwr1_xg0;
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uint16_t pcd2_delta_xg0;
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int16_t pwr2_xg0;
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uint16_t pcd3_delta_xg0;
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int16_t pwr3_xg0;
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uint16_t pcd4_delta_xg0;
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int16_t pwr4_xg0;
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int16_t maxPower_t4;
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int16_t pwr1_xg3; /* pcdac = 20 */
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int16_t pwr2_xg3; /* pcdac = 35 */
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int16_t pwr3_xg3; /* pcdac = 63 */
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/* XXX - Should be pwr1_xg2, etc to agree with documentation */
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} EEPROM_DATA_PER_CHANNEL_5112;
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typedef struct {
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uint16_t pChannels[NUM_11A_EEPROM_CHANNELS];
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uint16_t numChannels;
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uint16_t xpdMask; /* mask of permitted xpd_gains */
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EEPROM_DATA_PER_CHANNEL_5112 pDataPerChannel[NUM_11A_EEPROM_CHANNELS];
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} EEPROM_POWER_5112;
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/*
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* EEPROM version 5 definitions (Griffin, et. al.).
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*/
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#define NUM_2_4_EEPROM_CHANNELS_2413 4
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#define NUM_11A_EEPROM_CHANNELS_2413 10
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#define PWR_TABLE_SIZE_2413 128
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/* Used during pdadc construction */
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#define MAX_NUM_PDGAINS_PER_CHANNEL 4
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#define NUM_PDGAINS_PER_CHANNEL 2
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#define NUM_POINTS_LAST_PDGAIN 5
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#define NUM_POINTS_OTHER_PDGAINS 4
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#define XPD_GAIN1_GEN5 3
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#define XPD_GAIN2_GEN5 1
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#define MAX_PWR_RANGE_IN_HALF_DB 64
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#define PD_GAIN_BOUNDARY_STRETCH_IN_HALF_DB 4
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typedef struct {
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uint16_t pd_gain;
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uint16_t numVpd;
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uint16_t Vpd[NUM_POINTS_LAST_PDGAIN];
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int16_t pwr_t4[NUM_POINTS_LAST_PDGAIN]; /* or gainF */
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} RAW_DATA_PER_PDGAIN_2413;
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typedef struct {
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uint16_t channelValue;
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int16_t maxPower_t4;
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uint16_t numPdGains; /* # Pd Gains per channel */
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RAW_DATA_PER_PDGAIN_2413 pDataPerPDGain[MAX_NUM_PDGAINS_PER_CHANNEL];
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} RAW_DATA_PER_CHANNEL_2413;
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/* XXX: assumes NUM_11A_EEPROM_CHANNELS_2413 >= NUM_2_4_EEPROM_CHANNELS_2413 ??? */
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typedef struct {
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uint16_t pChannels[NUM_11A_EEPROM_CHANNELS_2413];
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uint16_t numChannels;
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uint16_t xpd_mask; /* mask of permitted xpd_gains */
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RAW_DATA_PER_CHANNEL_2413 pDataPerChannel[NUM_11A_EEPROM_CHANNELS_2413];
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} RAW_DATA_STRUCT_2413;
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typedef struct {
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uint16_t channelValue;
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uint16_t numPdGains;
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uint16_t Vpd_I[MAX_NUM_PDGAINS_PER_CHANNEL];
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int16_t pwr_I[MAX_NUM_PDGAINS_PER_CHANNEL];
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uint16_t Vpd_delta[NUM_POINTS_LAST_PDGAIN]
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[MAX_NUM_PDGAINS_PER_CHANNEL];
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int16_t pwr_delta_t2[NUM_POINTS_LAST_PDGAIN]
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[MAX_NUM_PDGAINS_PER_CHANNEL];
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int16_t maxPower_t4;
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} EEPROM_DATA_PER_CHANNEL_2413;
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typedef struct {
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uint16_t pChannels[NUM_11A_EEPROM_CHANNELS_2413];
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uint16_t numChannels;
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uint16_t xpd_mask; /* mask of permitted xpd_gains */
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EEPROM_DATA_PER_CHANNEL_2413 pDataPerChannel[NUM_11A_EEPROM_CHANNELS_2413];
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} EEPROM_DATA_STRUCT_2413;
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/*
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* Information retrieved from EEPROM.
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*/
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typedef struct {
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uint16_t ee_version; /* Version field */
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uint16_t ee_protect; /* EEPROM protect field */
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uint16_t ee_regdomain; /* Regulatory domain */
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/* General Device Parameters */
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uint16_t ee_turbo5Disable;
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uint16_t ee_turbo2Disable;
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uint16_t ee_rfKill;
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uint16_t ee_deviceType;
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uint16_t ee_turbo2WMaxPower5;
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uint16_t ee_turbo2WMaxPower2;
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uint16_t ee_xrTargetPower5;
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uint16_t ee_xrTargetPower2;
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uint16_t ee_Amode;
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uint16_t ee_regCap;
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uint16_t ee_Bmode;
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uint16_t ee_Gmode;
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int8_t ee_antennaGainMax[2];
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uint16_t ee_xtnd5GSupport;
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uint8_t ee_cckOfdmPwrDelta;
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uint8_t ee_exist32kHzCrystal;
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uint16_t ee_targetPowersStart;
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uint16_t ee_fixedBias5;
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uint16_t ee_fixedBias2;
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uint16_t ee_cckOfdmGainDelta;
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uint16_t ee_scaledCh14FilterCckDelta;
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uint16_t ee_eepMap;
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uint16_t ee_earStart;
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/* 5 GHz / 2.4 GHz CKK / 2.4 GHz OFDM common parameters */
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uint16_t ee_switchSettling[3];
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uint16_t ee_txrxAtten[3];
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uint16_t ee_txEndToXLNAOn[3];
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uint16_t ee_thresh62[3];
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uint16_t ee_txEndToXPAOff[3];
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uint16_t ee_txFrameToXPAOn[3];
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int8_t ee_adcDesiredSize[3]; /* 8-bit signed value */
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int8_t ee_pgaDesiredSize[3]; /* 8-bit signed value */
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int16_t ee_noiseFloorThresh[3];
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uint16_t ee_xlnaGain[3];
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uint16_t ee_xgain[3];
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uint16_t ee_xpd[3];
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uint16_t ee_antennaControl[11][3];
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uint16_t ee_falseDetectBackoff[3];
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uint16_t ee_gainI[3];
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uint16_t ee_rxtxMargin[3];
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/* new parameters added for the AR2413 */
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HAL_BOOL ee_disableXr5;
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HAL_BOOL ee_disableXr2;
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uint16_t ee_eepMap2PowerCalStart;
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uint16_t ee_capField;
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uint16_t ee_switchSettlingTurbo[2];
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uint16_t ee_txrxAttenTurbo[2];
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int8_t ee_adcDesiredSizeTurbo[2];
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int8_t ee_pgaDesiredSizeTurbo[2];
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uint16_t ee_rxtxMarginTurbo[2];
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/* 5 GHz parameters */
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uint16_t ee_ob1;
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uint16_t ee_db1;
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uint16_t ee_ob2;
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uint16_t ee_db2;
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uint16_t ee_ob3;
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uint16_t ee_db3;
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uint16_t ee_ob4;
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uint16_t ee_db4;
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/* 2.4 GHz parameters */
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uint16_t ee_obFor24;
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uint16_t ee_dbFor24;
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uint16_t ee_obFor24g;
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uint16_t ee_dbFor24g;
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uint16_t ee_ob2GHz[2];
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uint16_t ee_db2GHz[2];
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uint16_t ee_numCtls;
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uint16_t ee_ctl[NUM_CTLS_MAX];
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uint16_t ee_iqCalI[2];
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uint16_t ee_iqCalQ[2];
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uint16_t ee_calPier11g[NUM_2_4_EEPROM_CHANNELS];
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uint16_t ee_calPier11b[NUM_2_4_EEPROM_CHANNELS];
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/* corner calibration information */
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CORNER_CAL_INFO ee_cornerCal;
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uint16_t ee_opCap;
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/* 11a info */
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uint16_t ee_channels11a[NUM_11A_EEPROM_CHANNELS];
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uint16_t ee_numChannels11a;
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DATA_PER_CHANNEL ee_dataPerChannel11a[NUM_11A_EEPROM_CHANNELS];
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uint16_t ee_numChannels2_4;
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uint16_t ee_channels11g[NUM_2_4_EEPROM_CHANNELS];
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uint16_t ee_channels11b[NUM_2_4_EEPROM_CHANNELS];
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uint16_t ee_spurChans[AR_EEPROM_MODAL_SPURS][2];
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/* 11g info */
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DATA_PER_CHANNEL ee_dataPerChannel11g[NUM_2_4_EEPROM_CHANNELS];
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/* 11b info */
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DATA_PER_CHANNEL ee_dataPerChannel11b[NUM_2_4_EEPROM_CHANNELS];
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TRGT_POWER_ALL_MODES ee_tpow;
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RD_EDGES_POWER ee_rdEdgesPower[NUM_EDGES*NUM_CTLS_MAX];
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union {
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EEPROM_POWER_EXPN_5112 eu_modePowerArray5112[3];
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RAW_DATA_STRUCT_2413 eu_rawDataset2413[3];
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} ee_u;
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} HAL_EEPROM;
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/* write-around defines */
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#define ee_numTargetPwr_11a ee_tpow.numTargetPwr_11a
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#define ee_trgtPwr_11a ee_tpow.trgtPwr_11a
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#define ee_numTargetPwr_11g ee_tpow.numTargetPwr_11g
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#define ee_trgtPwr_11g ee_tpow.trgtPwr_11g
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#define ee_numTargetPwr_11b ee_tpow.numTargetPwr_11b
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#define ee_trgtPwr_11b ee_tpow.trgtPwr_11b
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#define ee_modePowerArray5112 ee_u.eu_modePowerArray5112
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#define ee_rawDataset2413 ee_u.eu_rawDataset2413
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#endif /* _ATH_AH_EEPROM_V3_H_ */
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