mirror of
https://github.com/proski/madwifi
synced 2025-02-19 16:54:18 +03:00
Port ah_writeIni and ar5416SpurMitigate from FreeBSD HAL
git-svn-id: http://madwifi-project.org/svn/madwifi/trunk@4106 0192ed92-7a03-0410-a25b-9323aeb14dbd
This commit is contained in:
proski
parent
da9812696d
commit
00b7ee3649
@ -582,6 +582,17 @@ extern void ath_hal_assert_failed(const char* filename,
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#define HALASSERT(_x)
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#endif /* AH_ASSERT */
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/*
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* Return the h/w frequency for a channel. This may be
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* different from ic_freq if this is a GSM device that
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* takes 2.4GHz frequencies and down-converts them.
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*/
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static OS_INLINE uint16_t
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ath_hal_gethwchannel(struct ath_hal *ah, const HAL_CHANNEL *c)
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{
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return ath_hal_checkchannel(ah, c)->channel;
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}
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/*
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* Convert between microseconds and core system clocks.
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*/
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@ -45,6 +45,8 @@ typedef struct {
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#define AR5416_CCA_MAX_HIGH_VALUE -62
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#define AR5416_CCA_MIN_BAD_VALUE -140
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#define AR5416_SPUR_RSSI_THRESH 40
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struct ath_hal_5416 {
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struct ath_hal_5212 ah_5212;
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@ -59,6 +61,11 @@ struct ath_hal_5416 {
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HAL_INI_ARRAY ah_ini_addac;
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HAL_INI_ARRAY ah_ini_pcieserdes;
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void (*ah_writeIni)(struct ath_hal *,
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const HAL_CHANNEL *);
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void (*ah_spurMitigate)(struct ath_hal *,
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HAL_CHANNEL_INTERNAL *);
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u_int ah_globaltxtimeout; /* global tx timeout */
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int ah_hangs; /* h/w hangs state */
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uint8_t ah_keytype[AR5416_KEYTABLE_SIZE];
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@ -22,6 +22,8 @@
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#include "ah_internal.h"
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#include "ah_devid.h"
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#include "ah_eeprom_v14.h"
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#include "ar5416/ar5416.h"
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#include "ar5416/ar5416reg.h"
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#include "ar5416/ar5416phy.h"
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@ -29,6 +31,10 @@
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#include "ar5416/ar5416.ini"
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static void ar5416ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore);
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static void ar5416WriteIni(struct ath_hal *ah,
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const HAL_CHANNEL *chan);
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static void ar5416SpurMitigate(struct ath_hal *ah,
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HAL_CHANNEL_INTERNAL *chan);
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static void
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ar5416AniSetup(struct ath_hal *ah)
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@ -157,6 +163,8 @@ ar5416InitState(struct ath_hal_5416 *ahp5416, uint16_t devid, HAL_SOFTC sc,
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ahp->ah_priv.ah_gpioSetIntr = ar5416GpioSetIntr;
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ahp->ah_priv.ah_getChipPowerLimits = ar5416GetChipPowerLimits;
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AH5416(ah)->ah_writeIni = ar5416WriteIni;
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AH5416(ah)->ah_spurMitigate = ar5416SpurMitigate;
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/*
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* Start by setting all Owl devices to 2x2
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*/
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@ -400,6 +408,301 @@ ar5416ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore)
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}
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}
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static void
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ar5416WriteIni(struct ath_hal *ah, const HAL_CHANNEL *chan)
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{
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u_int modesIndex, freqIndex;
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int regWrites = 0;
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/* Setup the indices for the next set of register array writes */
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/* XXX Ignore 11n dynamic mode on the AR5416 for the moment */
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if (IS_CHAN_2GHZ(chan)) {
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freqIndex = 2;
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if (IS_CHAN_HT40(chan))
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modesIndex = 3;
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else if (IS_CHAN_108G(chan))
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modesIndex = 5;
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else
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modesIndex = 4;
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} else {
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freqIndex = 1;
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if (IS_CHAN_HT40(chan) ||
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IS_CHAN_TURBO(chan))
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modesIndex = 2;
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else
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modesIndex = 1;
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}
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/* Set correct Baseband to analog shift setting to access analog chips. */
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OS_REG_WRITE(ah, AR_PHY(0), 0x00000007);
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/*
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* Write addac shifts
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*/
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OS_REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_EXTERNAL_RADIO);
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#if 0
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/* NB: only required for Sowl */
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ar5416EepromSetAddac(ah, chan);
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#endif
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regWrites = ath_hal_ini_write(ah, &AH5416(ah)->ah_ini_addac, 1,
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regWrites);
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OS_REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC);
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regWrites = ath_hal_ini_write(ah, &AH5212(ah)->ah_ini_modes,
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modesIndex, regWrites);
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regWrites = ath_hal_ini_write(ah, &AH5212(ah)->ah_ini_common,
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1, regWrites);
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/* XXX updated regWrites? */
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AH5212(ah)->ah_rfHal->writeRegs(ah, modesIndex, freqIndex, regWrites);
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}
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/*
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* Convert to baseband spur frequency given input channel frequency
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* and compute register settings below.
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*/
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static void
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ar5416SpurMitigate(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *chan)
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{
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uint16_t freq = ath_hal_gethwchannel(ah, (HAL_CHANNEL *) chan);
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static const int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
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AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60 };
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static const int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
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AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60 };
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static const int inc[4] = { 0, 100, 0, 0 };
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int bb_spur = AR_NO_SPUR;
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int bin, cur_bin;
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int spur_freq_sd;
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int spur_delta_phase;
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int denominator;
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int upper, lower, cur_vit_mask;
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int tmp, new;
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int i;
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int8_t mask_m[123];
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int8_t mask_p[123];
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int8_t mask_amt;
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int tmp_mask;
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int cur_bb_spur;
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HAL_BOOL is2GHz = IS_CHAN_2GHZ(chan);
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OS_MEMZERO(mask_m, sizeof(mask_m));
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OS_MEMZERO(mask_p, sizeof(mask_p));
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/*
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* Need to verify range +/- 9.5 for static ht20, otherwise spur
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* is out-of-band and can be ignored.
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*/
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/* XXX ath9k changes */
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for (i = 0; i < AR5416_EEPROM_MODAL_SPURS; i++) {
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cur_bb_spur = ath_hal_getSpurChan(ah, i, is2GHz);
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if (AR_NO_SPUR == cur_bb_spur)
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break;
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cur_bb_spur = cur_bb_spur - (freq * 10);
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if ((cur_bb_spur > -95) && (cur_bb_spur < 95)) {
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bb_spur = cur_bb_spur;
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break;
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}
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}
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if (AR_NO_SPUR == bb_spur)
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return;
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bin = bb_spur * 32;
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tmp = OS_REG_READ(ah, AR_PHY_TIMING_CTRL4_CHAIN(0));
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new = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
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AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
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AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
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AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
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OS_REG_WRITE(ah, AR_PHY_TIMING_CTRL4_CHAIN(0), new);
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new = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
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AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
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AR_PHY_SPUR_REG_MASK_RATE_SELECT |
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AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
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SM(AR5416_SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
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OS_REG_WRITE(ah, AR_PHY_SPUR_REG, new);
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/*
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* Should offset bb_spur by +/- 10 MHz for dynamic 2040 MHz
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* config, no offset for HT20.
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* spur_delta_phase = bb_spur/40 * 2**21 for static ht20,
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* /80 for dyn2040.
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*/
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spur_delta_phase = ((bb_spur * 524288) / 100) &
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AR_PHY_TIMING11_SPUR_DELTA_PHASE;
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/*
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* in 11A mode the denominator of spur_freq_sd should be 40 and
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* it should be 44 in 11G
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*/
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denominator = IS_CHAN_2GHZ(chan) ? 440 : 400;
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spur_freq_sd = ((bb_spur * 2048) / denominator) & 0x3ff;
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new = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
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SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
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SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
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OS_REG_WRITE(ah, AR_PHY_TIMING11, new);
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/*
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* ============================================
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* pilot mask 1 [31:0] = +6..-26, no 0 bin
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* pilot mask 2 [19:0] = +26..+7
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*
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* channel mask 1 [31:0] = +6..-26, no 0 bin
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* channel mask 2 [19:0] = +26..+7
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*/
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//cur_bin = -26;
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cur_bin = -6000;
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upper = bin + 100;
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lower = bin - 100;
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for (i = 0; i < 4; i++) {
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int pilot_mask = 0;
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int chan_mask = 0;
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int bp = 0;
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for (bp = 0; bp < 30; bp++) {
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if ((cur_bin > lower) && (cur_bin < upper)) {
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pilot_mask = pilot_mask | 0x1 << bp;
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chan_mask = chan_mask | 0x1 << bp;
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}
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cur_bin += 100;
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}
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cur_bin += inc[i];
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OS_REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
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OS_REG_WRITE(ah, chan_mask_reg[i], chan_mask);
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}
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/* =================================================
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* viterbi mask 1 based on channel magnitude
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* four levels 0-3
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* - mask (-27 to 27) (reg 64,0x9900 to 67,0x990c)
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* [1 2 2 1] for -9.6 or [1 2 1] for +16
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* - enable_mask_ppm, all bins move with freq
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*
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* - mask_select, 8 bits for rates (reg 67,0x990c)
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* - mask_rate_cntl, 8 bits for rates (reg 67,0x990c)
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* choose which mask to use mask or mask2
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*/
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/*
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* viterbi mask 2 2nd set for per data rate puncturing
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* four levels 0-3
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* - mask_select, 8 bits for rates (reg 67)
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* - mask (-27 to 27) (reg 98,0x9988 to 101,0x9994)
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* [1 2 2 1] for -9.6 or [1 2 1] for +16
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*/
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cur_vit_mask = 6100;
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upper = bin + 120;
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lower = bin - 120;
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for (i = 0; i < 123; i++) {
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if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
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if ((abs(cur_vit_mask - bin)) < 75) {
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mask_amt = 1;
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} else {
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mask_amt = 0;
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}
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if (cur_vit_mask < 0) {
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mask_m[abs(cur_vit_mask / 100)] = mask_amt;
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} else {
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mask_p[cur_vit_mask / 100] = mask_amt;
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}
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}
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cur_vit_mask -= 100;
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}
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tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
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| (mask_m[48] << 26) | (mask_m[49] << 24)
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| (mask_m[50] << 22) | (mask_m[51] << 20)
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| (mask_m[52] << 18) | (mask_m[53] << 16)
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| (mask_m[54] << 14) | (mask_m[55] << 12)
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| (mask_m[56] << 10) | (mask_m[57] << 8)
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| (mask_m[58] << 6) | (mask_m[59] << 4)
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| (mask_m[60] << 2) | (mask_m[61] << 0);
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OS_REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
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OS_REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
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tmp_mask = (mask_m[31] << 28)
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| (mask_m[32] << 26) | (mask_m[33] << 24)
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| (mask_m[34] << 22) | (mask_m[35] << 20)
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| (mask_m[36] << 18) | (mask_m[37] << 16)
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| (mask_m[48] << 14) | (mask_m[39] << 12)
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| (mask_m[40] << 10) | (mask_m[41] << 8)
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| (mask_m[42] << 6) | (mask_m[43] << 4)
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| (mask_m[44] << 2) | (mask_m[45] << 0);
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OS_REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
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OS_REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
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tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
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| (mask_m[18] << 26) | (mask_m[18] << 24)
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| (mask_m[20] << 22) | (mask_m[20] << 20)
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| (mask_m[22] << 18) | (mask_m[22] << 16)
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| (mask_m[24] << 14) | (mask_m[24] << 12)
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| (mask_m[25] << 10) | (mask_m[26] << 8)
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| (mask_m[27] << 6) | (mask_m[28] << 4)
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| (mask_m[29] << 2) | (mask_m[30] << 0);
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OS_REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
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OS_REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
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tmp_mask = (mask_m[ 0] << 30) | (mask_m[ 1] << 28)
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| (mask_m[ 2] << 26) | (mask_m[ 3] << 24)
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| (mask_m[ 4] << 22) | (mask_m[ 5] << 20)
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| (mask_m[ 6] << 18) | (mask_m[ 7] << 16)
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| (mask_m[ 8] << 14) | (mask_m[ 9] << 12)
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| (mask_m[10] << 10) | (mask_m[11] << 8)
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| (mask_m[12] << 6) | (mask_m[13] << 4)
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| (mask_m[14] << 2) | (mask_m[15] << 0);
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OS_REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
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OS_REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
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tmp_mask = (mask_p[15] << 28)
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| (mask_p[14] << 26) | (mask_p[13] << 24)
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| (mask_p[12] << 22) | (mask_p[11] << 20)
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| (mask_p[10] << 18) | (mask_p[ 9] << 16)
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| (mask_p[ 8] << 14) | (mask_p[ 7] << 12)
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| (mask_p[ 6] << 10) | (mask_p[ 5] << 8)
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| (mask_p[ 4] << 6) | (mask_p[ 3] << 4)
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| (mask_p[ 2] << 2) | (mask_p[ 1] << 0);
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OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
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OS_REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
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tmp_mask = (mask_p[30] << 28)
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| (mask_p[29] << 26) | (mask_p[28] << 24)
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| (mask_p[27] << 22) | (mask_p[26] << 20)
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| (mask_p[25] << 18) | (mask_p[24] << 16)
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| (mask_p[23] << 14) | (mask_p[22] << 12)
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| (mask_p[21] << 10) | (mask_p[20] << 8)
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| (mask_p[19] << 6) | (mask_p[18] << 4)
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| (mask_p[17] << 2) | (mask_p[16] << 0);
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OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
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OS_REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
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tmp_mask = (mask_p[45] << 28)
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| (mask_p[44] << 26) | (mask_p[43] << 24)
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| (mask_p[42] << 22) | (mask_p[41] << 20)
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| (mask_p[40] << 18) | (mask_p[39] << 16)
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| (mask_p[38] << 14) | (mask_p[37] << 12)
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| (mask_p[36] << 10) | (mask_p[35] << 8)
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| (mask_p[34] << 6) | (mask_p[33] << 4)
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| (mask_p[32] << 2) | (mask_p[31] << 0);
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OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
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OS_REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
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tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
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| (mask_p[59] << 26) | (mask_p[58] << 24)
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| (mask_p[57] << 22) | (mask_p[56] << 20)
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| (mask_p[55] << 18) | (mask_p[54] << 16)
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| (mask_p[53] << 14) | (mask_p[52] << 12)
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| (mask_p[51] << 10) | (mask_p[50] << 8)
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| (mask_p[49] << 6) | (mask_p[48] << 4)
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| (mask_p[47] << 2) | (mask_p[46] << 0);
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OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
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OS_REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
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}
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/*
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* Fill all software cached or static hardware state information.
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* Return failure if capabilities are to come from EEPROM and
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