mirror of
https://github.com/limine-bootloader/limine
synced 2024-12-09 08:24:35 +03:00
178 lines
4.1 KiB
C
178 lines
4.1 KiB
C
#include <stdint.h>
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#include <stddef.h>
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#include <stdbool.h>
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#include <sys/lapic.h>
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#include <sys/cpu.h>
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#include <lib/blib.h>
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#include <lib/acpi.h>
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#include <mm/pmm.h>
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struct madt {
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struct sdt header;
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uint32_t local_controller_addr;
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uint32_t flags;
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char madt_entries_begin[];
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} __attribute__((packed));
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struct madt_io_apic {
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uint8_t type;
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uint8_t length;
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uint8_t apic_id;
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uint8_t reserved;
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uint32_t address;
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uint32_t gsib;
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} __attribute__((packed));
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struct dmar {
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struct sdt header;
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uint8_t host_address_width;
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uint8_t flags;
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uint8_t reserved[10];
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symbol remapping_structures;
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} __attribute__((packed));
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bool lapic_check(void) {
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uint32_t eax, ebx, ecx, edx;
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if (!cpuid(1, 0, &eax, &ebx, &ecx, &edx))
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return false;
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if (!(edx & (1 << 9)))
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return false;
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return true;
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}
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uint32_t lapic_read(uint32_t reg) {
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size_t lapic_mmio_base = (size_t)(rdmsr(0x1b) & 0xfffff000);
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return mmind(lapic_mmio_base + reg);
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}
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void lapic_write(uint32_t reg, uint32_t data) {
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size_t lapic_mmio_base = (size_t)(rdmsr(0x1b) & 0xfffff000);
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mmoutd(lapic_mmio_base + reg, data);
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}
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bool x2apic_check(void) {
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uint32_t eax, ebx, ecx, edx;
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if (!cpuid(1, 0, &eax, &ebx, &ecx, &edx))
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return false;
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if (!(ecx & (1 << 21)))
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return false;
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// According to the Intel VT-d spec, we're required
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// to check if bit 0 and 1 of the flags field of the
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// DMAR ACPI table are set, and if they are, we should
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// not report x2APIC capabilities.
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struct dmar *dmar = acpi_get_table("DMAR", 0);
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if (!dmar)
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return true;
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if ((dmar->flags & (1 << 0)) && (dmar->flags & (1 << 1)))
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return false;
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return true;
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}
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static bool x2apic_mode = false;
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bool x2apic_enable(void) {
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if (!x2apic_check())
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return false;
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uint64_t ia32_apic_base = rdmsr(0x1b);
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ia32_apic_base |= (1 << 10);
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wrmsr(0x1b, ia32_apic_base);
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x2apic_mode = true;
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return true;
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}
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void lapic_eoi(void) {
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if (!x2apic_mode) {
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lapic_write(0xb0, 0);
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} else {
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x2apic_write(0xb0, 0);
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}
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}
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uint64_t x2apic_read(uint32_t reg) {
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return rdmsr(0x800 + (reg >> 4));
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}
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void x2apic_write(uint32_t reg, uint64_t data) {
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wrmsr(0x800 + (reg >> 4), data);
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}
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static struct madt_io_apic **io_apics = NULL;
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static size_t max_io_apics = 0;
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void init_io_apics(void) {
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static bool already_inited = false;
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if (already_inited) {
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return;
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}
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struct madt *madt = acpi_get_table("APIC", 0);
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if (madt == NULL) {
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goto out;
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}
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for (uint8_t *madt_ptr = (uint8_t *)madt->madt_entries_begin;
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(uintptr_t)madt_ptr < (uintptr_t)madt + madt->header.length;
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madt_ptr += *(madt_ptr + 1)) {
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switch (*madt_ptr) {
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case 1: {
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max_io_apics++;
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continue;
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}
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}
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}
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io_apics = ext_mem_alloc(max_io_apics * sizeof(struct madt_io_apic *));
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max_io_apics = 0;
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for (uint8_t *madt_ptr = (uint8_t *)madt->madt_entries_begin;
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(uintptr_t)madt_ptr < (uintptr_t)madt + madt->header.length;
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madt_ptr += *(madt_ptr + 1)) {
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switch (*madt_ptr) {
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case 1: {
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io_apics[max_io_apics++] = (void *)madt_ptr;
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continue;
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}
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}
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}
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out:
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already_inited = true;
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}
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uint32_t io_apic_read(size_t io_apic, uint32_t reg) {
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uintptr_t base = (uintptr_t)io_apics[io_apic]->address;
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mmoutd(base, reg);
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return mmind(base + 16);
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}
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void io_apic_write(size_t io_apic, uint32_t reg, uint32_t value) {
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uintptr_t base = (uintptr_t)io_apics[io_apic]->address;
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mmoutd(base, reg);
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mmoutd(base + 16, value);
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}
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uint32_t io_apic_gsi_count(size_t io_apic) {
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return ((io_apic_read(io_apic, 1) & 0xff0000) >> 16) + 1;
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}
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void io_apic_mask_all(void) {
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for (size_t i = 0; i < max_io_apics; i++) {
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uint32_t gsi_count = io_apic_gsi_count(i);
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for (uint32_t j = 0; j < gsi_count; j++) {
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uintptr_t ioredtbl = j * 2 + 16;
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io_apic_write(i, ioredtbl, (1 << 16)); // mask
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io_apic_write(i, ioredtbl + 1, 0);
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}
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}
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}
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