mirror of
https://github.com/limine-bootloader/limine
synced 2024-12-12 17:47:19 +03:00
e1f6ac8860
* Initial aarch64 port * Enable chainload on aarch64 No changes necessary since it's all UEFI anyway. * Add specification for Limine protocol for aarch64 * PROTOCOL: Specify state of information in DT /chosen node * common: Add spinup code for aarch64 * common: Port elf and term to aarch64 * common: Port vmm to aarch64 Also prepare to drop VMM_FLAG_PRESENT on x86. * protos: Port limine boot protocol to aarch64 Also drop VMM_FLAG_PRESENT since we never unmap pages anyway. * test: Add DTB request * PROTOCOL: Port SMP request to aarch64 * cpu: Add cache maintenance functions for aarch64 * protos/limine, sys: Port SMP to aarch64 Also move common asm macros into a header file. * test: Start up APs * vmm: Unify get_next_level and implement large page splitting * protos/limine: Map framebuffer using correct caching mode on AArch64 * CI: Fix GCC build for aarch64 * entry, menu: Replace uses of naked attribute with separate asm file GCC does not understand the naked attribute on aarch64, and didn't understand it for x86 in older versions.
74 lines
1.8 KiB
C
74 lines
1.8 KiB
C
#if defined (__x86_64__) || defined (__i386__)
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#include <stdint.h>
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#include <stddef.h>
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#include <sys/idt.h>
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#include <sys/cpu.h>
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#include <sys/pic.h>
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#include <sys/lapic.h>
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#include <mm/pmm.h>
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#include <lib/blib.h>
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static struct idt_entry *dummy_idt = NULL;
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void dummy_isr(void);
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void init_flush_irqs(void) {
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size_t dummy_idt_size = 256 * sizeof(struct idt_entry);
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dummy_idt = ext_mem_alloc(dummy_idt_size);
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for (size_t i = 0; i < 256; i++) {
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dummy_idt[i].offset_lo = (uint16_t)(uintptr_t)dummy_isr;
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dummy_idt[i].type_attr = 0x8e;
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#if defined (__i386__)
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dummy_idt[i].selector = 0x18;
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dummy_idt[i].offset_hi = (uint16_t)((uintptr_t)dummy_isr >> 16);
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#elif defined (__x86_64__)
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dummy_idt[i].selector = 0x28;
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dummy_idt[i].offset_mid = (uint16_t)((uintptr_t)dummy_isr >> 16);
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dummy_idt[i].offset_hi = (uint32_t)((uintptr_t)dummy_isr >> 32);
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#endif
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}
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pmm_free(dummy_idt, dummy_idt_size);
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}
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int irq_flush_type = IRQ_NO_FLUSH;
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void flush_irqs(void) {
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switch (irq_flush_type) {
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case IRQ_PIC_ONLY_FLUSH:
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pic_flush();
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// FALLTHRU
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case IRQ_NO_FLUSH:
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return;
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case IRQ_PIC_APIC_FLUSH:
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break;
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default:
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panic(false, "Invalid IRQ flush type");
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}
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struct idtr old_idt;
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asm volatile ("sidt %0" : "=m"(old_idt) :: "memory");
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struct idtr new_idt = {
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256 * sizeof(struct idt_entry) - 1,
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(uintptr_t)dummy_idt
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};
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asm volatile ("lidt %0" :: "m"(new_idt) : "memory");
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// Flush the legacy PIC so we know the remaining ints come from the LAPIC
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pic_flush();
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asm volatile ("sti" ::: "memory");
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// Delay a while to make sure we catch ALL pending IRQs
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delay(10000000);
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asm volatile ("cli" ::: "memory");
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asm volatile ("lidt %0" :: "m"(old_idt) : "memory");
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}
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#endif
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