limine/common/lib/mem.asm_aarch64
Kacper Słomiński e1f6ac8860
Initial AArch64 port (#205)
* Initial aarch64 port

* Enable chainload on aarch64

No changes necessary since it's all UEFI anyway.

* Add specification for Limine protocol for aarch64

* PROTOCOL: Specify state of information in DT /chosen node

* common: Add spinup code for aarch64

* common: Port elf and term to aarch64

* common: Port vmm to aarch64

Also prepare to drop VMM_FLAG_PRESENT on x86.

* protos: Port limine boot protocol to aarch64

Also drop VMM_FLAG_PRESENT since we never unmap pages anyway.

* test: Add DTB request

* PROTOCOL: Port SMP request to aarch64

* cpu: Add cache maintenance functions for aarch64

* protos/limine, sys: Port SMP to aarch64

Also move common asm macros into a header file.

* test: Start up APs

* vmm: Unify get_next_level and implement large page splitting

* protos/limine: Map framebuffer using correct caching mode on AArch64

* CI: Fix GCC build for aarch64

* entry, menu: Replace uses of naked attribute with separate asm file

GCC does not understand the naked attribute on aarch64, and didn't
understand it for x86 in older versions.
2022-08-18 17:32:54 +02:00

67 lines
819 B
Plaintext

.section .text
.global memcpy
memcpy:
mov x3, x0
0:
cbz x2, 1f
ldrb w4, [x1], #1
strb w4, [x0], #1
sub x2, x2, #1
b 0b
1:
mov x0, x3
ret
.global memset
memset:
mov x3, x0
0:
cbz x2, 1f
strb w1, [x0], #1
sub x2, x2, #1
b 0b
1:
mov x0, x3
ret
.global memmove
memmove:
mov x3, x0
mov x5, x2
cmp x0, x1
b.gt 1f
0:
cbz x2, 2f
ldrb w4, [x1], #1
strb w4, [x0], #1
sub x2, x2, #1
b 0b
1:
sub x5, x5, #1
cbz x2, 2f
ldrb w4, [x1, x5]
strb w4, [x0, x5]
sub x2, x2, #1
b 1b
2:
mov x0, x3
ret
.global memcmp
memcmp:
mov x3, xzr
0:
cbz x2, 1f
ldrb w3, [x0], #1
ldrb w4, [x1], #1
sub w3, w3, w4
cbnz w3, 1f
sub x2, x2, #1
b 0b
1:
sxtw x0, w3
mov x0, x3
ret