mirror of
https://github.com/limine-bootloader/limine
synced 2024-12-05 22:52:36 +03:00
e1f6ac8860
* Initial aarch64 port * Enable chainload on aarch64 No changes necessary since it's all UEFI anyway. * Add specification for Limine protocol for aarch64 * PROTOCOL: Specify state of information in DT /chosen node * common: Add spinup code for aarch64 * common: Port elf and term to aarch64 * common: Port vmm to aarch64 Also prepare to drop VMM_FLAG_PRESENT on x86. * protos: Port limine boot protocol to aarch64 Also drop VMM_FLAG_PRESENT since we never unmap pages anyway. * test: Add DTB request * PROTOCOL: Port SMP request to aarch64 * cpu: Add cache maintenance functions for aarch64 * protos/limine, sys: Port SMP to aarch64 Also move common asm macros into a header file. * test: Start up APs * vmm: Unify get_next_level and implement large page splitting * protos/limine: Map framebuffer using correct caching mode on AArch64 * CI: Fix GCC build for aarch64 * entry, menu: Replace uses of naked attribute with separate asm file GCC does not understand the naked attribute on aarch64, and didn't understand it for x86 in older versions.
53 lines
929 B
C
53 lines
929 B
C
// Branch to \el1 if in EL1, or to \el2 if in EL2
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// Uses \reg, halts if not in EL1 or EL2
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.macro PICK_EL reg, el1, el2
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mrs \reg, currentel
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and \reg, \reg, #0b1100
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cmp \reg, #0b0100 // EL1?
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b.eq \el1
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cmp \reg, #0b1000 // EL2?
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b.eq \el2
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// Halt otherwise
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msr daifset, #0b1111
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99:
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wfi
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b 99b
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.endm
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// Zero out all general purpose registers apart from X0
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.macro ZERO_REGS_EXCEPT_X0
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mov x1, xzr
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mov x2, xzr
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mov x3, xzr
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mov x4, xzr
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mov x5, xzr
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mov x6, xzr
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mov x7, xzr
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mov x8, xzr
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mov x9, xzr
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mov x10, xzr
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mov x11, xzr
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mov x12, xzr
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mov x13, xzr
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mov x14, xzr
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mov x15, xzr
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mov x16, xzr
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mov x17, xzr
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mov x18, xzr
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mov x19, xzr
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mov x20, xzr
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mov x21, xzr
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mov x22, xzr
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mov x23, xzr
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mov x24, xzr
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mov x25, xzr
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mov x26, xzr
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mov x27, xzr
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mov x28, xzr
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mov x29, xzr
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mov x30, xzr
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.endm
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