limine/common/lib/macros.aarch64_asm.h
Kacper Słomiński e1f6ac8860
Initial AArch64 port (#205)
* Initial aarch64 port

* Enable chainload on aarch64

No changes necessary since it's all UEFI anyway.

* Add specification for Limine protocol for aarch64

* PROTOCOL: Specify state of information in DT /chosen node

* common: Add spinup code for aarch64

* common: Port elf and term to aarch64

* common: Port vmm to aarch64

Also prepare to drop VMM_FLAG_PRESENT on x86.

* protos: Port limine boot protocol to aarch64

Also drop VMM_FLAG_PRESENT since we never unmap pages anyway.

* test: Add DTB request

* PROTOCOL: Port SMP request to aarch64

* cpu: Add cache maintenance functions for aarch64

* protos/limine, sys: Port SMP to aarch64

Also move common asm macros into a header file.

* test: Start up APs

* vmm: Unify get_next_level and implement large page splitting

* protos/limine: Map framebuffer using correct caching mode on AArch64

* CI: Fix GCC build for aarch64

* entry, menu: Replace uses of naked attribute with separate asm file

GCC does not understand the naked attribute on aarch64, and didn't
understand it for x86 in older versions.
2022-08-18 17:32:54 +02:00

53 lines
929 B
C

// Branch to \el1 if in EL1, or to \el2 if in EL2
// Uses \reg, halts if not in EL1 or EL2
.macro PICK_EL reg, el1, el2
mrs \reg, currentel
and \reg, \reg, #0b1100
cmp \reg, #0b0100 // EL1?
b.eq \el1
cmp \reg, #0b1000 // EL2?
b.eq \el2
// Halt otherwise
msr daifset, #0b1111
99:
wfi
b 99b
.endm
// Zero out all general purpose registers apart from X0
.macro ZERO_REGS_EXCEPT_X0
mov x1, xzr
mov x2, xzr
mov x3, xzr
mov x4, xzr
mov x5, xzr
mov x6, xzr
mov x7, xzr
mov x8, xzr
mov x9, xzr
mov x10, xzr
mov x11, xzr
mov x12, xzr
mov x13, xzr
mov x14, xzr
mov x15, xzr
mov x16, xzr
mov x17, xzr
mov x18, xzr
mov x19, xzr
mov x20, xzr
mov x21, xzr
mov x22, xzr
mov x23, xzr
mov x24, xzr
mov x25, xzr
mov x26, xzr
mov x27, xzr
mov x28, xzr
mov x29, xzr
mov x30, xzr
.endm