mirror of
https://github.com/limine-bootloader/limine
synced 2024-12-17 03:42:57 +03:00
e1f6ac8860
* Initial aarch64 port * Enable chainload on aarch64 No changes necessary since it's all UEFI anyway. * Add specification for Limine protocol for aarch64 * PROTOCOL: Specify state of information in DT /chosen node * common: Add spinup code for aarch64 * common: Port elf and term to aarch64 * common: Port vmm to aarch64 Also prepare to drop VMM_FLAG_PRESENT on x86. * protos: Port limine boot protocol to aarch64 Also drop VMM_FLAG_PRESENT since we never unmap pages anyway. * test: Add DTB request * PROTOCOL: Port SMP request to aarch64 * cpu: Add cache maintenance functions for aarch64 * protos/limine, sys: Port SMP to aarch64 Also move common asm macros into a header file. * test: Start up APs * vmm: Unify get_next_level and implement large page splitting * protos/limine: Map framebuffer using correct caching mode on AArch64 * CI: Fix GCC build for aarch64 * entry, menu: Replace uses of naked attribute with separate asm file GCC does not understand the naked attribute on aarch64, and didn't understand it for x86 in older versions.
90 lines
2.3 KiB
C
90 lines
2.3 KiB
C
#include <stdint.h>
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#include <stddef.h>
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#include <stdbool.h>
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#include <lib/blib.h>
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#include <lib/print.h>
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#include <lib/rand.h>
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#include <sys/cpu.h>
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#include <mm/pmm.h>
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// TODO: Find where this mersenne twister implementation is inspired from
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// and properly credit the original author(s).
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static bool rand_initialised = false;
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#define n ((int)624)
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#define m ((int)397)
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#define matrix_a ((uint32_t)0x9908b0df)
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#define msb ((uint32_t)0x80000000)
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#define lsbs ((uint32_t)0x7fffffff)
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static uint32_t *status;
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static int ctr;
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static void init_rand(void) {
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uint32_t seed = ((uint32_t)0xc597060c * (uint32_t)rdtsc())
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* ((uint32_t)0xce86d624)
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^ ((uint32_t)0xee0da130 * (uint32_t)rdtsc());
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// TODO(qookie): aarch64 also has an optional HW random number generator
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#if defined (__x86_64__) || defined(__i386__)
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uint32_t eax, ebx, ecx, edx;
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// Check for rdseed
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if (cpuid(0x07, 0, &eax, &ebx, &ecx, &edx) && (ebx & (1 << 18))) {
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seed *= (seed ^ rdseed(uint32_t));
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} else if (cpuid(0x01, 0, &eax, &ebx, &ecx, &edx) && (ecx & (1 << 30))) {
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seed *= (seed ^ rdrand(uint32_t));
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}
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#endif
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status = ext_mem_alloc(n * sizeof(uint32_t));
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srand(seed);
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rand_initialised = true;
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}
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void srand(uint32_t s) {
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status[0] = s;
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for (ctr = 1; ctr < n; ctr++)
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status[ctr] = (1812433253 * (status[ctr - 1] ^ (status[ctr - 1] >> 30)) + ctr);
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}
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uint32_t rand32(void) {
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if (!rand_initialised)
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init_rand();
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const uint32_t mag01[2] = {0, matrix_a};
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if (ctr >= n) {
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for (int kk = 0; kk < n - m; kk++) {
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uint32_t y = (status[kk] & msb) | (status[kk + 1] & lsbs);
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status[kk] = status[kk + m] ^ (y >> 1) ^ mag01[y & 1];
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}
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for (int kk = n - m; kk < n - 1; kk++) {
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uint32_t y = (status[kk] & msb) | (status[kk + 1] & lsbs);
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status[kk] = status[kk + (m - n)] ^ (y >> 1) ^ mag01[y & 1];
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}
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uint32_t y = (status[n - 1] & msb) | (status[0] & lsbs);
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status[n - 1] = status[m - 1] ^ (y >> 1) ^ mag01[y & 1];
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ctr = 0;
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}
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uint32_t res = status[ctr++];
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res ^= (res >> 11);
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res ^= (res << 7) & 0x9d2c5680;
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res ^= (res << 15) & 0xefc60000;
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res ^= (res >> 18);
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return res;
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}
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uint64_t rand64(void) {
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return (((uint64_t)rand32()) << 32) | (uint64_t)rand32();
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}
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