mirror of
https://github.com/limine-bootloader/limine
synced 2024-12-11 17:24:08 +03:00
Implement do_32() and make stivale kernels work with UEFI
This commit is contained in:
mintsuki
parent
6c22743c7e
commit
5d3f8b4eb0
@ -8,6 +8,8 @@ else
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$(error Invalid target)
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endif
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CC32 = i386-elf-gcc
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CC = $(TOOLCHAIN)-gcc
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LD = $(TOOLCHAIN)-ld
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OBJCOPY = $(TOOLCHAIN)-objcopy
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@ -76,6 +78,9 @@ C_FILES := $(shell find -L ./ -type f -name '*.c' | sort)
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ifeq ($(TARGET), bios)
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ASM_FILES := $(shell find -L ./ -type f -name '*.asm' | sort)
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endif
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ifeq ($(TARGET), uefi)
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ASM_FILES := lib/do_32.asm
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endif
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OBJ := $(ASM_FILES:.asm=.o) $(C_FILES:.c=.o)
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HEADER_DEPS := $(C_FILES:.c=.d)
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@ -139,8 +144,21 @@ ifeq ($(TARGET), bios)
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$(CC) $(S2CFLAGS) $(INTERNAL_CFLAGS) -c $< -o $@
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endif
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ifeq ($(TARGET), uefi)
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%.32.o: %.32.c
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$(CC32) $(CFLAGS) $(INTERNAL_CFLAGS) -c $< -o $@.32
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$(OBJCOPY) -I elf32-i386 -O elf64-x86-64 $@.32 $@
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rm $@.32
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endif
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ifeq ($(TARGET), bios)
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%.o: %.asm
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nasm $< -F dwarf -g -f elf32 -o $@
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endif
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ifeq ($(TARGET), uefi)
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%.o: %.asm
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nasm $< -F dwarf -g -f elf64 -o $@
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endif
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clean:
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rm -f limine.elf limine_efi.elf limine_dbg.elf limine_nomap.elf limine_stage2only.elf font.o limine.map.o limine.sys stage2.bin stage2.bin.gz BOOTX64.EFI sys/smp_trampoline.bin sys/smp_trampoline.o $(OBJ) $(HEADER_DEPS)
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@ -71,6 +71,8 @@ uint64_t sqrt(uint64_t a_nInput) {
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bool efi_boot_services_exited = false;
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bool efi_exit_boot_services(void) {
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EFI_STATUS status;
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EFI_MEMORY_DESCRIPTOR tmp_mmap[1];
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UINTN mmap_size = sizeof(tmp_mmap);
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UINTN mmap_key = 0, desc_size = 0, desc_ver = 0;
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@ -78,7 +80,12 @@ bool efi_exit_boot_services(void) {
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uefi_call_wrapper(gBS->GetMemoryMap, 5,
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&mmap_size, tmp_mmap, &mmap_key, &desc_size, &desc_ver);
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uefi_call_wrapper(gBS->ExitBootServices, 2, efi_image_handle, mmap_key);
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status = uefi_call_wrapper(gBS->ExitBootServices, 2, efi_image_handle, mmap_key);
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if (status)
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panic("efi: Failed to exit boot services\n");
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asm volatile ("cli" ::: "memory");
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efi_boot_services_exited = true;
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@ -66,4 +66,8 @@ enum {
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BOOT_FROM_CD
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};
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#if defined (uefi)
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__attribute__((noreturn)) void do_32(void *fnptr, int args, ...);
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#endif
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#endif
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64
stage23/lib/do_32.asm
Normal file
64
stage23/lib/do_32.asm
Normal file
@ -0,0 +1,64 @@
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section .rodata
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invalid_idt:
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dq 0, 0
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section .text
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%macro push32 1
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sub rsp, 4
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mov dword [rsp], %1
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%endmacro
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global do_32
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bits 64
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do_32:
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mov rbp, rsp
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lidt [rel invalid_idt]
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cmp esi, 4
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jle .no_stack_args
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.push_stack_args:
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dec esi
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mov eax, [rbp + 8 + rsi*8]
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push32 eax
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test esi, esi
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jnz .push_stack_args
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.no_stack_args:
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push32 r9d
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push32 r8d
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push32 ecx
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push32 edx
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mov eax, 0x20
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mov ds, ax
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mov es, ax
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mov fs, ax
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mov gs, ax
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mov ss, ax
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lea rbx, [rel .go_32]
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push 0x18
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push rbx
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retfq
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bits 32
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.go_32:
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mov eax, cr0
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btr eax, 31
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mov cr0, eax
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mov ecx, 0xc0000080
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rdmsr
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btr eax, 8
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wrmsr
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mov eax, cr4
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btr eax, 5
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mov cr4, eax
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call edi
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127
stage23/protos/stivale.32.c
Normal file
127
stage23/protos/stivale.32.c
Normal file
@ -0,0 +1,127 @@
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#include <stdint.h>
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#include <stddef.h>
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#include <stdbool.h>
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#include <mm/vmm.h>
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__attribute__((noreturn)) void stivale_spinup_32(
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int bits, bool level5pg, uint32_t pagemap_top_lv,
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uint32_t entry_point_lo, uint32_t entry_point_hi,
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void *stivale_struct, uint32_t stack_lo, uint32_t stack_hi) {
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uint64_t entry_point =
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(uint64_t)entry_point_lo | ((uint64_t)entry_point_hi << 32);
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uint64_t stack =
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(uint64_t)stack_lo | ((uint64_t)stack_hi << 32);
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if (bits == 64) {
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if (level5pg) {
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// Enable CR4.LA57
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asm volatile (
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"mov eax, cr4\n\t"
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"bts eax, 12\n\t"
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"mov cr4, eax\n\t" ::: "eax", "memory"
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);
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}
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asm volatile (
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"cli\n\t"
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"cld\n\t"
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"mov cr3, eax\n\t"
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"mov eax, cr4\n\t"
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"or eax, 1 << 5\n\t"
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"mov cr4, eax\n\t"
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"mov ecx, 0xc0000080\n\t"
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"rdmsr\n\t"
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"or eax, 1 << 8\n\t"
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"wrmsr\n\t"
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"mov eax, cr0\n\t"
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"or eax, 1 << 31\n\t"
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"mov cr0, eax\n\t"
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"call 1f\n\t"
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"1: pop eax\n\t"
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"add eax, 8\n\t"
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"push 0x28\n\t"
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"push eax\n\t"
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"retf\n\t"
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".code64\n\t"
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"mov ax, 0x30\n\t"
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"mov ds, ax\n\t"
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"mov es, ax\n\t"
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"mov fs, ax\n\t"
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"mov gs, ax\n\t"
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"mov ss, ax\n\t"
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// Since we don't really know what is now present in the upper
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// 32 bits of the 64 bit registers, clear up the upper bits
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// of the registers we use to store stack pointer and instruction
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// pointer
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"mov esi, esi\n\t"
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"mov ebx, ebx\n\t"
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"mov edi, edi\n\t"
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// Let's pretend we push a return address
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"mov rsi, qword ptr [rsi]\n\t"
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"test rsi, rsi\n\t"
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"jz 1f\n\t"
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"sub rsi, 8\n\t"
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"mov qword ptr [rsi], 0\n\t"
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"1:\n\t"
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"push 0x30\n\t"
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"push rsi\n\t"
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"pushfq\n\t"
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"push 0x28\n\t"
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"push [rbx]\n\t"
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"xor rax, rax\n\t"
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"xor rbx, rbx\n\t"
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"xor rcx, rcx\n\t"
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"xor rdx, rdx\n\t"
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"xor rsi, rsi\n\t"
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"xor rbp, rbp\n\t"
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"xor r8, r8\n\t"
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"xor r9, r9\n\t"
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"xor r10, r10\n\t"
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"xor r11, r11\n\t"
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"xor r12, r12\n\t"
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"xor r13, r13\n\t"
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"xor r14, r14\n\t"
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"xor r15, r15\n\t"
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"iretq\n\t"
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".code32\n\t"
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:
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: "a" (pagemap_top_lv), "b" (&entry_point),
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"D" (stivale_struct), "S" (&stack)
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: "memory"
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);
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} else if (bits == 32) {
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asm volatile (
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"cli\n\t"
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"cld\n\t"
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"mov esp, dword ptr [esi]\n\t"
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"push edi\n\t"
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"push 0\n\t"
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"pushfd\n\t"
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"push 0x18\n\t"
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"push [ebx]\n\t"
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"xor eax, eax\n\t"
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"xor ebx, ebx\n\t"
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"xor ecx, ecx\n\t"
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"xor edx, edx\n\t"
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"xor esi, esi\n\t"
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"xor edi, edi\n\t"
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"xor ebp, ebp\n\t"
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"iret\n\t"
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:
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: "b"(&entry_point), "D"(stivale_struct), "S"(&stack)
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: "memory"
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);
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}
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__builtin_unreachable();
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}
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@ -16,6 +16,7 @@
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#include <lib/term.h>
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#include <sys/pic.h>
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#include <sys/cpu.h>
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#include <sys/gdt.h>
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#include <fs/file.h>
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#include <mm/vmm.h>
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#include <mm/pmm.h>
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@ -199,7 +200,7 @@ void stivale_load(char *config, char *cmdline) {
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stivale_struct.memory_map_entries = (uint64_t)memmap_entries;
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stivale_struct.memory_map_addr = (uint64_t)(size_t)memmap;
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stivale_spinup(bits, want_5lv, pagemap,
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stivale_spinup(bits, want_5lv, &pagemap,
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entry_point, &stivale_struct, stivale_hdr.stack);
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}
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@ -244,8 +245,17 @@ pagemap_t stivale_build_pagemap(bool level5pg) {
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return pagemap;
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}
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#if defined (uefi)
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extern symbol ImageBase;
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#endif
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__attribute__((noreturn)) void stivale_spinup_32(
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int bits, bool level5pg, uint32_t pagemap_top_lv,
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uint32_t entry_point_lo, uint32_t entry_point_hi,
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void *stivale_struct, uint32_t stack_lo, uint32_t stack_hi);
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__attribute__((noreturn)) void stivale_spinup(
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int bits, bool level5pg, pagemap_t pagemap,
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int bits, bool level5pg, pagemap_t *pagemap,
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uint64_t entry_point, void *stivale_struct, uint64_t stack) {
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mtrr_restore();
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@ -261,120 +271,36 @@ __attribute__((noreturn)) void stivale_spinup(
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}
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#endif
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#if defined (uefi)
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efi_exit_boot_services();
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#endif
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pic_mask_all();
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pic_flush();
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#if defined (bios)
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if (bits == 64) {
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if (level5pg) {
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// Enable CR4.LA57
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asm volatile (
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"mov eax, cr4\n\t"
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"bts eax, 12\n\t"
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"mov cr4, eax\n\t" ::: "eax", "memory"
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);
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}
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#if defined (uefi)
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gdt.ptr += (uintptr_t)ImageBase;
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asm volatile (
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"cli\n\t"
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"cld\n\t"
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"mov cr3, eax\n\t"
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"mov eax, cr4\n\t"
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"or eax, 1 << 5\n\t"
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"mov cr4, eax\n\t"
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"mov ecx, 0xc0000080\n\t"
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"rdmsr\n\t"
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"or eax, 1 << 8\n\t"
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"wrmsr\n\t"
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"mov eax, cr0\n\t"
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"or eax, 1 << 31\n\t"
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"mov cr0, eax\n\t"
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"jmp 0x28:1f\n\t"
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"1: .code64\n\t"
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"mov ax, 0x30\n\t"
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"mov ds, ax\n\t"
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"mov es, ax\n\t"
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"mov fs, ax\n\t"
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"mov gs, ax\n\t"
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"mov ss, ax\n\t"
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// Since we don't really know what is now present in the upper
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// 32 bits of the 64 bit registers, clear up the upper bits
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// of the registers we use to store stack pointer and instruction
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// pointer
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"mov esi, esi\n\t"
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"mov ebx, ebx\n\t"
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"mov edi, edi\n\t"
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// Let's pretend we push a return address
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"mov rsi, qword ptr [rsi]\n\t"
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"test rsi, rsi\n\t"
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"jz 1f\n\t"
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"sub rsi, 8\n\t"
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"mov qword ptr [rsi], 0\n\t"
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"1:\n\t"
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"push 0x30\n\t"
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"push rsi\n\t"
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"pushfq\n\t"
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"push 0x28\n\t"
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"push [rbx]\n\t"
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"xor rax, rax\n\t"
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"xor rbx, rbx\n\t"
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"xor rcx, rcx\n\t"
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"xor rdx, rdx\n\t"
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"xor rsi, rsi\n\t"
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"xor rbp, rbp\n\t"
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"xor r8, r8\n\t"
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"xor r9, r9\n\t"
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"xor r10, r10\n\t"
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"xor r11, r11\n\t"
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"xor r12, r12\n\t"
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"xor r13, r13\n\t"
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"xor r14, r14\n\t"
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"xor r15, r15\n\t"
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"iretq\n\t"
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".code32\n\t"
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:
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: "a" (pagemap.top_level), "b" (&entry_point),
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"D" (stivale_struct), "S" (&stack)
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: "memory"
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);
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} else if (bits == 32) {
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asm volatile (
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"cli\n\t"
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"cld\n\t"
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"mov esp, dword ptr [esi]\n\t"
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"push edi\n\t"
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"push 0\n\t"
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"pushfd\n\t"
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"push 0x18\n\t"
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"push [ebx]\n\t"
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"xor eax, eax\n\t"
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"xor ebx, ebx\n\t"
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"xor ecx, ecx\n\t"
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"xor edx, edx\n\t"
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"xor esi, esi\n\t"
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"xor edi, edi\n\t"
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"xor ebp, ebp\n\t"
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"iret\n\t"
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:
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: "b"(&entry_point), "D"(stivale_struct), "S"(&stack)
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: "memory"
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);
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}
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#elif defined (uefi)
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(void)bits; (void)level5pg; (void)pagemap; (void)entry_point;
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(void)stivale_struct; (void)stack;
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asm volatile (
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"lgdt %0\n\t"
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:
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: "m"(gdt)
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: "memory"
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);
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do_32(stivale_spinup_32, 8,
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bits, level5pg, (uint32_t)(uintptr_t)pagemap->top_level,
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(uint32_t)entry_point, (uint32_t)(entry_point >> 32),
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stivale_struct,
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(uint32_t)stack, (uint32_t)(stack >> 32));
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#endif
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for (;;);
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#if defined (bios)
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stivale_spinup_32(bits, level5pg, (uint32_t)(uintptr_t)pagemap->top_level,
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(uint32_t)entry_point, (uint32_t)(entry_point >> 32),
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stivale_struct,
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(uint32_t)stack, (uint32_t)(stack >> 32));
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#endif
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__builtin_unreachable();
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}
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@ -10,7 +10,7 @@ void stivale_load(char *config, char *cmdline);
|
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|
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pagemap_t stivale_build_pagemap(bool level5pg);
|
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__attribute__((noreturn)) void stivale_spinup(
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int bits, bool level5pg, pagemap_t pagemap,
|
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int bits, bool level5pg, pagemap_t *pagemap,
|
||||
uint64_t entry_point, void *stivale_struct, uint64_t stack);
|
||||
|
||||
#endif
|
||||
|
||||
@ -376,6 +376,6 @@ void stivale2_load(char *config, char *cmdline, bool pxe) {
|
||||
break;
|
||||
}
|
||||
|
||||
stivale_spinup(bits, level5pg && level5pg_requested, pagemap,
|
||||
stivale_spinup(bits, level5pg && level5pg_requested, &pagemap,
|
||||
entry_point, &stivale2_struct, stivale2_hdr.stack);
|
||||
}
|
||||
|
||||
22
stage23/sys/gdt.h
Normal file
22
stage23/sys/gdt.h
Normal file
@ -0,0 +1,22 @@
|
||||
#ifndef __SYS__GDT_H__
|
||||
#define __SYS__GDT_H__
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
struct gdtr {
|
||||
uint16_t limit;
|
||||
uintptr_t ptr;
|
||||
} __attribute__((packed));
|
||||
|
||||
struct gdt_desc {
|
||||
uint16_t limit;
|
||||
uint16_t base_low;
|
||||
uint8_t base_mid;
|
||||
uint8_t access;
|
||||
uint8_t granularity;
|
||||
uint8_t base_hi;
|
||||
} __attribute__((packed));
|
||||
|
||||
extern struct gdtr gdt;
|
||||
|
||||
#endif
|
||||
@ -1,63 +0,0 @@
|
||||
section .data
|
||||
|
||||
global gdt
|
||||
|
||||
gdt:
|
||||
dw .size - 1 ; GDT size
|
||||
dd .start ; GDT start address
|
||||
|
||||
.start:
|
||||
; Null desc
|
||||
dq 0
|
||||
|
||||
; 16-bit code
|
||||
dw 0xffff ; Limit
|
||||
dw 0x0000 ; Base (low 16 bits)
|
||||
db 0x00 ; Base (mid 8 bits)
|
||||
db 10011010b ; Access
|
||||
db 00000000b ; Granularity
|
||||
db 0x00 ; Base (high 8 bits)
|
||||
|
||||
; 16-bit data
|
||||
dw 0xffff ; Limit
|
||||
dw 0x0000 ; Base (low 16 bits)
|
||||
db 0x00 ; Base (mid 8 bits)
|
||||
db 10010010b ; Access
|
||||
db 00000000b ; Granularity
|
||||
db 0x00 ; Base (high 8 bits)
|
||||
|
||||
; 32-bit code
|
||||
dw 0xffff ; Limit
|
||||
dw 0x0000 ; Base (low 16 bits)
|
||||
db 0x00 ; Base (mid 8 bits)
|
||||
db 10011010b ; Access
|
||||
db 11001111b ; Granularity
|
||||
db 0x00 ; Base (high 8 bits)
|
||||
|
||||
; 32-bit data
|
||||
dw 0xffff ; Limit
|
||||
dw 0x0000 ; Base (low 16 bits)
|
||||
db 0x00 ; Base (mid 8 bits)
|
||||
db 10010010b ; Access
|
||||
db 11001111b ; Granularity
|
||||
db 0x00 ; Base (high 8 bits)
|
||||
|
||||
; 64-bit code
|
||||
dw 0x0000 ; Limit
|
||||
dw 0x0000 ; Base (low 16 bits)
|
||||
db 0x00 ; Base (mid 8 bits)
|
||||
db 10011010b ; Access
|
||||
db 00100000b ; Granularity
|
||||
db 0x00 ; Base (high 8 bits)
|
||||
|
||||
; 64-bit data
|
||||
dw 0x0000 ; Limit
|
||||
dw 0x0000 ; Base (low 16 bits)
|
||||
db 0x00 ; Base (mid 8 bits)
|
||||
db 10010010b ; Access
|
||||
db 00000000b ; Granularity
|
||||
db 0x00 ; Base (high 8 bits)
|
||||
|
||||
.end:
|
||||
|
||||
.size: equ .end - .start
|
||||
65
stage23/sys/gdt.s2.c
Normal file
65
stage23/sys/gdt.s2.c
Normal file
@ -0,0 +1,65 @@
|
||||
#include <stdint.h>
|
||||
#include <sys/gdt.h>
|
||||
|
||||
static struct gdt_desc gdt_descs[] = {
|
||||
{0},
|
||||
|
||||
{
|
||||
.limit = 0xffff,
|
||||
.base_low = 0x0000,
|
||||
.base_mid = 0x00,
|
||||
.access = 0b10011010,
|
||||
.granularity = 0b00000000,
|
||||
.base_hi = 0x00
|
||||
},
|
||||
|
||||
{
|
||||
.limit = 0xffff,
|
||||
.base_low = 0x0000,
|
||||
.base_mid = 0x00,
|
||||
.access = 0b10010010,
|
||||
.granularity = 0b00000000,
|
||||
.base_hi = 0x00
|
||||
},
|
||||
|
||||
{
|
||||
.limit = 0xffff,
|
||||
.base_low = 0x0000,
|
||||
.base_mid = 0x00,
|
||||
.access = 0b10011010,
|
||||
.granularity = 0b11001111,
|
||||
.base_hi = 0x00
|
||||
},
|
||||
|
||||
{
|
||||
.limit = 0xffff,
|
||||
.base_low = 0x0000,
|
||||
.base_mid = 0x00,
|
||||
.access = 0b10010010,
|
||||
.granularity = 0b11001111,
|
||||
.base_hi = 0x00
|
||||
},
|
||||
|
||||
{
|
||||
.limit = 0x0000,
|
||||
.base_low = 0x0000,
|
||||
.base_mid = 0x00,
|
||||
.access = 0b10011010,
|
||||
.granularity = 0b00100000,
|
||||
.base_hi = 0x00
|
||||
},
|
||||
|
||||
{
|
||||
.limit = 0x0000,
|
||||
.base_low = 0x0000,
|
||||
.base_mid = 0x00,
|
||||
.access = 0b10010010,
|
||||
.granularity = 0b00000000,
|
||||
.base_hi = 0x00
|
||||
}
|
||||
};
|
||||
|
||||
struct gdtr gdt = {
|
||||
sizeof(gdt_descs) - 1,
|
||||
(uintptr_t)gdt_descs
|
||||
};
|
||||
@ -8,6 +8,7 @@
|
||||
#include <lib/print.h>
|
||||
#include <sys/smp.h>
|
||||
#include <sys/lapic.h>
|
||||
#include <sys/gdt.h>
|
||||
#include <mm/vmm.h>
|
||||
#include <mm/pmm.h>
|
||||
#include <mm/mtrr.h>
|
||||
@ -39,11 +40,6 @@ struct madt_x2apic {
|
||||
uint32_t acpi_processor_uid;
|
||||
} __attribute__((packed));
|
||||
|
||||
struct gdtr {
|
||||
uint16_t limit;
|
||||
uint32_t ptr;
|
||||
} __attribute__((packed));
|
||||
|
||||
static void delay(uint32_t cycles) {
|
||||
for (uint32_t i = 0; i < cycles; i++)
|
||||
inb(0x80);
|
||||
|
||||
Loading…
Reference in New Issue
Block a user