limine/common/menu_thunk.asm_ia32

section .text

global menu
extern _menu
menu:
    pop eax
    call .L1
.L1:
    pop eax
    add eax, .L3 - .L1
    cmp dword [eax], 0
    jne .L2
    mov [eax], esp
    jmp .L4

.L2:
    mov edi, [esp]
    mov esp, [eax]
    push edi
    jmp .L4

.L3:
    dq 0

.L4:
    push 0
    jmp _menu
asm: Add missing section directives 2023-06-20 14:24:49 +03:00			`section .text`

Initial AArch64 port (#205) * Initial aarch64 port * Enable chainload on aarch64 No changes necessary since it's all UEFI anyway. * Add specification for Limine protocol for aarch64 * PROTOCOL: Specify state of information in DT /chosen node * common: Add spinup code for aarch64 * common: Port elf and term to aarch64 * common: Port vmm to aarch64 Also prepare to drop VMM_FLAG_PRESENT on x86. * protos: Port limine boot protocol to aarch64 Also drop VMM_FLAG_PRESENT since we never unmap pages anyway. * test: Add DTB request * PROTOCOL: Port SMP request to aarch64 * cpu: Add cache maintenance functions for aarch64 * protos/limine, sys: Port SMP to aarch64 Also move common asm macros into a header file. * test: Start up APs * vmm: Unify get_next_level and implement large page splitting * protos/limine: Map framebuffer using correct caching mode on AArch64 * CI: Fix GCC build for aarch64 * entry, menu: Replace uses of naked attribute with separate asm file GCC does not understand the naked attribute on aarch64, and didn't understand it for x86 in older versions. 2022-08-18 18:32:54 +03:00			`global menu`
			`extern _menu`
			`menu:`
			`pop eax`
			`call .L1`
			`.L1:`
			`pop eax`
			`add eax, .L3 - .L1`
			`cmp dword [eax], 0`
			`jne .L2`
			`mov [eax], esp`
			`jmp .L4`

			`.L2:`
			`mov edi, [esp]`
			`mov esp, [eax]`
			`push edi`
			`jmp .L4`

			`.L3:`
			`dq 0`

			`.L4:`
			`push 0`
			`jmp _menu`