mirror of https://github.com/0intro/libelf
476 lines
15 KiB
C
476 lines
15 KiB
C
#define USED(x) if(x){}else{}
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#define nelem(x) (sizeof(x)/sizeof((x)[0]))
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extern char *machinestr[];
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#define EI_NIDENT 16
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enum {
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Eh32sz = 52,
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Sh32sz = 40,
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Ph32sz = 32,
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Eh64sz = 64,
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Sh64sz = 64,
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Ph64sz = 56,
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};
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/*
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* ELF32 Header
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*/
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typedef struct {
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uint8_t ident[EI_NIDENT];
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uint16_t type;
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uint16_t machine;
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uint32_t version;
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uint32_t entry;
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uint32_t phoff;
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uint32_t shoff;
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uint32_t flags;
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uint16_t ehsize;
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uint16_t phentsize;
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uint16_t phnum;
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uint16_t shentsize;
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uint16_t shnum;
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uint16_t shstrndx;
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} Elf32_Ehdr;
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/*
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* ELF64 Header
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*/
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typedef struct {
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uint8_t ident[EI_NIDENT];
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uint16_t type;
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uint16_t machine;
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uint32_t version;
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uint64_t entry;
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uint64_t phoff;
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uint64_t shoff;
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uint32_t flags;
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uint16_t ehsize;
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uint16_t phentsize;
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uint16_t phnum;
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uint16_t shentsize;
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uint16_t shnum;
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uint16_t shstrndx;
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} Elf64_Ehdr;
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/*
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* ELF32 Section Header
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*/
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typedef struct {
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uint32_t name;
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uint32_t type;
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uint32_t flags;
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uint32_t addr;
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uint32_t offset;
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uint32_t size;
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uint32_t link;
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uint32_t info;
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uint32_t addralign;
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uint32_t entsize;
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} Elf32_Shdr;
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/*
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* ELF64 Section Header
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*/
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typedef struct {
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uint32_t name;
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uint32_t type;
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uint64_t flags;
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uint64_t addr;
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uint64_t offset;
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uint64_t size;
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uint32_t link;
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uint32_t info;
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uint64_t addralign;
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uint64_t entsize;
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} Elf64_Shdr;
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/*
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* ELF32 Program Header
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*/
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typedef struct {
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uint32_t type;
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uint32_t offset;
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uint32_t vaddr;
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uint32_t paddr;
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uint32_t filesz;
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uint32_t memsz;
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uint32_t flags;
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uint32_t align;
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} Elf32_Phdr;
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/*
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* ELF64 Program Header
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*/
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typedef struct {
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uint32_t type;
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uint32_t flags;
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uint64_t offset;
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uint64_t vaddr;
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uint64_t paddr;
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uint64_t filesz;
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uint64_t memsz;
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uint64_t align;
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} Elf64_Phdr;
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/*
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* Object file type
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*/
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enum {
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ET_NONE = 0, /* No file type */
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ET_REL = 1, /* Relocatable file */
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ET_EXEC = 2, /* Executable file */
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ET_DYN = 3, /* Shared object file */
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ET_CORE = 4, /* Core file */
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ET_LOOS = 0xfe00, /* Operating system-specific */
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ET_HIOS = 0xfeff, /* Operating system-specific */
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ET_LOPROC = 0xff00, /* Processor-specific */
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ET_HIPROC = 0xffff, /* Processor-specific */
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};
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/*
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* Architectures
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*/
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enum {
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EM_NONE = 0, /* No machine */
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EM_M32 = 1, /* AT&T WE 32100 */
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EM_SPARC = 2, /* SPARC */
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EM_386 = 3, /* Intel 80386 */
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EM_68K = 4, /* Motorola 68000 */
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EM_88K = 5, /* Motorola 88000 */
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EM_IAMCU = 6, /* Intel MCU */
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EM_860 = 7, /* Intel 80860 */
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EM_MIPS = 8, /* MIPS I Architecture */
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EM_S370 = 9, /* IBM System/370 Processor */
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EM_MIPS_RS3_LE = 10, /* MIPS RS3000 Little-endian */
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/* 11-14 Reserved for future use */
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EM_PARISC = 15, /* Hewlett-Packard PA-RISC */
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reserved = 16, /* Reserved for future use */
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EM_VPP500 = 17, /* Fujitsu VPP500 */
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EM_SPARC32PLUS = 18, /* Enhanced instruction set SPARC */
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EM_960 = 19, /* Intel 80960 */
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EM_PPC = 20, /* PowerPC */
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EM_PPC64 = 21, /* 64-bit PowerPC */
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EM_S390 = 22, /* IBM System/390 Processor */
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EM_SPU = 23, /* IBM SPU/SPC */
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/* 24-35 Reserved for future use */
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EM_V800 = 36, /* NEC V800 */
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EM_FR20 = 37, /* Fujitsu FR20 */
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EM_RH32 = 38, /* TRW RH-32 */
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EM_RCE = 39, /* Motorola RCE */
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EM_ARM = 40, /* ARM 32-bit architecture (AARCH32) */
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EM_ALPHA = 41, /* Digital Alpha */
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EM_SH = 42, /* Hitachi SH */
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EM_SPARCV9 = 43, /* SPARC Version 9 */
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EM_TRICORE = 44, /* Siemens TriCore embedded processor */
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EM_ARC = 45, /* Argonaut RISC Core, Argonaut Technologies Inc. */
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EM_H8_300 = 46, /* Hitachi H8/300 */
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EM_H8_300H = 47, /* Hitachi H8/300H */
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EM_H8S = 48, /* Hitachi H8S */
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EM_H8_500 = 49, /* Hitachi H8/500 */
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EM_IA_64 = 50, /* Intel IA-64 processor architecture */
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EM_MIPS_X = 51, /* Stanford MIPS-X */
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EM_COLDFIRE = 52, /* Motorola ColdFire */
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EM_68HC12 = 53, /* Motorola M68HC12 */
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EM_MMA = 54, /* Fujitsu MMA Multimedia Accelerator */
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EM_PCP = 55, /* Siemens PCP */
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EM_NCPU = 56, /* Sony nCPU embedded RISC processor */
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EM_NDR1 = 57, /* Denso NDR1 microprocessor */
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EM_STARCORE = 58, /* Motorola Star*Core processor */
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EM_ME16 = 59, /* Toyota ME16 processor */
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EM_ST100 = 60, /* STMicroelectronics ST100 processor */
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EM_TINYJ = 61, /* Advanced Logic Corp. TinyJ embedded processor family */
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EM_X86_64 = 62, /* AMD x86-64 architecture */
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EM_PDSP = 63, /* Sony DSP Processor */
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EM_PDP10 = 64, /* Digital Equipment Corp. PDP-10 */
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EM_PDP11 = 65, /* Digital Equipment Corp. PDP-11 */
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EM_FX66 = 66, /* Siemens FX66 microcontroller */
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EM_ST9PLUS = 67, /* STMicroelectronics ST9+ 8/16 bit microcontroller */
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EM_ST7 = 68, /* STMicroelectronics ST7 8-bit microcontroller */
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EM_68HC16 = 69, /* Motorola MC68HC16 Microcontroller */
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EM_68HC11 = 70, /* Motorola MC68HC11 Microcontroller */
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EM_68HC08 = 71, /* Motorola MC68HC08 Microcontroller */
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EM_68HC05 = 72, /* Motorola MC68HC05 Microcontroller */
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EM_SVX = 73, /* Silicon Graphics SVx */
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EM_ST19 = 74, /* STMicroelectronics ST19 8-bit microcontroller */
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EM_VAX = 75, /* Digital VAX */
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EM_CRIS = 76, /* Axis Communications 32-bit embedded processor */
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EM_JAVELIN = 77, /* Infineon Technologies 32-bit embedded processor */
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EM_FIREPATH = 78, /* Element 14 64-bit DSP Processor */
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EM_ZSP = 79, /* LSI Logic 16-bit DSP Processor */
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EM_MMIX = 80, /* Donald Knuth's educational 64-bit processor */
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EM_HUANY = 81, /* Harvard University machine-independent object files */
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EM_PRISM = 82, /* SiTera Prism */
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EM_AVR = 83, /* Atmel AVR 8-bit microcontroller */
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EM_FR30 = 84, /* Fujitsu FR30 */
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EM_D10V = 85, /* Mitsubishi D10V */
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EM_D30V = 86, /* Mitsubishi D30V */
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EM_V850 = 87, /* NEC v850 */
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EM_M32R = 88, /* Mitsubishi M32R */
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EM_MN10300 = 89, /* Matsushita MN10300 */
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EM_MN10200 = 90, /* Matsushita MN10200 */
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EM_PJ = 91, /* picoJava */
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EM_OPENRISC = 92, /* OpenRISC 32-bit embedded processor */
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EM_ARC_COMPACT = 93, /* ARC International ARCompact processor (old spelling/synonym: EM_ARC_A5) */
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EM_XTENSA = 94, /* Tensilica Xtensa Architecture */
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EM_VIDEOCORE = 95, /* Alphamosaic VideoCore processor */
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EM_TMM_GPP = 96, /* Thompson Multimedia General Purpose Processor */
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EM_NS32K = 97, /* National Semiconductor 32000 series */
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EM_TPC = 98, /* Tenor Network TPC processor */
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EM_SNP1K = 99, /* Trebia SNP 1000 processor */
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EM_ST200 = 100, /* STMicroelectronics (www.st.com) ST200 microcontroller */
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EM_IP2K = 101, /* Ubicom IP2xxx microcontroller family */
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EM_MAX = 102, /* MAX Processor */
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EM_CR = 103, /* National Semiconductor CompactRISC microprocessor */
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EM_F2MC16 = 104, /* Fujitsu F2MC16 */
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EM_MSP430 = 105, /* Texas Instruments embedded microcontroller msp430 */
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EM_BLACKFIN = 106, /* Analog Devices Blackfin (DSP) processor */
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EM_SE_C33 = 107, /* S1C33 Family of Seiko Epson processors */
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EM_SEP = 108, /* Sharp embedded microprocessor */
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EM_ARCA = 109, /* Arca RISC Microprocessor */
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EM_UNICORE = 110, /* Microprocessor series from PKU-Unity Ltd. and MPRC of Peking University*/
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EM_EXCESS = 111, /* eXcess: 16/32/64-bit configurable embedded CPU */
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EM_DXP = 112, /* Icera Semiconductor Inc. Deep Execution Processor */
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EM_ALTERA_NIOS2 = 113, /* Altera Nios II soft-core processor */
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EM_CRX = 114, /* National Semiconductor CompactRISC CRX microprocessor */
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EM_XGATE = 115, /* Motorola XGATE embedded processor */
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EM_C166 = 116, /* Infineon C16x/XC16x processor */
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EM_M16C = 117, /* Renesas M16C series microprocessors */
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EM_DSPIC30F = 118, /* Microchip Technology dsPIC30F Digital Signal Controller */
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EM_CE = 119, /* Freescale Communication Engine RISC core */
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EM_M32C = 120, /* Renesas M32C series microprocessors */
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/* 121-130 Reserved for future use */
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EM_TSK3000 = 131, /* Altium TSK3000 core */
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EM_RS08 = 132, /* Freescale RS08 embedded processor */
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EM_SHARC = 133, /* Analog Devices SHARC family of 32-bit DSP processors */
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EM_ECOG2 = 134, /* Cyan Technology eCOG2 microprocessor */
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EM_SCORE7 = 135, /* Sunplus S+core7 RISC processor */
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EM_DSP24 = 136, /* New Japan Radio (NJR) 24-bit DSP Processor */
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EM_VIDEOCORE3 = 137, /* Broadcom VideoCore III processor */
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EM_LATTICEMICO32 = 138, /* RISC processor for Lattice FPGA architecture */
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EM_SE_C17 = 139, /* Seiko Epson C17 family */
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EM_TI_C6000 = 140, /* The Texas Instruments TMS320C6000 DSP family */
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EM_TI_C2000 = 141, /* The Texas Instruments TMS320C2000 DSP family */
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EM_TI_C5500 = 142, /* The Texas Instruments TMS320C55x DSP family */
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EM_TI_ARP32 = 143, /* Texas Instruments Application Specific RISC Processor, 32bit fetch */
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EM_TI_PRU = 144, /* Texas Instruments Programmable Realtime Unit */
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/* 145-159 Reserved for future use */
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EM_MMDSP_PLUS = 160, /* STMicroelectronics 64bit VLIW Data Signal Processor */
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EM_CYPRESS_M8C = 161, /* Cypress M8C microprocessor */
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EM_R32C = 162, /* Renesas R32C series microprocessors */
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EM_TRIMEDIA = 163, /* NXP Semiconductors TriMedia architecture family */
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EM_QDSP6 = 164, /* QUALCOMM DSP6 Processor */
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EM_8051 = 165, /* Intel 8051 and variants */
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EM_STXP7X = 166, /* STMicroelectronics STxP7x family of configurable and extensible RISC processors */
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EM_NDS32 = 167, /* Andes Technology compact code size embedded RISC processor family */
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EM_ECOG1X = 168, /* Cyan Technology eCOG1X family */
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EM_MAXQ30 = 169, /* Dallas Semiconductor MAXQ30 Core Micro-controllers */
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EM_XIMO16 = 170, /* New Japan Radio (NJR) 16-bit DSP Processor */
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EM_MANIK = 171, /* M2000 Reconfigurable RISC Microprocessor */
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EM_CRAYNV2 = 172, /* Cray Inc. NV2 vector architecture */
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EM_RX = 173, /* Renesas RX family */
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EM_METAG = 174, /* Imagination Technologies META processor architecture */
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EM_MCST_ELBRUS = 175, /* MCST Elbrus general purpose hardware architecture */
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EM_ECOG16 = 176, /* Cyan Technology eCOG16 family */
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EM_CR16 = 177, /* National Semiconductor CompactRISC CR16 16-bit microprocessor */
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EM_ETPU = 178, /* Freescale Extended Time Processing Unit */
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EM_SLE9X = 179, /* Infineon Technologies SLE9X core */
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EM_L10M = 180, /* Intel L10M */
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EM_K10M = 181, /* Intel K10M */
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/* 182 Reserved for future Intel use */
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EM_AARCH64 = 183, /* ARM 64-bit architecture (AARCH64) */
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/* 184 Reserved for future ARM use */
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EM_AVR32 = 185, /* Atmel Corporation 32-bit microprocessor family */
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EM_STM8 = 186, /* STMicroeletronics STM8 8-bit microcontroller */
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EM_TILE64 = 187, /* Tilera TILE64 multicore architecture family */
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EM_TILEPRO = 188, /* Tilera TILEPro multicore architecture family */
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EM_MICROBLAZE = 189, /* Xilinx MicroBlaze 32-bit RISC soft processor core */
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EM_CUDA = 190, /* NVIDIA CUDA architecture */
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EM_TILEGX = 191, /* Tilera TILE-Gx multicore architecture family */
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EM_CLOUDSHIELD = 192, /* CloudShield architecture family */
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EM_COREA_1ST = 193, /* KIPO-KAIST Core-A 1st generation processor family */
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EM_COREA_2ND = 194, /* KIPO-KAIST Core-A 2nd generation processor family */
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EM_ARC_COMPACT2 = 195, /* Synopsys ARCompact V2 */
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EM_OPEN8 = 196, /* Open8 8-bit RISC soft processor core */
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EM_RL78 = 197, /* Renesas RL78 family */
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EM_VIDEOCORE5 = 198, /* Broadcom VideoCore V processor */
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EM_78KOR = 199, /* Renesas 78KOR family */
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EM_56800EX = 200, /* Freescale 56800EX Digital Signal Controller (DSC) */
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EM_BA1 = 201, /* Beyond BA1 CPU architecture */
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EM_BA2 = 202, /* Beyond BA2 CPU architecture */
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EM_XCORE = 203, /* XMOS xCORE processor family */
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EM_MCHP_PIC = 204, /* Microchip 8-bit PIC(r) family */
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EM_INTEL205 = 205, /* Reserved by Intel */
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EM_INTEL206 = 206, /* Reserved by Intel */
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EM_INTEL207 = 207, /* Reserved by Intel */
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EM_INTEL208 = 208, /* Reserved by Intel */
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EM_INTEL209 = 209, /* Reserved by Intel */
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EM_KM32 = 210, /* KM211 KM32 32-bit processor */
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EM_KMX32 = 211, /* KM211 KMX32 32-bit processor */
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EM_KMX16 = 212, /* KM211 KMX16 16-bit processor */
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EM_KMX8 = 213, /* KM211 KMX8 8-bit processor */
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EM_KVARC = 214, /* KM211 KVARC processor */
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EM_CDP = 215, /* Paneve CDP architecture family */
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EM_COGE = 216, /* Cognitive Smart Memory Processor */
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EM_COOL = 217, /* Bluechip Systems CoolEngine */
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EM_NORC = 218, /* Nanoradio Optimized RISC */
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EM_CSR_KALIMBA = 219, /* CSR Kalimba architecture family */
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EM_Z80 = 220, /* Zilog Z80 */
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EM_VISIUM = 221, /* Controls and Data Services VISIUMcore processor */
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EM_FT32 = 222, /* FTDI Chip FT32 high performance 32-bit RISC architecture */
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EM_MOXIE = 223, /* Moxie processor family */
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EM_AMDGPU = 224, /* AMD GPU architecture */
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/* 225-242 */
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EM_RISCV = 243, /* RISC-V */
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};
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/*
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* Object file version
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*/
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enum {
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EV_NONE = 0, /* Invalid */
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EV_CURRENT = 1, /* Current */
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};
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/*
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* Identification
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*/
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enum {
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EI_MAG0 = 0, /* File identification */
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EI_MAG1 = 1, /* File identification */
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EI_MAG2 = 2, /* File identification */
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EI_MAG3 = 3, /* File identification */
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EI_CLASS = 4, /* File class */
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EI_DATA = 5, /* Data encoding */
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EI_VERSION = 6, /* File version */
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EI_OSABI = 7, /* Operating system/ABI identification */
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EI_ABIVERSION = 8, /* ABI version */
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EI_PAD = 9, /* Start of padding bytes */
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};
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/*
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* ELF Magic Number
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*/
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enum {
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ELFMAG0 = 0x7f, /* e_ident[EI_MAG0] */
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ELFMAG1 = 'E', /* e_ident[EI_MAG1] */
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ELFMAG2 = 'L', /* e_ident[EI_MAG2] */
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ELFMAG3 = 'F', /* e_ident[EI_MAG3] */
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};
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/*
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* File class
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*/
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enum {
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ELFCLASSNONE = 0, /* Invalid class */
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ELFCLASS32 = 1, /* 32-bit objects */
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ELFCLASS64 = 2, /* 64-bit objects */
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};
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/*
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* Data encoding
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*/
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enum {
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ELFDATANONE = 0, /* Invalid data encoding */
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ELFDATA2LSB = 1, /* Litte-endian */
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ELFDATA2MSB = 2, /* Big-endian */
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};
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/*
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* Operating system/ABI identification
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*/
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enum {
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ELFOSABI_NONE = 0, /* No extensions or unspecified */
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ELFOSABI_HPUX = 1, /* Hewlett-Packard HP-UX */
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ELFOSABI_NETBSD = 2, /* NetBSD */
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ELFOSABI_GNU = 3, /* GNU */
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ELFOSABI_SOLARIS = 6, /* Sun Solaris */
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ELFOSABI_AIX = 7, /* AIX */
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ELFOSABI_IRIX = 8, /* IRIX */
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ELFOSABI_FREEBSD = 9, /* FreeBSD */
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ELFOSABI_TRU64 = 10, /* Compaq TRU64 UNIX */
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ELFOSABI_MODESTO = 11, /* Novell Modesto */
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ELFOSABI_OPENBSD = 12, /* Open BSD */
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ELFOSABI_OPENVMS = 13, /* Open VMS */
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ELFOSABI_NSK = 14, /* Hewlett-Packard Non-Stop Kernel */
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ELFOSABI_AROS = 15, /* Amiga Research OS */
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ELFOSABI_FENIXOS = 16, /* The FenixOS highly scalable multi-core OS */
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ELFOSABI_CLOUDABI = 17, /* Nuxi CloudABI */
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ELFOSABI_OPENVOS = 18, /* Stratus Technologies OpenVOS */
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/* 64-255 Architecture-specific value range */
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};
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/*
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* Special Section Indexes
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*/
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enum {
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SHN_UNDEF = 0,
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SHN_LORESERVE = 0xff00,
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SHN_LOPROC = 0xff00,
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SHN_HIPROC = 0xff1f,
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SHN_LOOS = 0xff20,
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SHN_HIOS = 0xff3f,
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SHN_ABS = 0xfff1,
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SHN_COMMON = 0xfff2,
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SHN_XINDEX = 0xffff,
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SHN_HIRESERVE = 0xffff,
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};
|
|
|
|
/*
|
|
* Section Types
|
|
*/
|
|
enum {
|
|
SHT_NULL = 0,
|
|
SHT_PROGBITS = 1,
|
|
SHT_SYMTAB = 2,
|
|
SHT_STRTAB = 3,
|
|
SHT_RELA = 4,
|
|
SHT_HASH = 5,
|
|
SHT_DYNAMIC = 6,
|
|
SHT_NOTE = 7,
|
|
SHT_NOBITS = 8,
|
|
SHT_REL = 9,
|
|
SHT_SHLIB = 10,
|
|
SHT_DYNSYM = 11,
|
|
SHT_INIT_ARRAY = 14,
|
|
SHT_FINI_ARRAY = 15,
|
|
SHT_PREINIT_ARRAY = 16,
|
|
SHT_GROUP = 17,
|
|
SHT_SYMTAB_SHNDX = 18,
|
|
SHT_LOOS = 0x60000000,
|
|
SHT_HIOS = 0x6fffffff,
|
|
SHT_LOPROC = 0x70000000,
|
|
SHT_HIPROC = 0x7fffffff,
|
|
SHT_LOUSER = 0x80000000,
|
|
SHT_HIUSER = 0xffffffff,
|
|
};
|
|
|
|
/*
|
|
* Section Attribute Flags
|
|
*/
|
|
enum {
|
|
SHF_WRITE = 0x1,
|
|
SHF_ALLOC = 0x2,
|
|
SHF_EXECINSTR = 0x4,
|
|
SHF_MERGE = 0x10,
|
|
SHF_STRINGS = 0x20,
|
|
SHF_INFO_LINK = 0x40,
|
|
SHF_LINK_ORDER = 0x80,
|
|
SHF_OS_NONCONFORMING = 0x100,
|
|
SHF_GROUP = 0x200,
|
|
SHF_TLS = 0x400,
|
|
SHF_COMPRESSED = 0x800,
|
|
SHF_MASKOS = 0x0ff00000,
|
|
SHF_MASKPROC = 0xf0000000,
|
|
};
|
|
|
|
/*
|
|
* Section Attribute Flags
|
|
*/
|
|
enum {
|
|
GRP_COMDAT = 0x1,
|
|
GRP_MASKOS = 0x0ff00000,
|
|
GRP_MASKPROC = 0xf0000000,
|
|
};
|