2013-02-21 19:45:36 +04:00
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#include <efi.h>
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#include <efilib.h>
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/* this example program changes the Reserved Page Route (RPR) bit on ICH10's General
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* Control And Status Register (GCS) from LPC to PCI. In practical terms, it routes
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* outb to port 80h to the PCI bus. */
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#define GCS_OFFSET_ADDR 0x3410
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#define GCS_RPR_SHIFT 2
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#define GCS_RPR_PCI 1
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#define GCS_RPR_LPC 0
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#define VENDOR_ID_INTEL 0x8086
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#define DEVICE_ID_LPCIF 0x3a16
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#define DEVICE_ID_COUGARPOINT_LPCIF 0x1c56
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static EFI_HANDLE ImageHandle;
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typedef struct {
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uint16_t vendor_id; /* 00-01 */
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uint16_t device_id; /* 02-03 */
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char pad[0xEB]; /* 04-EF */
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uint32_t rcba; /* F0-F3 */
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uint32_t reserved[3]; /* F4-FF */
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} lpcif_t;
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static inline void set_bit(volatile uint32_t *flag, int bit, int value)
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{
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uint32_t val = *flag;
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Print(L"current value is 0x%2x\n", val);
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if (value) {
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val |= (1 << bit);
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} else {
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val &= ~(1 << bit);
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}
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Print(L"setting value to 0x%2x\n", val);
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*flag = val;
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val = *flag;
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Print(L"new value is 0x%2x\n", val);
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}
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static int is_device(EFI_PCI_IO *pciio, uint16_t vendor_id, uint16_t device_id)
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{
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lpcif_t lpcif;
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EFI_STATUS rc;
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rc = uefi_call_wrapper(pciio->Pci.Read, 5, pciio, EfiPciIoWidthUint16, 0, 2, &lpcif);
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if (EFI_ERROR(rc))
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return 0;
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if (vendor_id == lpcif.vendor_id && device_id == lpcif.device_id)
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return 1;
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return 0;
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}
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static EFI_STATUS find_pci_device(uint16_t vendor_id, uint16_t device_id,
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EFI_PCI_IO **pciio)
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{
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EFI_STATUS rc;
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EFI_HANDLE *Handles;
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2016-03-04 00:55:26 +03:00
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UINTN NoHandles, i;
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2013-02-21 19:45:36 +04:00
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if (!pciio)
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return EFI_INVALID_PARAMETER;
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rc = LibLocateHandle(ByProtocol, &PciIoProtocol, NULL, &NoHandles,
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&Handles);
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if (EFI_ERROR(rc))
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return rc;
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for (i = 0; i < NoHandles; i++) {
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void *pciio_tmp = NULL;
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rc = uefi_call_wrapper(BS->OpenProtocol, 6, Handles[i],
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&PciIoProtocol, &pciio_tmp, ImageHandle,
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NULL, EFI_OPEN_PROTOCOL_GET_PROTOCOL);
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if (EFI_ERROR(rc))
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continue;
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*pciio = pciio_tmp;
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if (!is_device(*pciio, vendor_id, device_id)) {
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*pciio = NULL;
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continue;
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}
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return EFI_SUCCESS;
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}
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return EFI_NOT_FOUND;
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}
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EFI_STATUS
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efi_main (EFI_HANDLE image_handle, EFI_SYSTEM_TABLE *systab)
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{
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InitializeLib(image_handle, systab);
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EFI_PCI_IO *pciio = NULL;
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lpcif_t lpcif;
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2018-03-13 22:20:23 +03:00
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EFI_STATUS rc = EFI_SUCCESS;
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2013-02-21 19:45:36 +04:00
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struct {
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uint16_t vendor;
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uint16_t device;
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} devices[] = {
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{ VENDOR_ID_INTEL, DEVICE_ID_LPCIF },
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{ VENDOR_ID_INTEL, DEVICE_ID_COUGARPOINT_LPCIF },
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{ 0, 0 }
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};
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int i;
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ImageHandle = image_handle;
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for (i = 0; devices[i].vendor != 0; i++) {
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rc = find_pci_device(devices[i].vendor, devices[i].device, &pciio);
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if (EFI_ERROR(rc))
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continue;
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}
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if (rc == EFI_NOT_FOUND) {
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Print(L"Device not found.\n");
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return rc;
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} else if (EFI_ERROR(rc)) {
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return rc;
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}
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rc = uefi_call_wrapper(pciio->Pci.Read, 5, pciio, EfiPciIoWidthUint32,
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EFI_FIELD_OFFSET(lpcif_t, rcba), 1, &lpcif.rcba);
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if (EFI_ERROR(rc))
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return rc;
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if (!(lpcif.rcba & 1)) {
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Print(L"rcrb is not mapped, cannot route port 80h\n");
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return EFI_UNSUPPORTED;
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}
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lpcif.rcba &= ~1UL;
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Print(L"rcba: 0x%8x\n", lpcif.rcba, lpcif.rcba);
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2018-03-13 22:20:21 +03:00
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set_bit((uint32_t *)(intptr_t)(lpcif.rcba + GCS_OFFSET_ADDR),
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2013-02-21 19:45:36 +04:00
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GCS_RPR_SHIFT, GCS_RPR_PCI);
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return EFI_SUCCESS;
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}
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