mirror of https://github.com/xiph/flac
libFLAC/cpu.c : Refactor for readability.
Patch-from: lvqcl <lvqcl.mail@gmail.com>
This commit is contained in:
Erik de Castro Lopo
parent
6a6207b52a
commit
cf732a8e86
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@ -140,7 +140,9 @@ void FLAC__cpu_info(FLAC__CPUInfo *info)
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info->ia32._3dnow = false;
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info->ia32.ext3dnow = false;
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info->ia32.extmmx = false;
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if(info->ia32.cpuid) {
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if(info->ia32.cpuid == false)
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return;
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{
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/* http://www.sandpile.org/x86/cpuid.htm */
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FLAC__uint32 flags_edx, flags_ecx;
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#ifdef FLAC__HAS_NASM
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@ -166,138 +168,138 @@ void FLAC__cpu_info(FLAC__CPUInfo *info)
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#else
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info->ia32._3dnow = info->ia32.ext3dnow = info->ia32.extmmx = false;
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#endif
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}
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#ifdef DEBUG
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fprintf(stderr, "CPU info (IA-32):\n");
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fprintf(stderr, " CPUID ...... %c\n", info->ia32.cpuid ? 'Y' : 'n');
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fprintf(stderr, " BSWAP ...... %c\n", info->ia32.bswap ? 'Y' : 'n');
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fprintf(stderr, " CMOV ....... %c\n", info->ia32.cmov ? 'Y' : 'n');
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fprintf(stderr, " MMX ........ %c\n", info->ia32.mmx ? 'Y' : 'n');
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fprintf(stderr, " FXSR ....... %c\n", info->ia32.fxsr ? 'Y' : 'n');
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fprintf(stderr, " SSE ........ %c\n", info->ia32.sse ? 'Y' : 'n');
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fprintf(stderr, " SSE2 ....... %c\n", info->ia32.sse2 ? 'Y' : 'n');
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fprintf(stderr, " SSE3 ....... %c\n", info->ia32.sse3 ? 'Y' : 'n');
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fprintf(stderr, " SSSE3 ...... %c\n", info->ia32.ssse3 ? 'Y' : 'n');
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fprintf(stderr, " SSE41 ...... %c\n", info->ia32.sse41 ? 'Y' : 'n');
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fprintf(stderr, " SSE42 ...... %c\n", info->ia32.sse42 ? 'Y' : 'n');
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fprintf(stderr, " 3DNow! ..... %c\n", info->ia32._3dnow ? 'Y' : 'n');
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fprintf(stderr, " 3DNow!-ext . %c\n", info->ia32.ext3dnow? 'Y' : 'n');
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fprintf(stderr, " 3DNow!-MMX . %c\n", info->ia32.extmmx ? 'Y' : 'n');
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fprintf(stderr, "CPU info (IA-32):\n");
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fprintf(stderr, " CPUID ...... %c\n", info->ia32.cpuid ? 'Y' : 'n');
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fprintf(stderr, " BSWAP ...... %c\n", info->ia32.bswap ? 'Y' : 'n');
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fprintf(stderr, " CMOV ....... %c\n", info->ia32.cmov ? 'Y' : 'n');
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fprintf(stderr, " MMX ........ %c\n", info->ia32.mmx ? 'Y' : 'n');
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fprintf(stderr, " FXSR ....... %c\n", info->ia32.fxsr ? 'Y' : 'n');
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fprintf(stderr, " SSE ........ %c\n", info->ia32.sse ? 'Y' : 'n');
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fprintf(stderr, " SSE2 ....... %c\n", info->ia32.sse2 ? 'Y' : 'n');
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fprintf(stderr, " SSE3 ....... %c\n", info->ia32.sse3 ? 'Y' : 'n');
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fprintf(stderr, " SSSE3 ...... %c\n", info->ia32.ssse3 ? 'Y' : 'n');
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fprintf(stderr, " SSE41 ...... %c\n", info->ia32.sse41 ? 'Y' : 'n');
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fprintf(stderr, " SSE42 ...... %c\n", info->ia32.sse42 ? 'Y' : 'n');
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fprintf(stderr, " 3DNow! ..... %c\n", info->ia32._3dnow ? 'Y' : 'n');
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fprintf(stderr, " 3DNow!-ext . %c\n", info->ia32.ext3dnow? 'Y' : 'n');
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fprintf(stderr, " 3DNow!-MMX . %c\n", info->ia32.extmmx ? 'Y' : 'n');
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#endif
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/*
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* now have to check for OS support of SSE instructions
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*/
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if(info->ia32.sse) {
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/*
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* now have to check for OS support of SSE instructions
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*/
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if(info->ia32.sse) {
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#if defined FLAC__NO_SSE_OS
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/* assume user knows better than us; turn it off */
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disable_sse(info);
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/* assume user knows better than us; turn it off */
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disable_sse(info);
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#elif defined FLAC__SSE_OS
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/* assume user knows better than us; leave as detected above */
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/* assume user knows better than us; leave as detected above */
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#elif defined(__FreeBSD__) || defined(__FreeBSD_kernel__) || defined(__DragonFly__) || defined(__APPLE__)
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int sse = 0;
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size_t len;
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/* at least one of these must work: */
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len = sizeof(sse); sse = sse || (sysctlbyname("hw.instruction_sse", &sse, &len, NULL, 0) == 0 && sse);
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len = sizeof(sse); sse = sse || (sysctlbyname("hw.optional.sse" , &sse, &len, NULL, 0) == 0 && sse); /* __APPLE__ ? */
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if(!sse)
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disable_sse(info);
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int sse = 0;
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size_t len;
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/* at least one of these must work: */
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len = sizeof(sse); sse = sse || (sysctlbyname("hw.instruction_sse", &sse, &len, NULL, 0) == 0 && sse);
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len = sizeof(sse); sse = sse || (sysctlbyname("hw.optional.sse" , &sse, &len, NULL, 0) == 0 && sse); /* __APPLE__ ? */
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if(!sse)
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disable_sse(info);
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#elif defined(__NetBSD__) || defined (__OpenBSD__)
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# if __NetBSD_Version__ >= 105250000 || (defined __OpenBSD__)
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int val = 0, mib[2] = { CTL_MACHDEP, CPU_SSE };
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size_t len = sizeof(val);
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if(sysctl(mib, 2, &val, &len, NULL, 0) < 0 || !val)
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disable_sse(info);
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else { /* double-check SSE2 */
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mib[1] = CPU_SSE2;
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len = sizeof(val);
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if(sysctl(mib, 2, &val, &len, NULL, 0) < 0 || !val) {
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disable_sse(info);
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info->ia32.fxsr = info->ia32.sse = true;
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}
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}
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# else
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int val = 0, mib[2] = { CTL_MACHDEP, CPU_SSE };
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size_t len = sizeof(val);
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if(sysctl(mib, 2, &val, &len, NULL, 0) < 0 || !val)
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disable_sse(info);
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else { /* double-check SSE2 */
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mib[1] = CPU_SSE2;
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len = sizeof(val);
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if(sysctl(mib, 2, &val, &len, NULL, 0) < 0 || !val) {
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disable_sse(info);
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info->ia32.fxsr = info->ia32.sse = true;
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}
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}
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# else
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disable_sse(info);
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# endif
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#elif defined(__linux__)
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int sse = 0;
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struct sigaction sigill_save;
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struct sigaction sigill_sse;
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sigill_sse.sa_sigaction = sigill_handler_sse_os;
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__sigemptyset(&sigill_sse.sa_mask);
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sigill_sse.sa_flags = SA_SIGINFO | SA_RESETHAND; /* SA_RESETHAND just in case our SIGILL return jump breaks, so we don't get stuck in a loop */
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if(0 == sigaction(SIGILL, &sigill_sse, &sigill_save))
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{
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/* http://www.ibiblio.org/gferg/ldp/GCC-Inline-Assembly-HOWTO.html */
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/* see sigill_handler_sse_os() for an explanation of the following: */
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asm volatile (
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"xorps %%xmm0,%%xmm0\n\t" /* will cause SIGILL if unsupported by OS */
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"incl %0\n\t" /* SIGILL handler will jump over this */
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/* landing zone */
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"nop\n\t" /* SIGILL jump lands here if "inc" is 9 bytes */
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"nop\n\t"
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"nop\n\t"
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"nop\n\t"
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"nop\n\t"
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"nop\n\t"
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"nop\n\t" /* SIGILL jump lands here if "inc" is 3 bytes (expected) */
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"nop\n\t"
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"nop" /* SIGILL jump lands here if "inc" is 1 byte */
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: "=r"(sse)
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: "0"(sse)
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);
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int sse = 0;
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struct sigaction sigill_save;
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struct sigaction sigill_sse;
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sigill_sse.sa_sigaction = sigill_handler_sse_os;
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__sigemptyset(&sigill_sse.sa_mask);
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sigill_sse.sa_flags = SA_SIGINFO | SA_RESETHAND; /* SA_RESETHAND just in case our SIGILL return jump breaks, so we don't get stuck in a loop */
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if(0 == sigaction(SIGILL, &sigill_sse, &sigill_save))
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{
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/* http://www.ibiblio.org/gferg/ldp/GCC-Inline-Assembly-HOWTO.html */
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/* see sigill_handler_sse_os() for an explanation of the following: */
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asm volatile (
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"xorps %%xmm0,%%xmm0\n\t" /* will cause SIGILL if unsupported by OS */
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"incl %0\n\t" /* SIGILL handler will jump over this */
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/* landing zone */
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"nop\n\t" /* SIGILL jump lands here if "inc" is 9 bytes */
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"nop\n\t"
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"nop\n\t"
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"nop\n\t"
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"nop\n\t"
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"nop\n\t"
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"nop\n\t" /* SIGILL jump lands here if "inc" is 3 bytes (expected) */
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"nop\n\t"
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"nop" /* SIGILL jump lands here if "inc" is 1 byte */
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: "=r"(sse)
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: "0"(sse)
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);
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sigaction(SIGILL, &sigill_save, NULL);
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}
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sigaction(SIGILL, &sigill_save, NULL);
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}
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if(!sse)
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disable_sse(info);
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#elif defined(_MSC_VER)
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__try {
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__asm {
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xorps xmm0,xmm0
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}
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}
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__except(EXCEPTION_EXECUTE_HANDLER) {
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if (_exception_code() == STATUS_ILLEGAL_INSTRUCTION)
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disable_sse(info);
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}
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#elif defined(__GNUC__) /* MinGW goes here */
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int sse = 0;
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/* Based on the idea described in Agner Fog's manual "Optimizing subroutines in assembly language" */
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/* In theory, not guaranteed to detect lack of OS SSE support on some future Intel CPUs, but in practice works (see the aforementioned manual) */
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if (info->ia32.fxsr) {
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struct {
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FLAC__uint32 buff[128];
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} __attribute__((aligned(16))) fxsr;
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FLAC__uint32 old_val, new_val;
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asm volatile ("fxsave %0" : "=m" (fxsr) : "m" (fxsr));
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old_val = fxsr.buff[50];
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fxsr.buff[50] ^= 0x0013c0de; /* change value in the buffer */
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asm volatile ("fxrstor %0" : "=m" (fxsr) : "m" (fxsr)); /* try to change SSE register */
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fxsr.buff[50] = old_val; /* restore old value in the buffer */
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asm volatile ("fxsave %0 " : "=m" (fxsr) : "m" (fxsr)); /* old value will be overwritten if SSE register was changed */
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new_val = fxsr.buff[50]; /* == old_val if FXRSTOR didn't change SSE register and (old_val ^ 0x0013c0de) otherwise */
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fxsr.buff[50] = old_val; /* again restore old value in the buffer */
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asm volatile ("fxrstor %0" : "=m" (fxsr) : "m" (fxsr)); /* restore old values of registers */
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if ((old_val^new_val) == 0x0013c0de)
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sse = 1;
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}
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if(!sse)
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disable_sse(info);
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#else
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/* no way to test, disable to be safe */
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if(!sse)
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disable_sse(info);
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#elif defined(_MSC_VER)
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__try {
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__asm {
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xorps xmm0,xmm0
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}
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}
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__except(EXCEPTION_EXECUTE_HANDLER) {
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if (_exception_code() == STATUS_ILLEGAL_INSTRUCTION)
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disable_sse(info);
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}
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#elif defined(__GNUC__) /* MinGW goes here */
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int sse = 0;
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/* Based on the idea described in Agner Fog's manual "Optimizing subroutines in assembly language" */
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/* In theory, not guaranteed to detect lack of OS SSE support on some future Intel CPUs, but in practice works (see the aforementioned manual) */
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if (info->ia32.fxsr) {
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struct {
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FLAC__uint32 buff[128];
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} __attribute__((aligned(16))) fxsr;
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FLAC__uint32 old_val, new_val;
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asm volatile ("fxsave %0" : "=m" (fxsr) : "m" (fxsr));
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old_val = fxsr.buff[50];
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fxsr.buff[50] ^= 0x0013c0de; /* change value in the buffer */
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asm volatile ("fxrstor %0" : "=m" (fxsr) : "m" (fxsr)); /* try to change SSE register */
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fxsr.buff[50] = old_val; /* restore old value in the buffer */
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asm volatile ("fxsave %0 " : "=m" (fxsr) : "m" (fxsr)); /* old value will be overwritten if SSE register was changed */
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new_val = fxsr.buff[50]; /* == old_val if FXRSTOR didn't change SSE register and (old_val ^ 0x0013c0de) otherwise */
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fxsr.buff[50] = old_val; /* again restore old value in the buffer */
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asm volatile ("fxrstor %0" : "=m" (fxsr) : "m" (fxsr)); /* restore old values of registers */
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if ((old_val^new_val) == 0x0013c0de)
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sse = 1;
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}
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if(!sse)
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disable_sse(info);
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#else
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/* no way to test, disable to be safe */
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disable_sse(info);
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#endif
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#ifdef DEBUG
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fprintf(stderr, " SSE OS sup . %c\n", info->ia32.sse ? 'Y' : 'n');
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fprintf(stderr, " SSE OS sup . %c\n", info->ia32.sse ? 'Y' : 'n');
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#endif
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}
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else /* info->ia32.sse == false */
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disable_sse(info);
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}
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else /* info->ia32.sse == false */
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disable_sse(info);
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#else
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info->use_asm = false;
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#endif
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