973 lines
40 KiB
C++
973 lines
40 KiB
C++
// Copyright (c) 2019 Google LLC.
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#include "source/opt/amd_ext_to_khr.h"
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#include <set>
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#include <string>
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#include "ir_builder.h"
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#include "source/opt/ir_context.h"
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#include "spv-amd-shader-ballot.insts.inc"
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#include "type_manager.h"
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namespace spvtools {
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namespace opt {
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namespace {
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enum AmdShaderBallotExtOpcodes {
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AmdShaderBallotSwizzleInvocationsAMD = 1,
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AmdShaderBallotSwizzleInvocationsMaskedAMD = 2,
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AmdShaderBallotWriteInvocationAMD = 3,
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AmdShaderBallotMbcntAMD = 4
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};
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enum AmdShaderTrinaryMinMaxExtOpCodes {
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FMin3AMD = 1,
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UMin3AMD = 2,
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SMin3AMD = 3,
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FMax3AMD = 4,
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UMax3AMD = 5,
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SMax3AMD = 6,
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FMid3AMD = 7,
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UMid3AMD = 8,
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SMid3AMD = 9
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};
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enum AmdGcnShader { CubeFaceCoordAMD = 2, CubeFaceIndexAMD = 1, TimeAMD = 3 };
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analysis::Type* GetUIntType(IRContext* ctx) {
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analysis::Integer int_type(32, false);
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return ctx->get_type_mgr()->GetRegisteredType(&int_type);
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}
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// Returns a folding rule that replaces |op(a,b,c)| by |op(op(a,b),c)|, where
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// |op| is either min or max. |opcode| is the binary opcode in the GLSLstd450
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// extended instruction set that corresponds to the trinary instruction being
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// replaced.
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template <GLSLstd450 opcode>
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bool ReplaceTrinaryMinMax(IRContext* ctx, Instruction* inst,
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const std::vector<const analysis::Constant*>&) {
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uint32_t glsl405_ext_inst_id =
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ctx->get_feature_mgr()->GetExtInstImportId_GLSLstd450();
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if (glsl405_ext_inst_id == 0) {
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ctx->AddExtInstImport("GLSL.std.450");
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glsl405_ext_inst_id =
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ctx->get_feature_mgr()->GetExtInstImportId_GLSLstd450();
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}
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InstructionBuilder ir_builder(
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ctx, inst,
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IRContext::kAnalysisDefUse | IRContext::kAnalysisInstrToBlockMapping);
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uint32_t op1 = inst->GetSingleWordInOperand(2);
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uint32_t op2 = inst->GetSingleWordInOperand(3);
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uint32_t op3 = inst->GetSingleWordInOperand(4);
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Instruction* temp = ir_builder.AddNaryExtendedInstruction(
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inst->type_id(), glsl405_ext_inst_id, opcode, {op1, op2});
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Instruction::OperandList new_operands;
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new_operands.push_back({SPV_OPERAND_TYPE_ID, {glsl405_ext_inst_id}});
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new_operands.push_back({SPV_OPERAND_TYPE_EXTENSION_INSTRUCTION_NUMBER,
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{static_cast<uint32_t>(opcode)}});
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new_operands.push_back({SPV_OPERAND_TYPE_ID, {temp->result_id()}});
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new_operands.push_back({SPV_OPERAND_TYPE_ID, {op3}});
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inst->SetInOperands(std::move(new_operands));
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ctx->UpdateDefUse(inst);
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return true;
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}
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// Returns a folding rule that replaces |mid(a,b,c)| by |clamp(a, min(b,c),
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// max(b,c)|. The three parameters are the opcode that correspond to the min,
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// max, and clamp operations for the type of the instruction being replaced.
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template <GLSLstd450 min_opcode, GLSLstd450 max_opcode, GLSLstd450 clamp_opcode>
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bool ReplaceTrinaryMid(IRContext* ctx, Instruction* inst,
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const std::vector<const analysis::Constant*>&) {
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uint32_t glsl405_ext_inst_id =
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ctx->get_feature_mgr()->GetExtInstImportId_GLSLstd450();
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if (glsl405_ext_inst_id == 0) {
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ctx->AddExtInstImport("GLSL.std.450");
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glsl405_ext_inst_id =
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ctx->get_feature_mgr()->GetExtInstImportId_GLSLstd450();
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}
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InstructionBuilder ir_builder(
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ctx, inst,
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IRContext::kAnalysisDefUse | IRContext::kAnalysisInstrToBlockMapping);
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uint32_t op1 = inst->GetSingleWordInOperand(2);
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uint32_t op2 = inst->GetSingleWordInOperand(3);
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uint32_t op3 = inst->GetSingleWordInOperand(4);
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Instruction* min = ir_builder.AddNaryExtendedInstruction(
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inst->type_id(), glsl405_ext_inst_id, static_cast<uint32_t>(min_opcode),
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{op2, op3});
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Instruction* max = ir_builder.AddNaryExtendedInstruction(
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inst->type_id(), glsl405_ext_inst_id, static_cast<uint32_t>(max_opcode),
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{op2, op3});
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Instruction::OperandList new_operands;
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new_operands.push_back({SPV_OPERAND_TYPE_ID, {glsl405_ext_inst_id}});
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new_operands.push_back({SPV_OPERAND_TYPE_EXTENSION_INSTRUCTION_NUMBER,
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{static_cast<uint32_t>(clamp_opcode)}});
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new_operands.push_back({SPV_OPERAND_TYPE_ID, {op1}});
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new_operands.push_back({SPV_OPERAND_TYPE_ID, {min->result_id()}});
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new_operands.push_back({SPV_OPERAND_TYPE_ID, {max->result_id()}});
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inst->SetInOperands(std::move(new_operands));
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ctx->UpdateDefUse(inst);
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return true;
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}
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// Returns a folding rule that will replace the opcode with |opcode| and add
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// the capabilities required. The folding rule assumes it is folding an
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// OpGroup*NonUniformAMD instruction from the SPV_AMD_shader_ballot extension.
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template <SpvOp new_opcode>
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bool ReplaceGroupNonuniformOperationOpCode(
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IRContext* ctx, Instruction* inst,
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const std::vector<const analysis::Constant*>&) {
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switch (new_opcode) {
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case SpvOpGroupNonUniformIAdd:
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case SpvOpGroupNonUniformFAdd:
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case SpvOpGroupNonUniformUMin:
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case SpvOpGroupNonUniformSMin:
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case SpvOpGroupNonUniformFMin:
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case SpvOpGroupNonUniformUMax:
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case SpvOpGroupNonUniformSMax:
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case SpvOpGroupNonUniformFMax:
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break;
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default:
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assert(
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false &&
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"Should be replacing with a group non uniform arithmetic operation.");
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}
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switch (inst->opcode()) {
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case SpvOpGroupIAddNonUniformAMD:
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case SpvOpGroupFAddNonUniformAMD:
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case SpvOpGroupUMinNonUniformAMD:
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case SpvOpGroupSMinNonUniformAMD:
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case SpvOpGroupFMinNonUniformAMD:
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case SpvOpGroupUMaxNonUniformAMD:
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case SpvOpGroupSMaxNonUniformAMD:
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case SpvOpGroupFMaxNonUniformAMD:
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break;
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default:
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assert(false &&
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"Should be replacing a group non uniform arithmetic operation.");
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}
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ctx->AddCapability(SpvCapabilityGroupNonUniformArithmetic);
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inst->SetOpcode(new_opcode);
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return true;
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}
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// Returns a folding rule that will replace the SwizzleInvocationsAMD extended
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// instruction in the SPV_AMD_shader_ballot extension.
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//
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// The instruction
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//
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// %offset = OpConstantComposite %v3uint %x %y %z %w
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// %result = OpExtInst %type %1 SwizzleInvocationsAMD %data %offset
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//
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// is replaced with
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//
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// potentially new constants and types
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//
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// clang-format off
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// %uint_max = OpConstant %uint 0xFFFFFFFF
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// %v4uint = OpTypeVector %uint 4
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// %ballot_value = OpConstantComposite %v4uint %uint_max %uint_max %uint_max %uint_max
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// %null = OpConstantNull %type
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// clang-format on
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//
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// and the following code in the function body
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//
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// clang-format off
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// %id = OpLoad %uint %SubgroupLocalInvocationId
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// %quad_idx = OpBitwiseAnd %uint %id %uint_3
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// %quad_ldr = OpBitwiseXor %uint %id %quad_idx
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// %my_offset = OpVectorExtractDynamic %uint %offset %quad_idx
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// %target_inv = OpIAdd %uint %quad_ldr %my_offset
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// %is_active = OpGroupNonUniformBallotBitExtract %bool %uint_3 %ballot_value %target_inv
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// %shuffle = OpGroupNonUniformShuffle %type %uint_3 %data %target_inv
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// %result = OpSelect %type %is_active %shuffle %null
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// clang-format on
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//
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// Also adding the capabilities and builtins that are needed.
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bool ReplaceSwizzleInvocations(IRContext* ctx, Instruction* inst,
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const std::vector<const analysis::Constant*>&) {
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analysis::TypeManager* type_mgr = ctx->get_type_mgr();
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analysis::ConstantManager* const_mgr = ctx->get_constant_mgr();
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ctx->AddExtension("SPV_KHR_shader_ballot");
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ctx->AddCapability(SpvCapabilityGroupNonUniformBallot);
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ctx->AddCapability(SpvCapabilityGroupNonUniformShuffle);
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InstructionBuilder ir_builder(
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ctx, inst,
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IRContext::kAnalysisDefUse | IRContext::kAnalysisInstrToBlockMapping);
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uint32_t data_id = inst->GetSingleWordInOperand(2);
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uint32_t offset_id = inst->GetSingleWordInOperand(3);
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// Get the subgroup invocation id.
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uint32_t var_id =
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ctx->GetBuiltinInputVarId(SpvBuiltInSubgroupLocalInvocationId);
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assert(var_id != 0 && "Could not get SubgroupLocalInvocationId variable.");
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Instruction* var_inst = ctx->get_def_use_mgr()->GetDef(var_id);
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Instruction* var_ptr_type =
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ctx->get_def_use_mgr()->GetDef(var_inst->type_id());
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uint32_t uint_type_id = var_ptr_type->GetSingleWordInOperand(1);
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Instruction* id = ir_builder.AddLoad(uint_type_id, var_id);
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uint32_t quad_mask = ir_builder.GetUintConstantId(3);
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// This gives the offset in the group of 4 of this invocation.
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Instruction* quad_idx = ir_builder.AddBinaryOp(uint_type_id, SpvOpBitwiseAnd,
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id->result_id(), quad_mask);
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// Get the invocation id of the first invocation in the group of 4.
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Instruction* quad_ldr = ir_builder.AddBinaryOp(
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uint_type_id, SpvOpBitwiseXor, id->result_id(), quad_idx->result_id());
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// Get the offset of the target invocation from the offset vector.
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Instruction* my_offset =
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ir_builder.AddBinaryOp(uint_type_id, SpvOpVectorExtractDynamic, offset_id,
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quad_idx->result_id());
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// Determine the index of the invocation to read from.
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Instruction* target_inv = ir_builder.AddBinaryOp(
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uint_type_id, SpvOpIAdd, quad_ldr->result_id(), my_offset->result_id());
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// Do the group operations
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uint32_t uint_max_id = ir_builder.GetUintConstantId(0xFFFFFFFF);
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uint32_t subgroup_scope = ir_builder.GetUintConstantId(SpvScopeSubgroup);
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const auto* ballot_value_const = const_mgr->GetConstant(
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type_mgr->GetUIntVectorType(4),
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{uint_max_id, uint_max_id, uint_max_id, uint_max_id});
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Instruction* ballot_value =
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const_mgr->GetDefiningInstruction(ballot_value_const);
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Instruction* is_active = ir_builder.AddNaryOp(
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type_mgr->GetBoolTypeId(), SpvOpGroupNonUniformBallotBitExtract,
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{subgroup_scope, ballot_value->result_id(), target_inv->result_id()});
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Instruction* shuffle =
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ir_builder.AddNaryOp(inst->type_id(), SpvOpGroupNonUniformShuffle,
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{subgroup_scope, data_id, target_inv->result_id()});
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// Create the null constant to use in the select.
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const auto* null = const_mgr->GetConstant(type_mgr->GetType(inst->type_id()),
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std::vector<uint32_t>());
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Instruction* null_inst = const_mgr->GetDefiningInstruction(null);
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// Build the select.
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inst->SetOpcode(SpvOpSelect);
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Instruction::OperandList new_operands;
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new_operands.push_back({SPV_OPERAND_TYPE_ID, {is_active->result_id()}});
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new_operands.push_back({SPV_OPERAND_TYPE_ID, {shuffle->result_id()}});
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new_operands.push_back({SPV_OPERAND_TYPE_ID, {null_inst->result_id()}});
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inst->SetInOperands(std::move(new_operands));
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ctx->UpdateDefUse(inst);
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return true;
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}
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// Returns a folding rule that will replace the SwizzleInvocationsMaskedAMD
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// extended instruction in the SPV_AMD_shader_ballot extension.
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//
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// The instruction
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//
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// %mask = OpConstantComposite %v3uint %uint_x %uint_y %uint_z
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// %result = OpExtInst %uint %1 SwizzleInvocationsMaskedAMD %data %mask
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//
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// is replaced with
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//
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// potentially new constants and types
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//
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// clang-format off
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// %uint_mask_extend = OpConstant %uint 0xFFFFFFE0
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// %uint_max = OpConstant %uint 0xFFFFFFFF
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// %v4uint = OpTypeVector %uint 4
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// %ballot_value = OpConstantComposite %v4uint %uint_max %uint_max %uint_max %uint_max
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// clang-format on
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//
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// and the following code in the function body
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//
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// clang-format off
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// %id = OpLoad %uint %SubgroupLocalInvocationId
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// %and_mask = OpBitwiseOr %uint %uint_x %uint_mask_extend
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// %and = OpBitwiseAnd %uint %id %and_mask
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// %or = OpBitwiseOr %uint %and %uint_y
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// %target_inv = OpBitwiseXor %uint %or %uint_z
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// %is_active = OpGroupNonUniformBallotBitExtract %bool %uint_3 %ballot_value %target_inv
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// %shuffle = OpGroupNonUniformShuffle %type %uint_3 %data %target_inv
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// %result = OpSelect %type %is_active %shuffle %uint_0
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// clang-format on
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//
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// Also adding the capabilities and builtins that are needed.
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bool ReplaceSwizzleInvocationsMasked(
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IRContext* ctx, Instruction* inst,
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const std::vector<const analysis::Constant*>&) {
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analysis::TypeManager* type_mgr = ctx->get_type_mgr();
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analysis::DefUseManager* def_use_mgr = ctx->get_def_use_mgr();
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analysis::ConstantManager* const_mgr = ctx->get_constant_mgr();
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ctx->AddCapability(SpvCapabilityGroupNonUniformBallot);
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ctx->AddCapability(SpvCapabilityGroupNonUniformShuffle);
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InstructionBuilder ir_builder(
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ctx, inst,
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IRContext::kAnalysisDefUse | IRContext::kAnalysisInstrToBlockMapping);
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// Get the operands to inst, and the components of the mask
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uint32_t data_id = inst->GetSingleWordInOperand(2);
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Instruction* mask_inst = def_use_mgr->GetDef(inst->GetSingleWordInOperand(3));
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assert(mask_inst->opcode() == SpvOpConstantComposite &&
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"The mask is suppose to be a vector constant.");
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assert(mask_inst->NumInOperands() == 3 &&
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"The mask is suppose to have 3 components.");
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uint32_t uint_x = mask_inst->GetSingleWordInOperand(0);
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uint32_t uint_y = mask_inst->GetSingleWordInOperand(1);
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uint32_t uint_z = mask_inst->GetSingleWordInOperand(2);
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// Get the subgroup invocation id.
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uint32_t var_id =
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ctx->GetBuiltinInputVarId(SpvBuiltInSubgroupLocalInvocationId);
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ctx->AddExtension("SPV_KHR_shader_ballot");
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assert(var_id != 0 && "Could not get SubgroupLocalInvocationId variable.");
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Instruction* var_inst = ctx->get_def_use_mgr()->GetDef(var_id);
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Instruction* var_ptr_type =
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ctx->get_def_use_mgr()->GetDef(var_inst->type_id());
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uint32_t uint_type_id = var_ptr_type->GetSingleWordInOperand(1);
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Instruction* id = ir_builder.AddLoad(uint_type_id, var_id);
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// Do the bitwise operations.
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uint32_t mask_extended = ir_builder.GetUintConstantId(0xFFFFFFE0);
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Instruction* and_mask = ir_builder.AddBinaryOp(uint_type_id, SpvOpBitwiseOr,
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uint_x, mask_extended);
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Instruction* and_result = ir_builder.AddBinaryOp(
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uint_type_id, SpvOpBitwiseAnd, id->result_id(), and_mask->result_id());
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Instruction* or_result = ir_builder.AddBinaryOp(
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uint_type_id, SpvOpBitwiseOr, and_result->result_id(), uint_y);
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Instruction* target_inv = ir_builder.AddBinaryOp(
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uint_type_id, SpvOpBitwiseXor, or_result->result_id(), uint_z);
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// Do the group operations
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uint32_t uint_max_id = ir_builder.GetUintConstantId(0xFFFFFFFF);
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uint32_t subgroup_scope = ir_builder.GetUintConstantId(SpvScopeSubgroup);
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const auto* ballot_value_const = const_mgr->GetConstant(
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type_mgr->GetUIntVectorType(4),
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{uint_max_id, uint_max_id, uint_max_id, uint_max_id});
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Instruction* ballot_value =
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const_mgr->GetDefiningInstruction(ballot_value_const);
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Instruction* is_active = ir_builder.AddNaryOp(
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type_mgr->GetBoolTypeId(), SpvOpGroupNonUniformBallotBitExtract,
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{subgroup_scope, ballot_value->result_id(), target_inv->result_id()});
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Instruction* shuffle =
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ir_builder.AddNaryOp(inst->type_id(), SpvOpGroupNonUniformShuffle,
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{subgroup_scope, data_id, target_inv->result_id()});
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// Create the null constant to use in the select.
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const auto* null = const_mgr->GetConstant(type_mgr->GetType(inst->type_id()),
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std::vector<uint32_t>());
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Instruction* null_inst = const_mgr->GetDefiningInstruction(null);
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// Build the select.
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inst->SetOpcode(SpvOpSelect);
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Instruction::OperandList new_operands;
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new_operands.push_back({SPV_OPERAND_TYPE_ID, {is_active->result_id()}});
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new_operands.push_back({SPV_OPERAND_TYPE_ID, {shuffle->result_id()}});
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new_operands.push_back({SPV_OPERAND_TYPE_ID, {null_inst->result_id()}});
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inst->SetInOperands(std::move(new_operands));
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ctx->UpdateDefUse(inst);
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return true;
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}
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// Returns a folding rule that will replace the WriteInvocationAMD extended
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// instruction in the SPV_AMD_shader_ballot extension.
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//
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// The instruction
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//
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// clang-format off
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// %result = OpExtInst %type %1 WriteInvocationAMD %input_value %write_value %invocation_index
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// clang-format on
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//
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// with
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//
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// %id = OpLoad %uint %SubgroupLocalInvocationId
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// %cmp = OpIEqual %bool %id %invocation_index
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// %result = OpSelect %type %cmp %write_value %input_value
|
|
//
|
|
// Also adding the capabilities and builtins that are needed.
|
|
bool ReplaceWriteInvocation(IRContext* ctx, Instruction* inst,
|
|
const std::vector<const analysis::Constant*>&) {
|
|
uint32_t var_id =
|
|
ctx->GetBuiltinInputVarId(SpvBuiltInSubgroupLocalInvocationId);
|
|
ctx->AddCapability(SpvCapabilitySubgroupBallotKHR);
|
|
ctx->AddExtension("SPV_KHR_shader_ballot");
|
|
assert(var_id != 0 && "Could not get SubgroupLocalInvocationId variable.");
|
|
Instruction* var_inst = ctx->get_def_use_mgr()->GetDef(var_id);
|
|
Instruction* var_ptr_type =
|
|
ctx->get_def_use_mgr()->GetDef(var_inst->type_id());
|
|
|
|
InstructionBuilder ir_builder(
|
|
ctx, inst,
|
|
IRContext::kAnalysisDefUse | IRContext::kAnalysisInstrToBlockMapping);
|
|
Instruction* t =
|
|
ir_builder.AddLoad(var_ptr_type->GetSingleWordInOperand(1), var_id);
|
|
analysis::Bool bool_type;
|
|
uint32_t bool_type_id = ctx->get_type_mgr()->GetTypeInstruction(&bool_type);
|
|
Instruction* cmp =
|
|
ir_builder.AddBinaryOp(bool_type_id, SpvOpIEqual, t->result_id(),
|
|
inst->GetSingleWordInOperand(4));
|
|
|
|
// Build a select.
|
|
inst->SetOpcode(SpvOpSelect);
|
|
Instruction::OperandList new_operands;
|
|
new_operands.push_back({SPV_OPERAND_TYPE_ID, {cmp->result_id()}});
|
|
new_operands.push_back(inst->GetInOperand(3));
|
|
new_operands.push_back(inst->GetInOperand(2));
|
|
|
|
inst->SetInOperands(std::move(new_operands));
|
|
ctx->UpdateDefUse(inst);
|
|
return true;
|
|
}
|
|
|
|
// Returns a folding rule that will replace the MbcntAMD extended instruction in
|
|
// the SPV_AMD_shader_ballot extension.
|
|
//
|
|
// The instruction
|
|
//
|
|
// %result = OpExtInst %uint %1 MbcntAMD %mask
|
|
//
|
|
// with
|
|
//
|
|
// Get SubgroupLtMask and convert the first 64-bits into a uint64_t because
|
|
// AMD's shader compiler expects a 64-bit integer mask.
|
|
//
|
|
// %var = OpLoad %v4uint %SubgroupLtMaskKHR
|
|
// %shuffle = OpVectorShuffle %v2uint %var %var 0 1
|
|
// %cast = OpBitcast %ulong %shuffle
|
|
//
|
|
// Perform the mask and count the bits.
|
|
//
|
|
// %and = OpBitwiseAnd %ulong %cast %mask
|
|
// %result = OpBitCount %uint %and
|
|
//
|
|
// Also adding the capabilities and builtins that are needed.
|
|
bool ReplaceMbcnt(IRContext* context, Instruction* inst,
|
|
const std::vector<const analysis::Constant*>&) {
|
|
analysis::TypeManager* type_mgr = context->get_type_mgr();
|
|
analysis::DefUseManager* def_use_mgr = context->get_def_use_mgr();
|
|
|
|
uint32_t var_id = context->GetBuiltinInputVarId(SpvBuiltInSubgroupLtMask);
|
|
assert(var_id != 0 && "Could not get SubgroupLtMask variable.");
|
|
context->AddCapability(SpvCapabilityGroupNonUniformBallot);
|
|
Instruction* var_inst = def_use_mgr->GetDef(var_id);
|
|
Instruction* var_ptr_type = def_use_mgr->GetDef(var_inst->type_id());
|
|
Instruction* var_type =
|
|
def_use_mgr->GetDef(var_ptr_type->GetSingleWordInOperand(1));
|
|
assert(var_type->opcode() == SpvOpTypeVector &&
|
|
"Variable is suppose to be a vector of 4 ints");
|
|
|
|
// Get the type for the shuffle.
|
|
analysis::Vector temp_type(GetUIntType(context), 2);
|
|
const analysis::Type* shuffle_type =
|
|
context->get_type_mgr()->GetRegisteredType(&temp_type);
|
|
uint32_t shuffle_type_id = type_mgr->GetTypeInstruction(shuffle_type);
|
|
|
|
uint32_t mask_id = inst->GetSingleWordInOperand(2);
|
|
Instruction* mask_inst = def_use_mgr->GetDef(mask_id);
|
|
|
|
// Testing with amd's shader compiler shows that a 64-bit mask is expected.
|
|
assert(type_mgr->GetType(mask_inst->type_id())->AsInteger() != nullptr);
|
|
assert(type_mgr->GetType(mask_inst->type_id())->AsInteger()->width() == 64);
|
|
|
|
InstructionBuilder ir_builder(
|
|
context, inst,
|
|
IRContext::kAnalysisDefUse | IRContext::kAnalysisInstrToBlockMapping);
|
|
Instruction* load = ir_builder.AddLoad(var_type->result_id(), var_id);
|
|
Instruction* shuffle = ir_builder.AddVectorShuffle(
|
|
shuffle_type_id, load->result_id(), load->result_id(), {0, 1});
|
|
Instruction* bitcast = ir_builder.AddUnaryOp(
|
|
mask_inst->type_id(), SpvOpBitcast, shuffle->result_id());
|
|
Instruction* t = ir_builder.AddBinaryOp(mask_inst->type_id(), SpvOpBitwiseAnd,
|
|
bitcast->result_id(), mask_id);
|
|
|
|
inst->SetOpcode(SpvOpBitCount);
|
|
inst->SetInOperands({{SPV_OPERAND_TYPE_ID, {t->result_id()}}});
|
|
context->UpdateDefUse(inst);
|
|
return true;
|
|
}
|
|
|
|
// A folding rule that will replace the CubeFaceCoordAMD extended
|
|
// instruction in the SPV_AMD_gcn_shader_ballot. Returns true if the folding is
|
|
// successful.
|
|
//
|
|
// The instruction
|
|
//
|
|
// %result = OpExtInst %v2float %1 CubeFaceCoordAMD %input
|
|
//
|
|
// with
|
|
//
|
|
// %x = OpCompositeExtract %float %input 0
|
|
// %y = OpCompositeExtract %float %input 1
|
|
// %z = OpCompositeExtract %float %input 2
|
|
// %nx = OpFNegate %float %x
|
|
// %ny = OpFNegate %float %y
|
|
// %nz = OpFNegate %float %z
|
|
// %ax = OpExtInst %float %n_1 FAbs %x
|
|
// %ay = OpExtInst %float %n_1 FAbs %y
|
|
// %az = OpExtInst %float %n_1 FAbs %z
|
|
// %amax_x_y = OpExtInst %float %n_1 FMax %ay %ax
|
|
// %amax = OpExtInst %float %n_1 FMax %az %amax_x_y
|
|
// %cubema = OpFMul %float %float_2 %amax
|
|
// %is_z_max = OpFOrdGreaterThanEqual %bool %az %amax_x_y
|
|
// %not_is_z_max = OpLogicalNot %bool %is_z_max
|
|
// %y_gt_x = OpFOrdGreaterThanEqual %bool %ay %ax
|
|
// %is_y_max = OpLogicalAnd %bool %not_is_z_max %y_gt_x
|
|
// %is_z_neg = OpFOrdLessThan %bool %z %float_0
|
|
// %cubesc_case_1 = OpSelect %float %is_z_neg %nx %x
|
|
// %is_x_neg = OpFOrdLessThan %bool %x %float_0
|
|
// %cubesc_case_2 = OpSelect %float %is_x_neg %z %nz
|
|
// %sel = OpSelect %float %is_y_max %x %cubesc_case_2
|
|
// %cubesc = OpSelect %float %is_z_max %cubesc_case_1 %sel
|
|
// %is_y_neg = OpFOrdLessThan %bool %y %float_0
|
|
// %cubetc_case_1 = OpSelect %float %is_y_neg %nz %z
|
|
// %cubetc = OpSelect %float %is_y_max %cubetc_case_1 %ny
|
|
// %cube = OpCompositeConstruct %v2float %cubesc %cubetc
|
|
// %denom = OpCompositeConstruct %v2float %cubema %cubema
|
|
// %div = OpFDiv %v2float %cube %denom
|
|
// %result = OpFAdd %v2float %div %const
|
|
//
|
|
// Also adding the capabilities and builtins that are needed.
|
|
bool ReplaceCubeFaceCoord(IRContext* ctx, Instruction* inst,
|
|
const std::vector<const analysis::Constant*>&) {
|
|
analysis::TypeManager* type_mgr = ctx->get_type_mgr();
|
|
analysis::ConstantManager* const_mgr = ctx->get_constant_mgr();
|
|
|
|
uint32_t float_type_id = type_mgr->GetFloatTypeId();
|
|
const analysis::Type* v2_float_type = type_mgr->GetFloatVectorType(2);
|
|
uint32_t v2_float_type_id = type_mgr->GetId(v2_float_type);
|
|
uint32_t bool_id = type_mgr->GetBoolTypeId();
|
|
|
|
InstructionBuilder ir_builder(
|
|
ctx, inst,
|
|
IRContext::kAnalysisDefUse | IRContext::kAnalysisInstrToBlockMapping);
|
|
|
|
uint32_t input_id = inst->GetSingleWordInOperand(2);
|
|
uint32_t glsl405_ext_inst_id =
|
|
ctx->get_feature_mgr()->GetExtInstImportId_GLSLstd450();
|
|
if (glsl405_ext_inst_id == 0) {
|
|
ctx->AddExtInstImport("GLSL.std.450");
|
|
glsl405_ext_inst_id =
|
|
ctx->get_feature_mgr()->GetExtInstImportId_GLSLstd450();
|
|
}
|
|
|
|
// Get the constants that will be used.
|
|
uint32_t f0_const_id = const_mgr->GetFloatConst(0.0);
|
|
uint32_t f2_const_id = const_mgr->GetFloatConst(2.0);
|
|
uint32_t f0_5_const_id = const_mgr->GetFloatConst(0.5);
|
|
const analysis::Constant* vec_const =
|
|
const_mgr->GetConstant(v2_float_type, {f0_5_const_id, f0_5_const_id});
|
|
uint32_t vec_const_id =
|
|
const_mgr->GetDefiningInstruction(vec_const)->result_id();
|
|
|
|
// Extract the input values.
|
|
Instruction* x = ir_builder.AddCompositeExtract(float_type_id, input_id, {0});
|
|
Instruction* y = ir_builder.AddCompositeExtract(float_type_id, input_id, {1});
|
|
Instruction* z = ir_builder.AddCompositeExtract(float_type_id, input_id, {2});
|
|
|
|
// Negate the input values.
|
|
Instruction* nx =
|
|
ir_builder.AddUnaryOp(float_type_id, SpvOpFNegate, x->result_id());
|
|
Instruction* ny =
|
|
ir_builder.AddUnaryOp(float_type_id, SpvOpFNegate, y->result_id());
|
|
Instruction* nz =
|
|
ir_builder.AddUnaryOp(float_type_id, SpvOpFNegate, z->result_id());
|
|
|
|
// Get the abolsute values of the inputs.
|
|
Instruction* ax = ir_builder.AddNaryExtendedInstruction(
|
|
float_type_id, glsl405_ext_inst_id, GLSLstd450FAbs, {x->result_id()});
|
|
Instruction* ay = ir_builder.AddNaryExtendedInstruction(
|
|
float_type_id, glsl405_ext_inst_id, GLSLstd450FAbs, {y->result_id()});
|
|
Instruction* az = ir_builder.AddNaryExtendedInstruction(
|
|
float_type_id, glsl405_ext_inst_id, GLSLstd450FAbs, {z->result_id()});
|
|
|
|
// Find which values are negative. Used in later computations.
|
|
Instruction* is_z_neg = ir_builder.AddBinaryOp(bool_id, SpvOpFOrdLessThan,
|
|
z->result_id(), f0_const_id);
|
|
Instruction* is_y_neg = ir_builder.AddBinaryOp(bool_id, SpvOpFOrdLessThan,
|
|
y->result_id(), f0_const_id);
|
|
Instruction* is_x_neg = ir_builder.AddBinaryOp(bool_id, SpvOpFOrdLessThan,
|
|
x->result_id(), f0_const_id);
|
|
|
|
// Compute cubema
|
|
Instruction* amax_x_y = ir_builder.AddNaryExtendedInstruction(
|
|
float_type_id, glsl405_ext_inst_id, GLSLstd450FMax,
|
|
{ax->result_id(), ay->result_id()});
|
|
Instruction* amax = ir_builder.AddNaryExtendedInstruction(
|
|
float_type_id, glsl405_ext_inst_id, GLSLstd450FMax,
|
|
{az->result_id(), amax_x_y->result_id()});
|
|
Instruction* cubema = ir_builder.AddBinaryOp(float_type_id, SpvOpFMul,
|
|
f2_const_id, amax->result_id());
|
|
|
|
// Do the comparisons needed for computing cubesc and cubetc.
|
|
Instruction* is_z_max =
|
|
ir_builder.AddBinaryOp(bool_id, SpvOpFOrdGreaterThanEqual,
|
|
az->result_id(), amax_x_y->result_id());
|
|
Instruction* not_is_z_max =
|
|
ir_builder.AddUnaryOp(bool_id, SpvOpLogicalNot, is_z_max->result_id());
|
|
Instruction* y_gr_x = ir_builder.AddBinaryOp(
|
|
bool_id, SpvOpFOrdGreaterThanEqual, ay->result_id(), ax->result_id());
|
|
Instruction* is_y_max = ir_builder.AddBinaryOp(
|
|
bool_id, SpvOpLogicalAnd, not_is_z_max->result_id(), y_gr_x->result_id());
|
|
|
|
// Select the correct value for cubesc.
|
|
Instruction* cubesc_case_1 = ir_builder.AddSelect(
|
|
float_type_id, is_z_neg->result_id(), nx->result_id(), x->result_id());
|
|
Instruction* cubesc_case_2 = ir_builder.AddSelect(
|
|
float_type_id, is_x_neg->result_id(), z->result_id(), nz->result_id());
|
|
Instruction* sel =
|
|
ir_builder.AddSelect(float_type_id, is_y_max->result_id(), x->result_id(),
|
|
cubesc_case_2->result_id());
|
|
Instruction* cubesc =
|
|
ir_builder.AddSelect(float_type_id, is_z_max->result_id(),
|
|
cubesc_case_1->result_id(), sel->result_id());
|
|
|
|
// Select the correct value for cubetc.
|
|
Instruction* cubetc_case_1 = ir_builder.AddSelect(
|
|
float_type_id, is_y_neg->result_id(), nz->result_id(), z->result_id());
|
|
Instruction* cubetc =
|
|
ir_builder.AddSelect(float_type_id, is_y_max->result_id(),
|
|
cubetc_case_1->result_id(), ny->result_id());
|
|
|
|
// Do the division
|
|
Instruction* cube = ir_builder.AddCompositeConstruct(
|
|
v2_float_type_id, {cubesc->result_id(), cubetc->result_id()});
|
|
Instruction* denom = ir_builder.AddCompositeConstruct(
|
|
v2_float_type_id, {cubema->result_id(), cubema->result_id()});
|
|
Instruction* div = ir_builder.AddBinaryOp(
|
|
v2_float_type_id, SpvOpFDiv, cube->result_id(), denom->result_id());
|
|
|
|
// Get the final result by adding 0.5 to |div|.
|
|
inst->SetOpcode(SpvOpFAdd);
|
|
Instruction::OperandList new_operands;
|
|
new_operands.push_back({SPV_OPERAND_TYPE_ID, {div->result_id()}});
|
|
new_operands.push_back({SPV_OPERAND_TYPE_ID, {vec_const_id}});
|
|
|
|
inst->SetInOperands(std::move(new_operands));
|
|
ctx->UpdateDefUse(inst);
|
|
return true;
|
|
}
|
|
|
|
// A folding rule that will replace the CubeFaceIndexAMD extended
|
|
// instruction in the SPV_AMD_gcn_shader_ballot. Returns true if the folding
|
|
// is successful.
|
|
//
|
|
// The instruction
|
|
//
|
|
// %result = OpExtInst %float %1 CubeFaceIndexAMD %input
|
|
//
|
|
// with
|
|
//
|
|
// %x = OpCompositeExtract %float %input 0
|
|
// %y = OpCompositeExtract %float %input 1
|
|
// %z = OpCompositeExtract %float %input 2
|
|
// %ax = OpExtInst %float %n_1 FAbs %x
|
|
// %ay = OpExtInst %float %n_1 FAbs %y
|
|
// %az = OpExtInst %float %n_1 FAbs %z
|
|
// %is_z_neg = OpFOrdLessThan %bool %z %float_0
|
|
// %is_y_neg = OpFOrdLessThan %bool %y %float_0
|
|
// %is_x_neg = OpFOrdLessThan %bool %x %float_0
|
|
// %amax_x_y = OpExtInst %float %n_1 FMax %ax %ay
|
|
// %is_z_max = OpFOrdGreaterThanEqual %bool %az %amax_x_y
|
|
// %y_gt_x = OpFOrdGreaterThanEqual %bool %ay %ax
|
|
// %case_z = OpSelect %float %is_z_neg %float_5 %float4
|
|
// %case_y = OpSelect %float %is_y_neg %float_3 %float2
|
|
// %case_x = OpSelect %float %is_x_neg %float_1 %float0
|
|
// %sel = OpSelect %float %y_gt_x %case_y %case_x
|
|
// %result = OpSelect %float %is_z_max %case_z %sel
|
|
//
|
|
// Also adding the capabilities and builtins that are needed.
|
|
bool ReplaceCubeFaceIndex(IRContext* ctx, Instruction* inst,
|
|
const std::vector<const analysis::Constant*>&) {
|
|
analysis::TypeManager* type_mgr = ctx->get_type_mgr();
|
|
analysis::ConstantManager* const_mgr = ctx->get_constant_mgr();
|
|
|
|
uint32_t float_type_id = type_mgr->GetFloatTypeId();
|
|
uint32_t bool_id = type_mgr->GetBoolTypeId();
|
|
|
|
InstructionBuilder ir_builder(
|
|
ctx, inst,
|
|
IRContext::kAnalysisDefUse | IRContext::kAnalysisInstrToBlockMapping);
|
|
|
|
uint32_t input_id = inst->GetSingleWordInOperand(2);
|
|
uint32_t glsl405_ext_inst_id =
|
|
ctx->get_feature_mgr()->GetExtInstImportId_GLSLstd450();
|
|
if (glsl405_ext_inst_id == 0) {
|
|
ctx->AddExtInstImport("GLSL.std.450");
|
|
glsl405_ext_inst_id =
|
|
ctx->get_feature_mgr()->GetExtInstImportId_GLSLstd450();
|
|
}
|
|
|
|
// Get the constants that will be used.
|
|
uint32_t f0_const_id = const_mgr->GetFloatConst(0.0);
|
|
uint32_t f1_const_id = const_mgr->GetFloatConst(1.0);
|
|
uint32_t f2_const_id = const_mgr->GetFloatConst(2.0);
|
|
uint32_t f3_const_id = const_mgr->GetFloatConst(3.0);
|
|
uint32_t f4_const_id = const_mgr->GetFloatConst(4.0);
|
|
uint32_t f5_const_id = const_mgr->GetFloatConst(5.0);
|
|
|
|
// Extract the input values.
|
|
Instruction* x = ir_builder.AddCompositeExtract(float_type_id, input_id, {0});
|
|
Instruction* y = ir_builder.AddCompositeExtract(float_type_id, input_id, {1});
|
|
Instruction* z = ir_builder.AddCompositeExtract(float_type_id, input_id, {2});
|
|
|
|
// Get the absolute values of the inputs.
|
|
Instruction* ax = ir_builder.AddNaryExtendedInstruction(
|
|
float_type_id, glsl405_ext_inst_id, GLSLstd450FAbs, {x->result_id()});
|
|
Instruction* ay = ir_builder.AddNaryExtendedInstruction(
|
|
float_type_id, glsl405_ext_inst_id, GLSLstd450FAbs, {y->result_id()});
|
|
Instruction* az = ir_builder.AddNaryExtendedInstruction(
|
|
float_type_id, glsl405_ext_inst_id, GLSLstd450FAbs, {z->result_id()});
|
|
|
|
// Find which values are negative. Used in later computations.
|
|
Instruction* is_z_neg = ir_builder.AddBinaryOp(bool_id, SpvOpFOrdLessThan,
|
|
z->result_id(), f0_const_id);
|
|
Instruction* is_y_neg = ir_builder.AddBinaryOp(bool_id, SpvOpFOrdLessThan,
|
|
y->result_id(), f0_const_id);
|
|
Instruction* is_x_neg = ir_builder.AddBinaryOp(bool_id, SpvOpFOrdLessThan,
|
|
x->result_id(), f0_const_id);
|
|
|
|
// Find the max value.
|
|
Instruction* amax_x_y = ir_builder.AddNaryExtendedInstruction(
|
|
float_type_id, glsl405_ext_inst_id, GLSLstd450FMax,
|
|
{ax->result_id(), ay->result_id()});
|
|
Instruction* is_z_max =
|
|
ir_builder.AddBinaryOp(bool_id, SpvOpFOrdGreaterThanEqual,
|
|
az->result_id(), amax_x_y->result_id());
|
|
Instruction* y_gr_x = ir_builder.AddBinaryOp(
|
|
bool_id, SpvOpFOrdGreaterThanEqual, ay->result_id(), ax->result_id());
|
|
|
|
// Get the value for each case.
|
|
Instruction* case_z = ir_builder.AddSelect(
|
|
float_type_id, is_z_neg->result_id(), f5_const_id, f4_const_id);
|
|
Instruction* case_y = ir_builder.AddSelect(
|
|
float_type_id, is_y_neg->result_id(), f3_const_id, f2_const_id);
|
|
Instruction* case_x = ir_builder.AddSelect(
|
|
float_type_id, is_x_neg->result_id(), f1_const_id, f0_const_id);
|
|
|
|
// Select the correct case.
|
|
Instruction* sel =
|
|
ir_builder.AddSelect(float_type_id, y_gr_x->result_id(),
|
|
case_y->result_id(), case_x->result_id());
|
|
|
|
// Get the final result by adding 0.5 to |div|.
|
|
inst->SetOpcode(SpvOpSelect);
|
|
Instruction::OperandList new_operands;
|
|
new_operands.push_back({SPV_OPERAND_TYPE_ID, {is_z_max->result_id()}});
|
|
new_operands.push_back({SPV_OPERAND_TYPE_ID, {case_z->result_id()}});
|
|
new_operands.push_back({SPV_OPERAND_TYPE_ID, {sel->result_id()}});
|
|
|
|
inst->SetInOperands(std::move(new_operands));
|
|
ctx->UpdateDefUse(inst);
|
|
return true;
|
|
}
|
|
|
|
// A folding rule that will replace the TimeAMD extended instruction in the
|
|
// SPV_AMD_gcn_shader_ballot. It returns true if the folding is successful.
|
|
// It returns False, otherwise.
|
|
//
|
|
// The instruction
|
|
//
|
|
// %result = OpExtInst %uint64 %1 TimeAMD
|
|
//
|
|
// with
|
|
//
|
|
// %result = OpReadClockKHR %uint64 %uint_3
|
|
//
|
|
// NOTE: TimeAMD uses subgroup scope (it is not a real time clock).
|
|
bool ReplaceTimeAMD(IRContext* ctx, Instruction* inst,
|
|
const std::vector<const analysis::Constant*>&) {
|
|
InstructionBuilder ir_builder(
|
|
ctx, inst,
|
|
IRContext::kAnalysisDefUse | IRContext::kAnalysisInstrToBlockMapping);
|
|
ctx->AddExtension("SPV_KHR_shader_clock");
|
|
ctx->AddCapability(SpvCapabilityShaderClockKHR);
|
|
|
|
inst->SetOpcode(SpvOpReadClockKHR);
|
|
Instruction::OperandList args;
|
|
uint32_t subgroup_scope_id = ir_builder.GetUintConstantId(SpvScopeSubgroup);
|
|
args.push_back({SPV_OPERAND_TYPE_ID, {subgroup_scope_id}});
|
|
inst->SetInOperands(std::move(args));
|
|
ctx->UpdateDefUse(inst);
|
|
|
|
return true;
|
|
}
|
|
|
|
class AmdExtFoldingRules : public FoldingRules {
|
|
public:
|
|
explicit AmdExtFoldingRules(IRContext* ctx) : FoldingRules(ctx) {}
|
|
|
|
protected:
|
|
virtual void AddFoldingRules() override {
|
|
rules_[SpvOpGroupIAddNonUniformAMD].push_back(
|
|
ReplaceGroupNonuniformOperationOpCode<SpvOpGroupNonUniformIAdd>);
|
|
rules_[SpvOpGroupFAddNonUniformAMD].push_back(
|
|
ReplaceGroupNonuniformOperationOpCode<SpvOpGroupNonUniformFAdd>);
|
|
rules_[SpvOpGroupUMinNonUniformAMD].push_back(
|
|
ReplaceGroupNonuniformOperationOpCode<SpvOpGroupNonUniformUMin>);
|
|
rules_[SpvOpGroupSMinNonUniformAMD].push_back(
|
|
ReplaceGroupNonuniformOperationOpCode<SpvOpGroupNonUniformSMin>);
|
|
rules_[SpvOpGroupFMinNonUniformAMD].push_back(
|
|
ReplaceGroupNonuniformOperationOpCode<SpvOpGroupNonUniformFMin>);
|
|
rules_[SpvOpGroupUMaxNonUniformAMD].push_back(
|
|
ReplaceGroupNonuniformOperationOpCode<SpvOpGroupNonUniformUMax>);
|
|
rules_[SpvOpGroupSMaxNonUniformAMD].push_back(
|
|
ReplaceGroupNonuniformOperationOpCode<SpvOpGroupNonUniformSMax>);
|
|
rules_[SpvOpGroupFMaxNonUniformAMD].push_back(
|
|
ReplaceGroupNonuniformOperationOpCode<SpvOpGroupNonUniformFMax>);
|
|
|
|
uint32_t extension_id =
|
|
context()->module()->GetExtInstImportId("SPV_AMD_shader_ballot");
|
|
|
|
if (extension_id != 0) {
|
|
ext_rules_[{extension_id, AmdShaderBallotSwizzleInvocationsAMD}]
|
|
.push_back(ReplaceSwizzleInvocations);
|
|
ext_rules_[{extension_id, AmdShaderBallotSwizzleInvocationsMaskedAMD}]
|
|
.push_back(ReplaceSwizzleInvocationsMasked);
|
|
ext_rules_[{extension_id, AmdShaderBallotWriteInvocationAMD}].push_back(
|
|
ReplaceWriteInvocation);
|
|
ext_rules_[{extension_id, AmdShaderBallotMbcntAMD}].push_back(
|
|
ReplaceMbcnt);
|
|
}
|
|
|
|
extension_id = context()->module()->GetExtInstImportId(
|
|
"SPV_AMD_shader_trinary_minmax");
|
|
|
|
if (extension_id != 0) {
|
|
ext_rules_[{extension_id, FMin3AMD}].push_back(
|
|
ReplaceTrinaryMinMax<GLSLstd450FMin>);
|
|
ext_rules_[{extension_id, UMin3AMD}].push_back(
|
|
ReplaceTrinaryMinMax<GLSLstd450UMin>);
|
|
ext_rules_[{extension_id, SMin3AMD}].push_back(
|
|
ReplaceTrinaryMinMax<GLSLstd450SMin>);
|
|
ext_rules_[{extension_id, FMax3AMD}].push_back(
|
|
ReplaceTrinaryMinMax<GLSLstd450FMax>);
|
|
ext_rules_[{extension_id, UMax3AMD}].push_back(
|
|
ReplaceTrinaryMinMax<GLSLstd450UMax>);
|
|
ext_rules_[{extension_id, SMax3AMD}].push_back(
|
|
ReplaceTrinaryMinMax<GLSLstd450SMax>);
|
|
ext_rules_[{extension_id, FMid3AMD}].push_back(
|
|
ReplaceTrinaryMid<GLSLstd450FMin, GLSLstd450FMax, GLSLstd450FClamp>);
|
|
ext_rules_[{extension_id, UMid3AMD}].push_back(
|
|
ReplaceTrinaryMid<GLSLstd450UMin, GLSLstd450UMax, GLSLstd450UClamp>);
|
|
ext_rules_[{extension_id, SMid3AMD}].push_back(
|
|
ReplaceTrinaryMid<GLSLstd450SMin, GLSLstd450SMax, GLSLstd450SClamp>);
|
|
}
|
|
|
|
extension_id =
|
|
context()->module()->GetExtInstImportId("SPV_AMD_gcn_shader");
|
|
|
|
if (extension_id != 0) {
|
|
ext_rules_[{extension_id, CubeFaceCoordAMD}].push_back(
|
|
ReplaceCubeFaceCoord);
|
|
ext_rules_[{extension_id, CubeFaceIndexAMD}].push_back(
|
|
ReplaceCubeFaceIndex);
|
|
ext_rules_[{extension_id, TimeAMD}].push_back(ReplaceTimeAMD);
|
|
}
|
|
}
|
|
};
|
|
|
|
class AmdExtConstFoldingRules : public ConstantFoldingRules {
|
|
public:
|
|
AmdExtConstFoldingRules(IRContext* ctx) : ConstantFoldingRules(ctx) {}
|
|
|
|
protected:
|
|
virtual void AddFoldingRules() override {}
|
|
};
|
|
|
|
} // namespace
|
|
|
|
Pass::Status AmdExtensionToKhrPass::Process() {
|
|
bool changed = false;
|
|
|
|
// Traverse the body of the functions to replace instructions that require
|
|
// the extensions.
|
|
InstructionFolder folder(
|
|
context(),
|
|
std::unique_ptr<AmdExtFoldingRules>(new AmdExtFoldingRules(context())),
|
|
MakeUnique<AmdExtConstFoldingRules>(context()));
|
|
for (Function& func : *get_module()) {
|
|
func.ForEachInst([&changed, &folder](Instruction* inst) {
|
|
if (folder.FoldInstruction(inst)) {
|
|
changed = true;
|
|
}
|
|
});
|
|
}
|
|
|
|
// Now that instruction that require the extensions have been removed, we can
|
|
// remove the extension instructions.
|
|
std::set<std::string> ext_to_remove = {"SPV_AMD_shader_ballot",
|
|
"SPV_AMD_shader_trinary_minmax",
|
|
"SPV_AMD_gcn_shader"};
|
|
|
|
std::vector<Instruction*> to_be_killed;
|
|
for (Instruction& inst : context()->module()->extensions()) {
|
|
if (inst.opcode() == SpvOpExtension) {
|
|
if (ext_to_remove.count(reinterpret_cast<const char*>(
|
|
&(inst.GetInOperand(0).words[0]))) != 0) {
|
|
to_be_killed.push_back(&inst);
|
|
}
|
|
}
|
|
}
|
|
|
|
for (Instruction& inst : context()->ext_inst_imports()) {
|
|
if (inst.opcode() == SpvOpExtInstImport) {
|
|
if (ext_to_remove.count(reinterpret_cast<const char*>(
|
|
&(inst.GetInOperand(0).words[0]))) != 0) {
|
|
to_be_killed.push_back(&inst);
|
|
}
|
|
}
|
|
}
|
|
|
|
for (Instruction* inst : to_be_killed) {
|
|
context()->KillInst(inst);
|
|
changed = true;
|
|
}
|
|
|
|
// The replacements that take place use instructions that are missing before
|
|
// SPIR-V 1.3. If we changed something, we will have to make sure the version
|
|
// is at least SPIR-V 1.3 to make sure those instruction can be used.
|
|
if (changed) {
|
|
uint32_t version = get_module()->version();
|
|
if (version < 0x00010300 /*1.3*/) {
|
|
get_module()->set_version(0x00010300);
|
|
}
|
|
}
|
|
return changed ? Status::SuccessWithChange : Status::SuccessWithoutChange;
|
|
}
|
|
|
|
} // namespace opt
|
|
} // namespace spvtools
|