Updated spirv-headers.
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3rdparty/spirv-headers/include/spirv/unified1/NonSemanticDebugBreak.h
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3rdparty/spirv-headers/include/spirv/unified1/NonSemanticDebugBreak.h
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// Copyright (c) 2020 The Khronos Group Inc.
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//
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// Permission is hereby granted, free of charge, to any person obtaining a
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// copy of this software and/or associated documentation files (the
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// "Materials"), to deal in the Materials without restriction, including
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// without limitation the rights to use, copy, modify, merge, publish,
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// distribute, sublicense, and/or sell copies of the Materials, and to
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// permit persons to whom the Materials are furnished to do so, subject to
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// the following conditions:
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//
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// The above copyright notice and this permission notice shall be included
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// in all copies or substantial portions of the Materials.
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//
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// MODIFICATIONS TO THIS FILE MAY MEAN IT NO LONGER ACCURATELY REFLECTS
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// KHRONOS STANDARDS. THE UNMODIFIED, NORMATIVE VERSIONS OF KHRONOS
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// SPECIFICATIONS AND HEADER INFORMATION ARE LOCATED AT
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// https://www.khronos.org/registry/
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//
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// THE MATERIALS ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
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// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
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// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
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// MATERIALS OR THE USE OR OTHER DEALINGS IN THE MATERIALS.
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//
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#ifndef SPIRV_UNIFIED1_NonSemanticDebugBreak_H_
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#define SPIRV_UNIFIED1_NonSemanticDebugBreak_H_
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#ifdef __cplusplus
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extern "C" {
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#endif
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enum {
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NonSemanticDebugBreakRevision = 1,
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NonSemanticDebugBreakRevision_BitWidthPadding = 0x7fffffff
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};
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enum NonSemanticDebugBreakInstructions {
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NonSemanticDebugBreakDebugBreak = 1,
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NonSemanticDebugBreakInstructionsMax = 0x7fffffff
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};
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#ifdef __cplusplus
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}
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#endif
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#endif // SPIRV_UNIFIED1_NonSemanticDebugBreak_H_
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3rdparty/spirv-headers/include/spirv/unified1/extinst.nonsemantic.debugbreak.grammar.json
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3rdparty/spirv-headers/include/spirv/unified1/extinst.nonsemantic.debugbreak.grammar.json
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{
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"revision" : 1,
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"instructions" : [
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{
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"opname" : "DebugBreak",
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"opcode" : 1
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}
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]
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}
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@ -4751,7 +4751,6 @@
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{ "kind" : "IdScope", "name" : "'Scope'" }
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{ "kind" : "IdScope", "name" : "'Scope'" }
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],
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],
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"capabilities" : [ "ShaderClockKHR" ],
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"capabilities" : [ "ShaderClockKHR" ],
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"extensions" : [ "SPV_KHR_shader_clock" ],
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"version" : "None"
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"version" : "None"
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},
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},
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{
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{
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@ -12517,6 +12516,78 @@
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"value" : 6140,
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"value" : 6140,
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"capabilities" : [ "VectorComputeINTEL" ],
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"capabilities" : [ "VectorComputeINTEL" ],
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"version" : "None"
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"version" : "None"
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},
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{
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"enumerant" : "ConduitKernelArgumentINTEL",
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"value" : 6175,
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"capabilities" : [ "FPGAArgumentInterfacesINTEL" ],
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"version" : "None"
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},
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{
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"enumerant" : "RegisterMapKernelArgumentINTEL",
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"value" : 6176,
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"capabilities" : [ "FPGAArgumentInterfacesINTEL" ],
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"version" : "None"
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},
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{
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"enumerant" : "MMHostInterfaceAddressWidthINTEL",
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"value" : 6177,
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"capabilities" : [ "FPGAArgumentInterfacesINTEL" ],
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"parameters" : [
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{ "kind" : "LiteralInteger", "name" : "'AddressWidth'" }
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],
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"version" : "None"
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},
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{
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"enumerant" : "MMHostInterfaceDataWidthINTEL",
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"value" : 6178,
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"capabilities" : [ "FPGAArgumentInterfacesINTEL" ],
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"parameters" : [
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{ "kind" : "LiteralInteger", "name" : "'DataWidth'" }
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],
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"version" : "None"
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},
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{
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"enumerant" : "MMHostInterfaceLatencyINTEL",
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"value" : 6179,
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"capabilities" : [ "FPGAArgumentInterfacesINTEL" ],
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"parameters" : [
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{ "kind" : "LiteralInteger", "name" : "'Latency'" }
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],
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"version" : "None"
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},
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{
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"enumerant" : "MMHostInterfaceReadWriteModeINTEL",
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"value" : 6180,
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"capabilities" : [ "FPGAArgumentInterfacesINTEL" ],
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"parameters" : [
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{ "kind" : "AccessQualifier", "name" : "'ReadWriteMode'" }
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],
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"version" : "None"
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},
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{
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"enumerant" : "MMHostInterfaceMaxBurstINTEL",
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"value" : 6181,
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"capabilities" : [ "FPGAArgumentInterfacesINTEL" ],
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"parameters" : [
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{ "kind" : "LiteralInteger", "name" : "'MaxBurstCount'" }
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],
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"version" : "None"
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},
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{
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"enumerant" : "MMHostInterfaceWaitRequestINTEL",
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"value" : 6182,
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"capabilities" : [ "FPGAArgumentInterfacesINTEL" ],
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"parameters" : [
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{ "kind" : "LiteralInteger", "name" : "'Waitrequest'" }
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],
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"version" : "None"
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},
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{
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"enumerant" : "StableKernelArgumentINTEL",
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"value" : 6183,
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"capabilities" : [ "FPGAArgumentInterfacesINTEL" ],
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"version" : "None"
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}
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}
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]
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]
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},
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},
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{
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{
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"enumerant" : "ShaderClockKHR",
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"enumerant" : "ShaderClockKHR",
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"value" : 5055,
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"value" : 5055,
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"capabilities" : [ "Shader" ],
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"extensions" : [ "SPV_KHR_shader_clock" ],
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"extensions" : [ "SPV_KHR_shader_clock" ],
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"version" : "None"
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"version" : "None"
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},
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},
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"extensions" : [ "SPV_INTEL_split_barrier" ],
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"extensions" : [ "SPV_INTEL_split_barrier" ],
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"version" : "None"
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"version" : "None"
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},
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},
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{
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"enumerant" : "FPGAArgumentInterfacesINTEL",
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"value" : 6174,
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"extensions" : [ "SPV_INTEL_fpga_argument_interfaces" ],
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"version" : "None"
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},
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{
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{
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"enumerant" : "GroupUniformArithmeticKHR",
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"enumerant" : "GroupUniformArithmeticKHR",
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"value" : 6400,
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"value" : 6400,
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@ -580,6 +580,15 @@ typedef enum SpvDecoration_ {
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SpvDecorationSingleElementVectorINTEL = 6085,
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SpvDecorationSingleElementVectorINTEL = 6085,
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SpvDecorationVectorComputeCallableFunctionINTEL = 6087,
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SpvDecorationVectorComputeCallableFunctionINTEL = 6087,
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SpvDecorationMediaBlockIOINTEL = 6140,
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SpvDecorationMediaBlockIOINTEL = 6140,
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SpvDecorationConduitKernelArgumentINTEL = 6175,
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SpvDecorationRegisterMapKernelArgumentINTEL = 6176,
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SpvDecorationMMHostInterfaceAddressWidthINTEL = 6177,
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SpvDecorationMMHostInterfaceDataWidthINTEL = 6178,
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SpvDecorationMMHostInterfaceLatencyINTEL = 6179,
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SpvDecorationMMHostInterfaceReadWriteModeINTEL = 6180,
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SpvDecorationMMHostInterfaceMaxBurstINTEL = 6181,
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SpvDecorationMMHostInterfaceWaitRequestINTEL = 6182,
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SpvDecorationStableKernelArgumentINTEL = 6183,
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SpvDecorationMax = 0x7fffffff,
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SpvDecorationMax = 0x7fffffff,
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} SpvDecoration;
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} SpvDecoration;
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SpvCapabilityAtomicFloat16AddEXT = 6095,
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SpvCapabilityAtomicFloat16AddEXT = 6095,
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SpvCapabilityDebugInfoModuleINTEL = 6114,
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SpvCapabilityDebugInfoModuleINTEL = 6114,
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SpvCapabilitySplitBarrierINTEL = 6141,
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SpvCapabilitySplitBarrierINTEL = 6141,
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SpvCapabilityFPGAArgumentInterfacesINTEL = 6174,
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SpvCapabilityGroupUniformArithmeticKHR = 6400,
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SpvCapabilityGroupUniformArithmeticKHR = 6400,
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SpvCapabilityMax = 0x7fffffff,
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SpvCapabilityMax = 0x7fffffff,
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} SpvCapability;
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} SpvCapability;
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@ -576,6 +576,15 @@ enum class Decoration : unsigned {
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SingleElementVectorINTEL = 6085,
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SingleElementVectorINTEL = 6085,
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VectorComputeCallableFunctionINTEL = 6087,
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VectorComputeCallableFunctionINTEL = 6087,
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MediaBlockIOINTEL = 6140,
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MediaBlockIOINTEL = 6140,
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ConduitKernelArgumentINTEL = 6175,
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RegisterMapKernelArgumentINTEL = 6176,
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MMHostInterfaceAddressWidthINTEL = 6177,
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MMHostInterfaceDataWidthINTEL = 6178,
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MMHostInterfaceLatencyINTEL = 6179,
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MMHostInterfaceReadWriteModeINTEL = 6180,
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MMHostInterfaceMaxBurstINTEL = 6181,
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MMHostInterfaceWaitRequestINTEL = 6182,
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StableKernelArgumentINTEL = 6183,
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Max = 0x7fffffff,
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Max = 0x7fffffff,
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};
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};
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AtomicFloat16AddEXT = 6095,
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AtomicFloat16AddEXT = 6095,
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DebugInfoModuleINTEL = 6114,
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DebugInfoModuleINTEL = 6114,
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SplitBarrierINTEL = 6141,
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SplitBarrierINTEL = 6141,
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FPGAArgumentInterfacesINTEL = 6174,
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GroupUniformArithmeticKHR = 6400,
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GroupUniformArithmeticKHR = 6400,
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Max = 0x7fffffff,
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Max = 0x7fffffff,
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};
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};
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"FunctionFloatingPointModeINTEL": 6080,
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"FunctionFloatingPointModeINTEL": 6080,
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"SingleElementVectorINTEL": 6085,
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"SingleElementVectorINTEL": 6085,
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"VectorComputeCallableFunctionINTEL": 6087,
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"VectorComputeCallableFunctionINTEL": 6087,
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"MediaBlockIOINTEL": 6140
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"MediaBlockIOINTEL": 6140,
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"ConduitKernelArgumentINTEL": 6175,
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"RegisterMapKernelArgumentINTEL": 6176,
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"MMHostInterfaceAddressWidthINTEL": 6177,
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"MMHostInterfaceDataWidthINTEL": 6178,
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"MMHostInterfaceLatencyINTEL": 6179,
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"MMHostInterfaceReadWriteModeINTEL": 6180,
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"MMHostInterfaceMaxBurstINTEL": 6181,
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"MMHostInterfaceWaitRequestINTEL": 6182,
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"StableKernelArgumentINTEL": 6183
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}
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}
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},
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},
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{
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{
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"AtomicFloat16AddEXT": 6095,
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"AtomicFloat16AddEXT": 6095,
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"DebugInfoModuleINTEL": 6114,
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"DebugInfoModuleINTEL": 6114,
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"SplitBarrierINTEL": 6141,
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"SplitBarrierINTEL": 6141,
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"FPGAArgumentInterfacesINTEL": 6174,
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"GroupUniformArithmeticKHR": 6400
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"GroupUniformArithmeticKHR": 6400
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}
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}
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},
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},
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