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Updated spirv-headers.

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Бранимир Караџић 2023-03-16 20:26:58 -07:00
parent ea6510a9a7
commit 9f162a8cf3
4 changed files with 225 additions and 0 deletions
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162
3rdparty/spirv-headers/include/spirv/unified1/spirv.core.grammar.json vendored
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@ -4592,6 +4592,66 @@
"extensions" : [ "SPV_KHR_ray_query" ], "extensions" : [ "SPV_KHR_ray_query" ],
"version" : "None" "version" : "None"
}, },
{
"opname" : "OpImageSampleWeightedQCOM",
"class" : "Image",
"opcode" : 4480,
"operands" : [
{ "kind" : "IdResultType" },
{ "kind" : "IdResult" },
{ "kind" : "IdRef", "name" : "'Texture'" },
{ "kind" : "IdRef", "name" : "'Coordinates'" },
{ "kind" : "IdRef", "name" : "'Weights'" }
],
"capabilities" : [ "TextureSampleWeightedQCOM" ],
"version" : "None"
},
{
"opname" : "OpImageBoxFilterQCOM",
"class" : "Image",
"opcode" : 4481,
"operands" : [
{ "kind" : "IdResultType" },
{ "kind" : "IdResult" },
{ "kind" : "IdRef", "name" : "'Texture'" },
{ "kind" : "IdRef", "name" : "'Coordinates'" },
{ "kind" : "IdRef", "name" : "'Box Size'" }
],
"capabilities" : [ "TextureBoxFilterQCOM" ],
"version" : "None"
},
{
"opname" : "OpImageBlockMatchSSDQCOM",
"class" : "Image",
"opcode" : 4482,
"operands" : [
{ "kind" : "IdResultType" },
{ "kind" : "IdResult" },
{ "kind" : "IdRef", "name" : "'Target'" },
{ "kind" : "IdRef", "name" : "'Target Coordinates'" },
{ "kind" : "IdRef", "name" : "'Reference'" },
{ "kind" : "IdRef", "name" : "'Reference Coordinates'" },
{ "kind" : "IdRef", "name" : "'Block Size'" }
],
"capabilities" : [ "TextureBlockMatchQCOM" ],
"version" : "None"
},
{
"opname" : "OpImageBlockMatchSADQCOM",
"class" : "Image",
"opcode" : 4483,
"operands" : [
{ "kind" : "IdResultType" },
{ "kind" : "IdResult" },
{ "kind" : "IdRef", "name" : "'Target'" },
{ "kind" : "IdRef", "name" : "'Target Coordinates'" },
{ "kind" : "IdRef", "name" : "'Reference'" },
{ "kind" : "IdRef", "name" : "'Reference Coordinates'" },
{ "kind" : "IdRef", "name" : "'Block Size'" }
],
"capabilities" : [ "TextureBlockMatchQCOM" ],
"version" : "None"
},
{ {
"opname" : "OpGroupIAddNonUniformAMD", "opname" : "OpGroupIAddNonUniformAMD",
"class" : "Group", "class" : "Group",
@ -9043,6 +9103,30 @@
"capabilities" : [ "LongConstantCompositeINTEL" ], "capabilities" : [ "LongConstantCompositeINTEL" ],
"version" : "None" "version" : "None"
}, },
{
"opname" : "OpConvertFToBF16INTEL",
"class" : "Conversion",
"opcode" : 6116,
"operands" : [
{ "kind" : "IdResultType" },
{ "kind" : "IdResult" },
{ "kind" : "IdRef", "name" : "'Float Value'" }
],
"capabilities" : [ "BFloat16ConversionINTEL" ],
"version" : "None"
},
{
"opname" : "OpConvertBF16ToFINTEL",
"class" : "Conversion",
"opcode" : 6117,
"operands" : [
{ "kind" : "IdResultType" },
{ "kind" : "IdResult" },
{ "kind" : "IdRef", "name" : "'BFloat16 Value'" }
],
"capabilities" : [ "BFloat16ConversionINTEL" ],
"version" : "None"
},
{ {
"opname" : "OpControlBarrierArriveINTEL", "opname" : "OpControlBarrierArriveINTEL",
"class" : "Barrier", "class" : "Barrier",
@ -10715,6 +10799,15 @@
"capabilities" : [ "FPGAKernelAttributesINTEL" ], "capabilities" : [ "FPGAKernelAttributesINTEL" ],
"version" : "None" "version" : "None"
}, },
{
"enumerant" : "RegisterMapInterfaceINTEL",
"value" : 6160,
"parameters" : [
{ "kind" : "LiteralInteger", "name" : "'WaitForDoneWrite'" }
],
"capabilities" : [ "FPGAKernelAttributesv2INTEL" ],
"version" : "None"
},
{ {
"enumerant" : "NamedBarrierCountINTEL", "enumerant" : "NamedBarrierCountINTEL",
"value" : 6417, "value" : 6417,
@ -11986,6 +12079,18 @@
"extensions" : [ "SPV_KHR_no_integer_wrap_decoration" ], "extensions" : [ "SPV_KHR_no_integer_wrap_decoration" ],
"version" : "1.4" "version" : "1.4"
}, },
{
"enumerant" : "WeightTextureQCOM",
"value" : 4487,
"extensions" : [ "SPV_QCOM_image_processing" ],
"version" : "None"
},
{
"enumerant" : "BlockMatchTextureQCOM",
"value" : 4488,
"extensions" : [ "SPV_QCOM_image_processing" ],
"version" : "None"
},
{ {
"enumerant" : "ExplicitInterpAMD", "enumerant" : "ExplicitInterpAMD",
"value" : 4999, "value" : 4999,
@ -12517,6 +12622,26 @@
"capabilities" : [ "VectorComputeINTEL" ], "capabilities" : [ "VectorComputeINTEL" ],
"version" : "None" "version" : "None"
}, },
{
"enumerant" : "LatencyControlLabelINTEL",
"value" : 6172,
"parameters" : [
{ "kind" : "LiteralInteger", "name" : "'Latency Label'" }
],
"capabilities" : [ "FPGALatencyControlINTEL" ],
"version" : "None"
},
{
"enumerant" : "LatencyControlConstraintINTEL",
"value" : 6173,
"parameters" : [
{ "kind" : "LiteralInteger", "name" : "'Relative To'" },
{ "kind" : "LiteralInteger", "name" : "'Control Type'" },
{ "kind" : "LiteralInteger", "name" : "'Relative Cycle'" }
],
"capabilities" : [ "FPGALatencyControlINTEL" ],
"version" : "None"
},
{ {
"enumerant" : "ConduitKernelArgumentINTEL", "enumerant" : "ConduitKernelArgumentINTEL",
"value" : 6175, "value" : 6175,
@ -14082,6 +14207,24 @@
"extensions" : [ "SPV_KHR_ray_tracing" ], "extensions" : [ "SPV_KHR_ray_tracing" ],
"version" : "None" "version" : "None"
}, },
{
"enumerant" : "TextureSampleWeightedQCOM",
"value" : 4484,
"extensions" : [ "SPV_QCOM_image_processing" ],
"version" : "None"
},
{
"enumerant" : "TextureBoxFilterQCOM",
"value" : 4485,
"extensions" : [ "SPV_QCOM_image_processing" ],
"version" : "None"
},
{
"enumerant" : "TextureBlockMatchQCOM",
"value" : 4486,
"extensions" : [ "SPV_QCOM_image_processing" ],
"version" : "None"
},
{ {
"enumerant" : "Float16ImageAMD", "enumerant" : "Float16ImageAMD",
"value" : 5008, "value" : 5008,
@ -14887,12 +15030,31 @@
"extensions" : [ "SPV_INTEL_debug_module" ], "extensions" : [ "SPV_INTEL_debug_module" ],
"version" : "None" "version" : "None"
}, },
{
"enumerant" : "BFloat16ConversionINTEL",
"value" : 6115,
"extensions" : [ "SPV_INTEL_bfloat16_conversion" ],
"version" : "None"
},
{ {
"enumerant" : "SplitBarrierINTEL", "enumerant" : "SplitBarrierINTEL",
"value" : 6141, "value" : 6141,
"extensions" : [ "SPV_INTEL_split_barrier" ], "extensions" : [ "SPV_INTEL_split_barrier" ],
"version" : "None" "version" : "None"
}, },
{
"enumerant" : "FPGAKernelAttributesv2INTEL",
"value" : 6161,
"capabilities" : [ "FPGAKernelAttributesINTEL" ],
"extensions" : [ "SPV_INTEL_kernel_attributes" ],
"version" : "None"
},
{
"enumerant" : "FPGALatencyControlINTEL",
"value" : 6171,
"extensions" : [ "SPV_INTEL_fpga_latency_control" ],
"version" : "None"
},
{ {
"enumerant" : "FPGAArgumentInterfacesINTEL", "enumerant" : "FPGAArgumentInterfacesINTEL",
"value" : 6174, "value" : 6174,

23
3rdparty/spirv-headers/include/spirv/unified1/spirv.h vendored
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@ -200,6 +200,7 @@ typedef enum SpvExecutionMode_ {
SpvExecutionModeNumSIMDWorkitemsINTEL = 5896, SpvExecutionModeNumSIMDWorkitemsINTEL = 5896,
SpvExecutionModeSchedulerTargetFmaxMhzINTEL = 5903, SpvExecutionModeSchedulerTargetFmaxMhzINTEL = 5903,
SpvExecutionModeStreamingInterfaceINTEL = 6154, SpvExecutionModeStreamingInterfaceINTEL = 6154,
SpvExecutionModeRegisterMapInterfaceINTEL = 6160,
SpvExecutionModeNamedBarrierCountINTEL = 6417, SpvExecutionModeNamedBarrierCountINTEL = 6417,
SpvExecutionModeMax = 0x7fffffff, SpvExecutionModeMax = 0x7fffffff,
} SpvExecutionMode; } SpvExecutionMode;
@ -512,6 +513,8 @@ typedef enum SpvDecoration_ {
SpvDecorationMaxByteOffsetId = 47, SpvDecorationMaxByteOffsetId = 47,
SpvDecorationNoSignedWrap = 4469, SpvDecorationNoSignedWrap = 4469,
SpvDecorationNoUnsignedWrap = 4470, SpvDecorationNoUnsignedWrap = 4470,
SpvDecorationWeightTextureQCOM = 4487,
SpvDecorationBlockMatchTextureQCOM = 4488,
SpvDecorationExplicitInterpAMD = 4999, SpvDecorationExplicitInterpAMD = 4999,
SpvDecorationOverrideCoverageNV = 5248, SpvDecorationOverrideCoverageNV = 5248,
SpvDecorationPassthroughNV = 5250, SpvDecorationPassthroughNV = 5250,
@ -580,6 +583,8 @@ typedef enum SpvDecoration_ {
SpvDecorationSingleElementVectorINTEL = 6085, SpvDecorationSingleElementVectorINTEL = 6085,
SpvDecorationVectorComputeCallableFunctionINTEL = 6087, SpvDecorationVectorComputeCallableFunctionINTEL = 6087,
SpvDecorationMediaBlockIOINTEL = 6140, SpvDecorationMediaBlockIOINTEL = 6140,
SpvDecorationLatencyControlLabelINTEL = 6172,
SpvDecorationLatencyControlConstraintINTEL = 6173,
SpvDecorationConduitKernelArgumentINTEL = 6175, SpvDecorationConduitKernelArgumentINTEL = 6175,
SpvDecorationRegisterMapKernelArgumentINTEL = 6176, SpvDecorationRegisterMapKernelArgumentINTEL = 6176,
SpvDecorationMMHostInterfaceAddressWidthINTEL = 6177, SpvDecorationMMHostInterfaceAddressWidthINTEL = 6177,
@ -1018,6 +1023,9 @@ typedef enum SpvCapability_ {
SpvCapabilityRayQueryKHR = 4472, SpvCapabilityRayQueryKHR = 4472,
SpvCapabilityRayTraversalPrimitiveCullingKHR = 4478, SpvCapabilityRayTraversalPrimitiveCullingKHR = 4478,
SpvCapabilityRayTracingKHR = 4479, SpvCapabilityRayTracingKHR = 4479,
SpvCapabilityTextureSampleWeightedQCOM = 4484,
SpvCapabilityTextureBoxFilterQCOM = 4485,
SpvCapabilityTextureBlockMatchQCOM = 4486,
SpvCapabilityFloat16ImageAMD = 5008, SpvCapabilityFloat16ImageAMD = 5008,
SpvCapabilityImageGatherBiasLodAMD = 5009, SpvCapabilityImageGatherBiasLodAMD = 5009,
SpvCapabilityFragmentMaskAMD = 5010, SpvCapabilityFragmentMaskAMD = 5010,
@ -1145,7 +1153,10 @@ typedef enum SpvCapability_ {
SpvCapabilityOptNoneINTEL = 6094, SpvCapabilityOptNoneINTEL = 6094,
SpvCapabilityAtomicFloat16AddEXT = 6095, SpvCapabilityAtomicFloat16AddEXT = 6095,
SpvCapabilityDebugInfoModuleINTEL = 6114, SpvCapabilityDebugInfoModuleINTEL = 6114,
SpvCapabilityBFloat16ConversionINTEL = 6115,
SpvCapabilitySplitBarrierINTEL = 6141, SpvCapabilitySplitBarrierINTEL = 6141,
SpvCapabilityFPGAKernelAttributesv2INTEL = 6161,
SpvCapabilityFPGALatencyControlINTEL = 6171,
SpvCapabilityFPGAArgumentInterfacesINTEL = 6174, SpvCapabilityFPGAArgumentInterfacesINTEL = 6174,
SpvCapabilityGroupUniformArithmeticKHR = 6400, SpvCapabilityGroupUniformArithmeticKHR = 6400,
SpvCapabilityMax = 0x7fffffff, SpvCapabilityMax = 0x7fffffff,
@ -1631,6 +1642,10 @@ typedef enum SpvOp_ {
SpvOpRayQueryConfirmIntersectionKHR = 4476, SpvOpRayQueryConfirmIntersectionKHR = 4476,
SpvOpRayQueryProceedKHR = 4477, SpvOpRayQueryProceedKHR = 4477,
SpvOpRayQueryGetIntersectionTypeKHR = 4479, SpvOpRayQueryGetIntersectionTypeKHR = 4479,
SpvOpImageSampleWeightedQCOM = 4480,
SpvOpImageBoxFilterQCOM = 4481,
SpvOpImageBlockMatchSSDQCOM = 4482,
SpvOpImageBlockMatchSADQCOM = 4483,
SpvOpGroupIAddNonUniformAMD = 5000, SpvOpGroupIAddNonUniformAMD = 5000,
SpvOpGroupFAddNonUniformAMD = 5001, SpvOpGroupFAddNonUniformAMD = 5001,
SpvOpGroupFMinNonUniformAMD = 5002, SpvOpGroupFMinNonUniformAMD = 5002,
@ -1948,6 +1963,8 @@ typedef enum SpvOp_ {
SpvOpTypeStructContinuedINTEL = 6090, SpvOpTypeStructContinuedINTEL = 6090,
SpvOpConstantCompositeContinuedINTEL = 6091, SpvOpConstantCompositeContinuedINTEL = 6091,
SpvOpSpecConstantCompositeContinuedINTEL = 6092, SpvOpSpecConstantCompositeContinuedINTEL = 6092,
SpvOpConvertFToBF16INTEL = 6116,
SpvOpConvertBF16ToFINTEL = 6117,
SpvOpControlBarrierArriveINTEL = 6142, SpvOpControlBarrierArriveINTEL = 6142,
SpvOpControlBarrierWaitINTEL = 6143, SpvOpControlBarrierWaitINTEL = 6143,
SpvOpGroupIMulKHR = 6401, SpvOpGroupIMulKHR = 6401,
@ -2339,6 +2356,10 @@ inline void SpvHasResultAndType(SpvOp opcode, bool *hasResult, bool *hasResultTy
case SpvOpRayQueryConfirmIntersectionKHR: *hasResult = false; *hasResultType = false; break; case SpvOpRayQueryConfirmIntersectionKHR: *hasResult = false; *hasResultType = false; break;
case SpvOpRayQueryProceedKHR: *hasResult = true; *hasResultType = true; break; case SpvOpRayQueryProceedKHR: *hasResult = true; *hasResultType = true; break;
case SpvOpRayQueryGetIntersectionTypeKHR: *hasResult = true; *hasResultType = true; break; case SpvOpRayQueryGetIntersectionTypeKHR: *hasResult = true; *hasResultType = true; break;
case SpvOpImageSampleWeightedQCOM: *hasResult = true; *hasResultType = true; break;
case SpvOpImageBoxFilterQCOM: *hasResult = true; *hasResultType = true; break;
case SpvOpImageBlockMatchSSDQCOM: *hasResult = true; *hasResultType = true; break;
case SpvOpImageBlockMatchSADQCOM: *hasResult = true; *hasResultType = true; break;
case SpvOpGroupIAddNonUniformAMD: *hasResult = true; *hasResultType = true; break; case SpvOpGroupIAddNonUniformAMD: *hasResult = true; *hasResultType = true; break;
case SpvOpGroupFAddNonUniformAMD: *hasResult = true; *hasResultType = true; break; case SpvOpGroupFAddNonUniformAMD: *hasResult = true; *hasResultType = true; break;
case SpvOpGroupFMinNonUniformAMD: *hasResult = true; *hasResultType = true; break; case SpvOpGroupFMinNonUniformAMD: *hasResult = true; *hasResultType = true; break;
@ -2651,6 +2672,8 @@ inline void SpvHasResultAndType(SpvOp opcode, bool *hasResult, bool *hasResultTy
case SpvOpTypeStructContinuedINTEL: *hasResult = false; *hasResultType = false; break; case SpvOpTypeStructContinuedINTEL: *hasResult = false; *hasResultType = false; break;
case SpvOpConstantCompositeContinuedINTEL: *hasResult = false; *hasResultType = false; break; case SpvOpConstantCompositeContinuedINTEL: *hasResult = false; *hasResultType = false; break;
case SpvOpSpecConstantCompositeContinuedINTEL: *hasResult = false; *hasResultType = false; break; case SpvOpSpecConstantCompositeContinuedINTEL: *hasResult = false; *hasResultType = false; break;
case SpvOpConvertFToBF16INTEL: *hasResult = true; *hasResultType = true; break;
case SpvOpConvertBF16ToFINTEL: *hasResult = true; *hasResultType = true; break;
case SpvOpControlBarrierArriveINTEL: *hasResult = false; *hasResultType = false; break; case SpvOpControlBarrierArriveINTEL: *hasResult = false; *hasResultType = false; break;
case SpvOpControlBarrierWaitINTEL: *hasResult = false; *hasResultType = false; break; case SpvOpControlBarrierWaitINTEL: *hasResult = false; *hasResultType = false; break;
case SpvOpGroupIMulKHR: *hasResult = true; *hasResultType = true; break; case SpvOpGroupIMulKHR: *hasResult = true; *hasResultType = true; break;

23
3rdparty/spirv-headers/include/spirv/unified1/spirv.hpp11 vendored
View File

@ -196,6 +196,7 @@ enum class ExecutionMode : unsigned {
NumSIMDWorkitemsINTEL = 5896, NumSIMDWorkitemsINTEL = 5896,
SchedulerTargetFmaxMhzINTEL = 5903, SchedulerTargetFmaxMhzINTEL = 5903,
StreamingInterfaceINTEL = 6154, StreamingInterfaceINTEL = 6154,
RegisterMapInterfaceINTEL = 6160,
NamedBarrierCountINTEL = 6417, NamedBarrierCountINTEL = 6417,
Max = 0x7fffffff, Max = 0x7fffffff,
}; };
@ -508,6 +509,8 @@ enum class Decoration : unsigned {
MaxByteOffsetId = 47, MaxByteOffsetId = 47,
NoSignedWrap = 4469, NoSignedWrap = 4469,
NoUnsignedWrap = 4470, NoUnsignedWrap = 4470,
WeightTextureQCOM = 4487,
BlockMatchTextureQCOM = 4488,
ExplicitInterpAMD = 4999, ExplicitInterpAMD = 4999,
OverrideCoverageNV = 5248, OverrideCoverageNV = 5248,
PassthroughNV = 5250, PassthroughNV = 5250,
@ -576,6 +579,8 @@ enum class Decoration : unsigned {
SingleElementVectorINTEL = 6085, SingleElementVectorINTEL = 6085,
VectorComputeCallableFunctionINTEL = 6087, VectorComputeCallableFunctionINTEL = 6087,
MediaBlockIOINTEL = 6140, MediaBlockIOINTEL = 6140,
LatencyControlLabelINTEL = 6172,
LatencyControlConstraintINTEL = 6173,
ConduitKernelArgumentINTEL = 6175, ConduitKernelArgumentINTEL = 6175,
RegisterMapKernelArgumentINTEL = 6176, RegisterMapKernelArgumentINTEL = 6176,
MMHostInterfaceAddressWidthINTEL = 6177, MMHostInterfaceAddressWidthINTEL = 6177,
@ -1014,6 +1019,9 @@ enum class Capability : unsigned {
RayQueryKHR = 4472, RayQueryKHR = 4472,
RayTraversalPrimitiveCullingKHR = 4478, RayTraversalPrimitiveCullingKHR = 4478,
RayTracingKHR = 4479, RayTracingKHR = 4479,
TextureSampleWeightedQCOM = 4484,
TextureBoxFilterQCOM = 4485,
TextureBlockMatchQCOM = 4486,
Float16ImageAMD = 5008, Float16ImageAMD = 5008,
ImageGatherBiasLodAMD = 5009, ImageGatherBiasLodAMD = 5009,
FragmentMaskAMD = 5010, FragmentMaskAMD = 5010,
@ -1141,7 +1149,10 @@ enum class Capability : unsigned {
OptNoneINTEL = 6094, OptNoneINTEL = 6094,
AtomicFloat16AddEXT = 6095, AtomicFloat16AddEXT = 6095,
DebugInfoModuleINTEL = 6114, DebugInfoModuleINTEL = 6114,
BFloat16ConversionINTEL = 6115,
SplitBarrierINTEL = 6141, SplitBarrierINTEL = 6141,
FPGAKernelAttributesv2INTEL = 6161,
FPGALatencyControlINTEL = 6171,
FPGAArgumentInterfacesINTEL = 6174, FPGAArgumentInterfacesINTEL = 6174,
GroupUniformArithmeticKHR = 6400, GroupUniformArithmeticKHR = 6400,
Max = 0x7fffffff, Max = 0x7fffffff,
@ -1627,6 +1638,10 @@ enum class Op : unsigned {
OpRayQueryConfirmIntersectionKHR = 4476, OpRayQueryConfirmIntersectionKHR = 4476,
OpRayQueryProceedKHR = 4477, OpRayQueryProceedKHR = 4477,
OpRayQueryGetIntersectionTypeKHR = 4479, OpRayQueryGetIntersectionTypeKHR = 4479,
OpImageSampleWeightedQCOM = 4480,
OpImageBoxFilterQCOM = 4481,
OpImageBlockMatchSSDQCOM = 4482,
OpImageBlockMatchSADQCOM = 4483,
OpGroupIAddNonUniformAMD = 5000, OpGroupIAddNonUniformAMD = 5000,
OpGroupFAddNonUniformAMD = 5001, OpGroupFAddNonUniformAMD = 5001,
OpGroupFMinNonUniformAMD = 5002, OpGroupFMinNonUniformAMD = 5002,
@ -1944,6 +1959,8 @@ enum class Op : unsigned {
OpTypeStructContinuedINTEL = 6090, OpTypeStructContinuedINTEL = 6090,
OpConstantCompositeContinuedINTEL = 6091, OpConstantCompositeContinuedINTEL = 6091,
OpSpecConstantCompositeContinuedINTEL = 6092, OpSpecConstantCompositeContinuedINTEL = 6092,
OpConvertFToBF16INTEL = 6116,
OpConvertBF16ToFINTEL = 6117,
OpControlBarrierArriveINTEL = 6142, OpControlBarrierArriveINTEL = 6142,
OpControlBarrierWaitINTEL = 6143, OpControlBarrierWaitINTEL = 6143,
OpGroupIMulKHR = 6401, OpGroupIMulKHR = 6401,
@ -2335,6 +2352,10 @@ inline void HasResultAndType(Op opcode, bool *hasResult, bool *hasResultType) {
case Op::OpRayQueryConfirmIntersectionKHR: *hasResult = false; *hasResultType = false; break; case Op::OpRayQueryConfirmIntersectionKHR: *hasResult = false; *hasResultType = false; break;
case Op::OpRayQueryProceedKHR: *hasResult = true; *hasResultType = true; break; case Op::OpRayQueryProceedKHR: *hasResult = true; *hasResultType = true; break;
case Op::OpRayQueryGetIntersectionTypeKHR: *hasResult = true; *hasResultType = true; break; case Op::OpRayQueryGetIntersectionTypeKHR: *hasResult = true; *hasResultType = true; break;
case Op::OpImageSampleWeightedQCOM: *hasResult = true; *hasResultType = true; break;
case Op::OpImageBoxFilterQCOM: *hasResult = true; *hasResultType = true; break;
case Op::OpImageBlockMatchSSDQCOM: *hasResult = true; *hasResultType = true; break;
case Op::OpImageBlockMatchSADQCOM: *hasResult = true; *hasResultType = true; break;
case Op::OpGroupIAddNonUniformAMD: *hasResult = true; *hasResultType = true; break; case Op::OpGroupIAddNonUniformAMD: *hasResult = true; *hasResultType = true; break;
case Op::OpGroupFAddNonUniformAMD: *hasResult = true; *hasResultType = true; break; case Op::OpGroupFAddNonUniformAMD: *hasResult = true; *hasResultType = true; break;
case Op::OpGroupFMinNonUniformAMD: *hasResult = true; *hasResultType = true; break; case Op::OpGroupFMinNonUniformAMD: *hasResult = true; *hasResultType = true; break;
@ -2647,6 +2668,8 @@ inline void HasResultAndType(Op opcode, bool *hasResult, bool *hasResultType) {
case Op::OpTypeStructContinuedINTEL: *hasResult = false; *hasResultType = false; break; case Op::OpTypeStructContinuedINTEL: *hasResult = false; *hasResultType = false; break;
case Op::OpConstantCompositeContinuedINTEL: *hasResult = false; *hasResultType = false; break; case Op::OpConstantCompositeContinuedINTEL: *hasResult = false; *hasResultType = false; break;
case Op::OpSpecConstantCompositeContinuedINTEL: *hasResult = false; *hasResultType = false; break; case Op::OpSpecConstantCompositeContinuedINTEL: *hasResult = false; *hasResultType = false; break;
case Op::OpConvertFToBF16INTEL: *hasResult = true; *hasResultType = true; break;
case Op::OpConvertBF16ToFINTEL: *hasResult = true; *hasResultType = true; break;
case Op::OpControlBarrierArriveINTEL: *hasResult = false; *hasResultType = false; break; case Op::OpControlBarrierArriveINTEL: *hasResult = false; *hasResultType = false; break;
case Op::OpControlBarrierWaitINTEL: *hasResult = false; *hasResultType = false; break; case Op::OpControlBarrierWaitINTEL: *hasResult = false; *hasResultType = false; break;
case Op::OpGroupIMulKHR: *hasResult = true; *hasResultType = true; break; case Op::OpGroupIMulKHR: *hasResult = true; *hasResultType = true; break;

17
3rdparty/spirv-headers/include/spirv/unified1/spirv.json vendored
View File

@ -215,6 +215,7 @@
"NumSIMDWorkitemsINTEL": 5896, "NumSIMDWorkitemsINTEL": 5896,
"SchedulerTargetFmaxMhzINTEL": 5903, "SchedulerTargetFmaxMhzINTEL": 5903,
"StreamingInterfaceINTEL": 6154, "StreamingInterfaceINTEL": 6154,
"RegisterMapInterfaceINTEL": 6160,
"NamedBarrierCountINTEL": 6417 "NamedBarrierCountINTEL": 6417
} }
}, },
@ -534,6 +535,8 @@
"MaxByteOffsetId": 47, "MaxByteOffsetId": 47,
"NoSignedWrap": 4469, "NoSignedWrap": 4469,
"NoUnsignedWrap": 4470, "NoUnsignedWrap": 4470,
"WeightTextureQCOM": 4487,
"BlockMatchTextureQCOM": 4488,
"ExplicitInterpAMD": 4999, "ExplicitInterpAMD": 4999,
"OverrideCoverageNV": 5248, "OverrideCoverageNV": 5248,
"PassthroughNV": 5250, "PassthroughNV": 5250,
@ -602,6 +605,8 @@
"SingleElementVectorINTEL": 6085, "SingleElementVectorINTEL": 6085,
"VectorComputeCallableFunctionINTEL": 6087, "VectorComputeCallableFunctionINTEL": 6087,
"MediaBlockIOINTEL": 6140, "MediaBlockIOINTEL": 6140,
"LatencyControlLabelINTEL": 6172,
"LatencyControlConstraintINTEL": 6173,
"ConduitKernelArgumentINTEL": 6175, "ConduitKernelArgumentINTEL": 6175,
"RegisterMapKernelArgumentINTEL": 6176, "RegisterMapKernelArgumentINTEL": 6176,
"MMHostInterfaceAddressWidthINTEL": 6177, "MMHostInterfaceAddressWidthINTEL": 6177,
@ -994,6 +999,9 @@
"RayQueryKHR": 4472, "RayQueryKHR": 4472,
"RayTraversalPrimitiveCullingKHR": 4478, "RayTraversalPrimitiveCullingKHR": 4478,
"RayTracingKHR": 4479, "RayTracingKHR": 4479,
"TextureSampleWeightedQCOM": 4484,
"TextureBoxFilterQCOM": 4485,
"TextureBlockMatchQCOM": 4486,
"Float16ImageAMD": 5008, "Float16ImageAMD": 5008,
"ImageGatherBiasLodAMD": 5009, "ImageGatherBiasLodAMD": 5009,
"FragmentMaskAMD": 5010, "FragmentMaskAMD": 5010,
@ -1121,7 +1129,10 @@
"OptNoneINTEL": 6094, "OptNoneINTEL": 6094,
"AtomicFloat16AddEXT": 6095, "AtomicFloat16AddEXT": 6095,
"DebugInfoModuleINTEL": 6114, "DebugInfoModuleINTEL": 6114,
"BFloat16ConversionINTEL": 6115,
"SplitBarrierINTEL": 6141, "SplitBarrierINTEL": 6141,
"FPGAKernelAttributesv2INTEL": 6161,
"FPGALatencyControlINTEL": 6171,
"FPGAArgumentInterfacesINTEL": 6174, "FPGAArgumentInterfacesINTEL": 6174,
"GroupUniformArithmeticKHR": 6400 "GroupUniformArithmeticKHR": 6400
} }
@ -1617,6 +1628,10 @@
"OpRayQueryConfirmIntersectionKHR": 4476, "OpRayQueryConfirmIntersectionKHR": 4476,
"OpRayQueryProceedKHR": 4477, "OpRayQueryProceedKHR": 4477,
"OpRayQueryGetIntersectionTypeKHR": 4479, "OpRayQueryGetIntersectionTypeKHR": 4479,
"OpImageSampleWeightedQCOM": 4480,
"OpImageBoxFilterQCOM": 4481,
"OpImageBlockMatchSSDQCOM": 4482,
"OpImageBlockMatchSADQCOM": 4483,
"OpGroupIAddNonUniformAMD": 5000, "OpGroupIAddNonUniformAMD": 5000,
"OpGroupFAddNonUniformAMD": 5001, "OpGroupFAddNonUniformAMD": 5001,
"OpGroupFMinNonUniformAMD": 5002, "OpGroupFMinNonUniformAMD": 5002,
@ -1934,6 +1949,8 @@
"OpTypeStructContinuedINTEL": 6090, "OpTypeStructContinuedINTEL": 6090,
"OpConstantCompositeContinuedINTEL": 6091, "OpConstantCompositeContinuedINTEL": 6091,
"OpSpecConstantCompositeContinuedINTEL": 6092, "OpSpecConstantCompositeContinuedINTEL": 6092,
"OpConvertFToBF16INTEL": 6116,
"OpConvertBF16ToFINTEL": 6117,
"OpControlBarrierArriveINTEL": 6142, "OpControlBarrierArriveINTEL": 6142,
"OpControlBarrierWaitINTEL": 6143, "OpControlBarrierWaitINTEL": 6143,
"OpGroupIMulKHR": 6401, "OpGroupIMulKHR": 6401,