From 03279fe3c1859663b90938c590c7a3a7780a73df Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=D0=91=D1=80=D0=B0=D0=BD=D0=B8=D0=BC=D0=B8=D1=80=20=D0=9A?= =?UTF-8?q?=D0=B0=D1=80=D0=B0=D1=9F=D0=B8=D1=9B?= Date: Fri, 12 Apr 2024 21:20:55 -0700 Subject: [PATCH] Updated spirv-headers. --- .../spirv-headers/include/spirv/spir-v.xml | 12 ++- .../spirv/unified1/spirv.core.grammar.json | 91 +++++++++++++++++++ .../include/spirv/unified1/spirv.h | 24 +++++ .../include/spirv/unified1/spirv.hpp11 | 28 ++++++ .../include/spirv/unified1/spirv.json | 27 +++++- 5 files changed, 175 insertions(+), 7 deletions(-) diff --git a/3rdparty/spirv-headers/include/spirv/spir-v.xml b/3rdparty/spirv-headers/include/spirv/spir-v.xml index 4a2de8314..52de097a3 100644 --- a/3rdparty/spirv-headers/include/spirv/spir-v.xml +++ b/3rdparty/spirv-headers/include/spirv/spir-v.xml @@ -92,7 +92,9 @@ - + + + @@ -208,8 +210,8 @@ - - + + @@ -269,8 +271,8 @@ - - + + diff --git a/3rdparty/spirv-headers/include/spirv/unified1/spirv.core.grammar.json b/3rdparty/spirv-headers/include/spirv/unified1/spirv.core.grammar.json index 03f35957f..5d904cae1 100644 --- a/3rdparty/spirv-headers/include/spirv/unified1/spirv.core.grammar.json +++ b/3rdparty/spirv-headers/include/spirv/unified1/spirv.core.grammar.json @@ -6251,6 +6251,24 @@ "capabilities" : [ "BindlessTextureNV" ], "version" : "None" }, + { + "opname" : "OpRawAccessChainNV", + "class" : "Memory", + "opcode" : 5398, + "operands" : [ + { "kind" : "IdResultType" }, + { "kind" : "IdResult" }, + { "kind" : "IdRef", "name" : "'Base'" }, + { "kind" : "IdRef", "name" : "'Byte stride'" }, + { "kind" : "IdRef", "name" : "'Element index'" }, + { "kind" : "IdRef", "name" : "'Byte offset'" }, + { "kind" : "RawAccessChainOperands", "quantifier" : "?" } + ], + "capabilities" : [ + "RawAccessChainsNV" + ], + "version" : "None" + }, { "opname" : "OpSubgroupShuffleINTEL", "class" : "Group", @@ -10667,6 +10685,28 @@ } ] }, + { + "category" : "BitEnum", + "kind" : "RawAccessChainOperands", + "enumerants" : [ + { + "enumerant" : "None", + "value" : "0x0000" + }, + { + "enumerant" : "RobustnessPerComponentNV", + "value" : "0x0001", + "capabilities" : [ "RawAccessChainsNV" ], + "version" : "None" + }, + { + "enumerant" : "RobustnessPerElementNV", + "value" : "0x0002", + "capabilities" : [ "RawAccessChainsNV" ], + "version" : "None" + } + ] + }, { "category" : "ValueEnum", "kind" : "SourceLanguage", @@ -11660,6 +11700,33 @@ ], "capabilities" : [ "VectorComputeINTEL" ], "version" : "None" + }, + { + "enumerant" : "MaximumRegistersINTEL", + "value" : 6461, + "parameters" : [ + { "kind" : "LiteralInteger", "name" : "'Number of Registers'" } + ], + "capabilities" : [ "RegisterLimitsINTEL" ], + "version" : "None" + }, + { + "enumerant" : "MaximumRegistersIdINTEL", + "value" : 6462, + "parameters" : [ + { "kind" : "IdRef", "name" : "'Number of Registers'" } + ], + "capabilities" : [ "RegisterLimitsINTEL" ], + "version" : "None" + }, + { + "enumerant" : "NamedMaximumRegistersINTEL", + "value" : 6463, + "parameters" : [ + { "kind" : "NamedMaximumNumberOfRegisters", "name" : "'Named Maximum Number of Registers'" } + ], + "capabilities" : [ "RegisterLimitsINTEL" ], + "version" : "None" } ] }, @@ -16056,6 +16123,12 @@ "extensions" : [ "SPV_NV_displacement_micromap" ], "version" : "None" }, + { + "enumerant" : "RawAccessChainsNV", + "value" : 5414, + "extensions" : [ "SPV_NV_raw_access_chains" ], + "version" : "None" + }, { "enumerant" : "SubgroupShuffleINTEL", "value" : 5568, @@ -16497,6 +16570,12 @@ "value" : 6441, "extensions" : [ "SPV_INTEL_cache_controls" ], "version" : "None" + }, + { + "enumerant" : "RegisterLimitsINTEL", + "value" : 6460, + "extensions" : [ "SPV_INTEL_maximum_registers" ], + "version" : "None" } ] }, @@ -16734,6 +16813,18 @@ } ] }, + { + "category" : "ValueEnum", + "kind" : "NamedMaximumNumberOfRegisters", + "enumerants" : [ + { + "enumerant" : "AutoINTEL", + "value" : 0, + "capabilities" : [ "RegisterLimitsINTEL" ], + "version" : "None" + } + ] + }, { "category" : "Id", "kind" : "IdResultType", diff --git a/3rdparty/spirv-headers/include/spirv/unified1/spirv.h b/3rdparty/spirv-headers/include/spirv/unified1/spirv.h index 96928b11e..e544a853d 100644 --- a/3rdparty/spirv-headers/include/spirv/unified1/spirv.h +++ b/3rdparty/spirv-headers/include/spirv/unified1/spirv.h @@ -219,6 +219,9 @@ typedef enum SpvExecutionMode_ { SpvExecutionModeStreamingInterfaceINTEL = 6154, SpvExecutionModeRegisterMapInterfaceINTEL = 6160, SpvExecutionModeNamedBarrierCountINTEL = 6417, + SpvExecutionModeMaximumRegistersINTEL = 6461, + SpvExecutionModeMaximumRegistersIdINTEL = 6462, + SpvExecutionModeNamedMaximumRegistersINTEL = 6463, SpvExecutionModeMax = 0x7fffffff, } SpvExecutionMode; @@ -1156,6 +1159,7 @@ typedef enum SpvCapability_ { SpvCapabilityRayQueryPositionFetchKHR = 5391, SpvCapabilityAtomicFloat16VectorNV = 5404, SpvCapabilityRayTracingDisplacementMicromapNV = 5409, + SpvCapabilityRawAccessChainsNV = 5414, SpvCapabilitySubgroupShuffleINTEL = 5568, SpvCapabilitySubgroupBufferBlockIOINTEL = 5569, SpvCapabilitySubgroupImageBlockIOINTEL = 5570, @@ -1229,6 +1233,7 @@ typedef enum SpvCapability_ { SpvCapabilityGroupUniformArithmeticKHR = 6400, SpvCapabilityMaskedGatherScatterINTEL = 6427, SpvCapabilityCacheControlsINTEL = 6441, + SpvCapabilityRegisterLimitsINTEL = 6460, SpvCapabilityMax = 0x7fffffff, } SpvCapability; @@ -1397,6 +1402,23 @@ typedef enum SpvStoreCacheControl_ { SpvStoreCacheControlMax = 0x7fffffff, } SpvStoreCacheControl; +typedef enum SpvNamedMaximumNumberOfRegisters_ { + SpvNamedMaximumNumberOfRegistersAutoINTEL = 0, + SpvNamedMaximumNumberOfRegistersMax = 0x7fffffff, +} SpvNamedMaximumNumberOfRegisters; + +typedef enum SpvRawAccessChainOperandsShift_ { + SpvRawAccessChainOperandsRobustnessPerComponentNVShift = 0, + SpvRawAccessChainOperandsRobustnessPerElementNVShift = 1, + SpvRawAccessChainOperandsMax = 0x7fffffff, +} SpvRawAccessChainOperandsShift; + +typedef enum SpvRawAccessChainOperandsMask_ { + SpvRawAccessChainOperandsMaskNone = 0, + SpvRawAccessChainOperandsRobustnessPerComponentNVMask = 0x00000001, + SpvRawAccessChainOperandsRobustnessPerElementNVMask = 0x00000002, +} SpvRawAccessChainOperandsMask; + typedef enum SpvOp_ { SpvOpNop = 0, SpvOpUndef = 1, @@ -1874,6 +1896,7 @@ typedef enum SpvOp_ { SpvOpConvertUToSampledImageNV = 5395, SpvOpConvertSampledImageToUNV = 5396, SpvOpSamplerImageAddressingModeNV = 5397, + SpvOpRawAccessChainNV = 5398, SpvOpSubgroupShuffleINTEL = 5571, SpvOpSubgroupShuffleDownINTEL = 5572, SpvOpSubgroupShuffleUpINTEL = 5573, @@ -2608,6 +2631,7 @@ inline void SpvHasResultAndType(SpvOp opcode, bool *hasResult, bool *hasResultTy case SpvOpConvertUToSampledImageNV: *hasResult = true; *hasResultType = true; break; case SpvOpConvertSampledImageToUNV: *hasResult = true; *hasResultType = true; break; case SpvOpSamplerImageAddressingModeNV: *hasResult = false; *hasResultType = false; break; + case SpvOpRawAccessChainNV: *hasResult = true; *hasResultType = true; break; case SpvOpSubgroupShuffleINTEL: *hasResult = true; *hasResultType = true; break; case SpvOpSubgroupShuffleDownINTEL: *hasResult = true; *hasResultType = true; break; case SpvOpSubgroupShuffleUpINTEL: *hasResult = true; *hasResultType = true; break; diff --git a/3rdparty/spirv-headers/include/spirv/unified1/spirv.hpp11 b/3rdparty/spirv-headers/include/spirv/unified1/spirv.hpp11 index 32f209fbb..d6b4fb7bc 100644 --- a/3rdparty/spirv-headers/include/spirv/unified1/spirv.hpp11 +++ b/3rdparty/spirv-headers/include/spirv/unified1/spirv.hpp11 @@ -215,6 +215,9 @@ enum class ExecutionMode : unsigned { StreamingInterfaceINTEL = 6154, RegisterMapInterfaceINTEL = 6160, NamedBarrierCountINTEL = 6417, + MaximumRegistersINTEL = 6461, + MaximumRegistersIdINTEL = 6462, + NamedMaximumRegistersINTEL = 6463, Max = 0x7fffffff, }; @@ -1152,6 +1155,7 @@ enum class Capability : unsigned { RayQueryPositionFetchKHR = 5391, AtomicFloat16VectorNV = 5404, RayTracingDisplacementMicromapNV = 5409, + RawAccessChainsNV = 5414, SubgroupShuffleINTEL = 5568, SubgroupBufferBlockIOINTEL = 5569, SubgroupImageBlockIOINTEL = 5570, @@ -1225,6 +1229,7 @@ enum class Capability : unsigned { GroupUniformArithmeticKHR = 6400, MaskedGatherScatterINTEL = 6427, CacheControlsINTEL = 6441, + RegisterLimitsINTEL = 6460, Max = 0x7fffffff, }; @@ -1393,6 +1398,23 @@ enum class StoreCacheControl : unsigned { Max = 0x7fffffff, }; +enum class NamedMaximumNumberOfRegisters : unsigned { + AutoINTEL = 0, + Max = 0x7fffffff, +}; + +enum class RawAccessChainOperandsShift : unsigned { + RobustnessPerComponentNV = 0, + RobustnessPerElementNV = 1, + Max = 0x7fffffff, +}; + +enum class RawAccessChainOperandsMask : unsigned { + MaskNone = 0, + RobustnessPerComponentNV = 0x00000001, + RobustnessPerElementNV = 0x00000002, +}; + enum class Op : unsigned { OpNop = 0, OpUndef = 1, @@ -1870,6 +1892,7 @@ enum class Op : unsigned { OpConvertUToSampledImageNV = 5395, OpConvertSampledImageToUNV = 5396, OpSamplerImageAddressingModeNV = 5397, + OpRawAccessChainNV = 5398, OpSubgroupShuffleINTEL = 5571, OpSubgroupShuffleDownINTEL = 5572, OpSubgroupShuffleUpINTEL = 5573, @@ -2604,6 +2627,7 @@ inline void HasResultAndType(Op opcode, bool *hasResult, bool *hasResultType) { case Op::OpConvertUToSampledImageNV: *hasResult = true; *hasResultType = true; break; case Op::OpConvertSampledImageToUNV: *hasResult = true; *hasResultType = true; break; case Op::OpSamplerImageAddressingModeNV: *hasResult = false; *hasResultType = false; break; + case Op::OpRawAccessChainNV: *hasResult = true; *hasResultType = true; break; case Op::OpSubgroupShuffleINTEL: *hasResult = true; *hasResultType = true; break; case Op::OpSubgroupShuffleDownINTEL: *hasResult = true; *hasResultType = true; break; case Op::OpSubgroupShuffleUpINTEL: *hasResult = true; *hasResultType = true; break; @@ -2908,6 +2932,10 @@ constexpr CooperativeMatrixOperandsMask operator|(CooperativeMatrixOperandsMask constexpr CooperativeMatrixOperandsMask operator&(CooperativeMatrixOperandsMask a, CooperativeMatrixOperandsMask b) { return CooperativeMatrixOperandsMask(unsigned(a) & unsigned(b)); } constexpr CooperativeMatrixOperandsMask operator^(CooperativeMatrixOperandsMask a, CooperativeMatrixOperandsMask b) { return CooperativeMatrixOperandsMask(unsigned(a) ^ unsigned(b)); } constexpr CooperativeMatrixOperandsMask operator~(CooperativeMatrixOperandsMask a) { return CooperativeMatrixOperandsMask(~unsigned(a)); } +constexpr RawAccessChainOperandsMask operator|(RawAccessChainOperandsMask a, RawAccessChainOperandsMask b) { return RawAccessChainOperandsMask(unsigned(a) | unsigned(b)); } +constexpr RawAccessChainOperandsMask operator&(RawAccessChainOperandsMask a, RawAccessChainOperandsMask b) { return RawAccessChainOperandsMask(unsigned(a) & unsigned(b)); } +constexpr RawAccessChainOperandsMask operator^(RawAccessChainOperandsMask a, RawAccessChainOperandsMask b) { return RawAccessChainOperandsMask(unsigned(a) ^ unsigned(b)); } +constexpr RawAccessChainOperandsMask operator~(RawAccessChainOperandsMask a) { return RawAccessChainOperandsMask(~unsigned(a)); } } // end namespace spv diff --git a/3rdparty/spirv-headers/include/spirv/unified1/spirv.json b/3rdparty/spirv-headers/include/spirv/unified1/spirv.json index a47a1f6ed..204a9c569 100644 --- a/3rdparty/spirv-headers/include/spirv/unified1/spirv.json +++ b/3rdparty/spirv-headers/include/spirv/unified1/spirv.json @@ -233,7 +233,10 @@ "FPFastMathDefault": 6028, "StreamingInterfaceINTEL": 6154, "RegisterMapInterfaceINTEL": 6160, - "NamedBarrierCountINTEL": 6417 + "NamedBarrierCountINTEL": 6417, + "MaximumRegistersINTEL": 6461, + "MaximumRegistersIdINTEL": 6462, + "NamedMaximumRegistersINTEL": 6463 } }, { @@ -1129,6 +1132,7 @@ "RayQueryPositionFetchKHR": 5391, "AtomicFloat16VectorNV": 5404, "RayTracingDisplacementMicromapNV": 5409, + "RawAccessChainsNV": 5414, "SubgroupShuffleINTEL": 5568, "SubgroupBufferBlockIOINTEL": 5569, "SubgroupImageBlockIOINTEL": 5570, @@ -1201,7 +1205,8 @@ "GlobalVariableFPGADecorationsINTEL": 6189, "GroupUniformArithmeticKHR": 6400, "MaskedGatherScatterINTEL": 6427, - "CacheControlsINTEL": 6441 + "CacheControlsINTEL": 6441, + "RegisterLimitsINTEL": 6460 } }, { @@ -1388,6 +1393,23 @@ "StreamingINTEL": 3 } }, + { + "Name": "NamedMaximumNumberOfRegisters", + "Type": "Value", + "Values": + { + "AutoINTEL": 0 + } + }, + { + "Name": "RawAccessChainOperands", + "Type": "Bit", + "Values": + { + "RobustnessPerComponentNV": 0, + "RobustnessPerElementNV": 1 + } + }, { "Name": "Op", "Type": "Value", @@ -1869,6 +1891,7 @@ "OpConvertUToSampledImageNV": 5395, "OpConvertSampledImageToUNV": 5396, "OpSamplerImageAddressingModeNV": 5397, + "OpRawAccessChainNV": 5398, "OpSubgroupShuffleINTEL": 5571, "OpSubgroupShuffleDownINTEL": 5572, "OpSubgroupShuffleUpINTEL": 5573,