mirror of
https://github.com/acpica/acpica/
synced 2025-02-07 00:54:16 +03:00
462 lines
10 KiB
Plaintext
Executable File
462 lines
10 KiB
Plaintext
Executable File
DefinitionBlock(
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"hndl0038.aml", // Output filename
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"DSDT", // Signature
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0x02, // DSDT Revision
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"Intel", // OEMID
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"Many", // TABLE ID
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0x00000001 // OEM Revision
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) {
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/*
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* ACPICA API Test Suite
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* Misc Handlers test 0038
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*/
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Include("../asl/tblm_aux.asl")
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// Operation Region
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OperationRegion(OPR0, SystemMemory, 0, 0x10000)
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OperationRegion(OPR1, SystemIO, 0x21000, 0x11000)
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OperationRegion(OPR2, PCI_Config, 0x32000, 0x12000)
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OperationRegion(OPR3, EmbeddedControl, 0x45000, 0x13000)
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OperationRegion(OPR4, SMBus, 0x69000, 0x14000)
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OperationRegion(OPR5, SystemCMOS, 0x83000, 0x15000)
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OperationRegion(OPR6, PciBarTarget, 0x98000, 0x16000)
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// OperationRegion(OPR7, UserDefRegionSpace, 0x100000, 0x17000)
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// Device
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Device(DEV0) {
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Name(s000, "DEV0")
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OperationRegion(OPR0, SystemMemory, 0x100000, 0x10000)
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OperationRegion(OPR1, SystemIO, 0x121000, 0x11000)
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}
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// Processor
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Processor(CPU0, 0x0, 0xFFFFFFFF, 0x0) {
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Name(s000, "CPU0")
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OperationRegion(OPR2, PCI_Config, 0x132000, 0x12000)
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OperationRegion(OPR3, EmbeddedControl, 0x145000, 0x13000)
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OperationRegion(OPR4, SMBus, 0x169000, 0x14000)
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}
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// Thermal Zone
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ThermalZone(TZN0) {
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Name(s000, "TZN0")
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OperationRegion(OPR5, SystemCMOS, 0x183000, 0x15000)
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OperationRegion(OPR6, PciBarTarget, 0x198000, 0x16000)
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}
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// Device 1: check _REG calls co-ordination
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Device(DEV1) {
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Name(s000, "DEV0")
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OperationRegion(OPR0, SystemMemory, 0xB0000, 0x10000)
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Name(ACTV, 0)
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Name(DACT, 0)
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Name(DIFF, 0)
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Name(NERR, 0)
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Method(_REG, 2)
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{
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Store("_REG:", Debug)
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Store(arg0, Debug)
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Store(arg1, Debug)
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if (arg0) {
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Increment(NERR)
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} elseif (LGreater(arg1, 1)) {
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Increment(NERR)
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} else {
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if (arg1) {
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Increment(ACTV)
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} else {
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Increment(DACT)
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}
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Subtract(ACTV, DACT, DIFF)
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}
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}
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}
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/*
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* unsupported object types
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*/
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// Integer
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Name(INT0, 0xfedcba9876543210)
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// String
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Name(STR0, "source string")
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// Buffer
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Name(BUF0, Buffer(9){9,8,7,6,5,4,3,2,1})
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// Package
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Name(PAC0, Package(3) {
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0xfedcba987654321f,
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"test package",
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Buffer(9){19,18,17,16,15,14,13,12,11},
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})
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// Field Unit
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Field(OPR0, ByteAcc, NoLock, Preserve) {
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FLU0, 69,
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}
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// Event
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Event(EVE0)
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// Method
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Method(MMM0) {Return ("ff0X")}
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// Mutex
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Mutex(MTX0, 0)
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// Power Resource
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PowerResource(PWR0, 0, 0) {Name(s000, "PWR0")}
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// Buffer Field
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Createfield(BUF0, 0, 69, BFL0)
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Method(M000, 2)
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{
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Store (Sizeof (Arg1), Local0)
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while (Local0) {
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Decrement (Local0)
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Notify (Arg0, Derefof(Index(Arg1, Local0)))
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}
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}
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Method(TST0)
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{
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// Field Units
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Field(OPR0, ByteAcc, NoLock, Preserve) {FLU0, 70}
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Field(OPR1, ByteAcc, NoLock, Preserve) {FLU1, 71}
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Field(OPR2, ByteAcc, NoLock, Preserve) {FLU2, 72}
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Field(OPR3, ByteAcc, NoLock, Preserve) {FLU3, 73}
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Field(OPR4, BufferAcc, NoLock, Preserve) {FLU4, 74}
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Field(OPR5, ByteAcc, NoLock, Preserve) {FLU5, 75}
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Field(OPR6, ByteAcc, NoLock, Preserve) {FLU6, 76}
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Store (0xffffffffffffff00, FLU0)
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Store (0xffffffffffffff01, FLU1)
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Store (0xffffffffffffff02, FLU2)
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Store (0xffffffffffffff03, FLU3)
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// SMBus write requires Buffer
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// SMBus bidirectional buffer size
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// ACPI_SMBUS_BUFFER_SIZE 34
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Store (Buffer(34){0x04, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, FLU4)
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Store (0xffffffffffffff05, FLU5)
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Store (0xffffffffffffff06, FLU6)
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}
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Method(TST1)
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{
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// Field Units
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Field(\DEV0.OPR0, ByteAcc, NoLock, Preserve) {FLU0, 70}
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Field(\DEV0.OPR1, ByteAcc, NoLock, Preserve) {FLU1, 71}
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Field(\CPU0.OPR2, ByteAcc, NoLock, Preserve) {FLU2, 72}
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Field(\CPU0.OPR3, ByteAcc, NoLock, Preserve) {FLU3, 73}
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Field(\CPU0.OPR4, BufferAcc, NoLock, Preserve) {FLU4, 74}
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Field(\TZN0.OPR5, ByteAcc, NoLock, Preserve) {FLU5, 75}
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Field(\TZN0.OPR6, ByteAcc, NoLock, Preserve) {FLU6, 76}
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Store (0xffffffffffffff00, FLU0)
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Store (0xffffffffffffff01, FLU1)
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Store (0xffffffffffffff02, FLU2)
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Store (0xffffffffffffff03, FLU3)
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// SMBus write requires Buffer
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// SMBus bidirectional buffer size
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// ACPI_SMBUS_BUFFER_SIZE 34
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Store (Buffer(34){0x04, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, FLU4)
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Store (0xffffffffffffff05, FLU5)
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Store (0xffffffffffffff06, FLU6)
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}
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Method(TST2)
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{
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// Field Units
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Field(OPR0, ByteAcc, NoLock, Preserve) {FLU0, 70}
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Field(OPR1, ByteAcc, NoLock, Preserve) {FLU1, 71}
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Field(OPR2, ByteAcc, NoLock, Preserve) {FLU2, 72}
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// Field(OPR3, ByteAcc, NoLock, Preserve) {FLU3, 73}
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// Field(OPR4, BufferAcc, NoLock, Preserve) {FLU4, 74}
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Field(OPR5, ByteAcc, NoLock, Preserve) {FLU5, 75}
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Field(OPR6, ByteAcc, NoLock, Preserve) {FLU6, 76}
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Store (0xffffffffffffff00, FLU0)
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Store (0xffffffffffffff01, FLU1)
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Store (0xffffffffffffff02, FLU2)
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// Store (0xffffffffffffff03, FLU3)
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// SMBus write requires Buffer
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// SMBus bidirectional buffer size
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// ACPI_SMBUS_BUFFER_SIZE 34
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// Store (Buffer(34){0x04, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, FLU4)
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Store (0xffffffffffffff05, FLU5)
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Store (0xffffffffffffff06, FLU6)
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}
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Method(TST3)
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{
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// Field Units
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Field(\DEV0.OPR0, ByteAcc, NoLock, Preserve) {FLU0, 70}
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Field(\DEV0.OPR1, ByteAcc, NoLock, Preserve) {FLU1, 71}
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Field(\CPU0.OPR2, ByteAcc, NoLock, Preserve) {FLU2, 72}
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// Field(\CPU0.OPR3, ByteAcc, NoLock, Preserve) {FLU3, 73}
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// Field(\CPU0.OPR4, BufferAcc, NoLock, Preserve) {FLU4, 74}
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Field(\TZN0.OPR5, ByteAcc, NoLock, Preserve) {FLU5, 75}
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Field(\TZN0.OPR6, ByteAcc, NoLock, Preserve) {FLU6, 76}
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Store (0xffffffffffffff00, FLU0)
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Store (0xffffffffffffff01, FLU1)
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Store (0xffffffffffffff02, FLU2)
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// Store (0xffffffffffffff03, FLU3)
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// SMBus write requires Buffer
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// SMBus bidirectional buffer size
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// ACPI_SMBUS_BUFFER_SIZE 34
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// Store (Buffer(34){0x04, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, FLU4)
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Store (0xffffffffffffff05, FLU5)
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Store (0xffffffffffffff06, FLU6)
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}
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Method(TST4)
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{
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// Field Units
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Field(OPR0, ByteAcc, NoLock, Preserve) {FLU0, 14}
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Store (0x5aa5, FLU0)
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}
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Method(TST5)
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{
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// Field Units
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Field(OPR4, BufferAcc, NoLock, Preserve) {FLU4, 74}
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// SMBus write requires Buffer
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// SMBus bidirectional buffer size
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// ACPI_SMBUS_BUFFER_SIZE 34
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Store (Buffer(34){0x04, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, FLU4)
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}
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// For AtHndlrTest0038
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// Access dynamic OpRegions
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Method(TST6)
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{
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OperationRegion(OPR0, SystemMemory, 0x10001, 0x10000)
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OperationRegion(OPR1, SystemIO, 0x32001, 0x11000)
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OperationRegion(OPR2, PCI_Config, 0x44001, 0x12000)
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OperationRegion(OPR3, EmbeddedControl, 0x58001, 0x13000)
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OperationRegion(OPR4, SMBus, 0x7d001, 0x14000)
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OperationRegion(OPR5, SystemCMOS, 0x98001, 0x15000)
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OperationRegion(OPR6, PciBarTarget, 0xae001, 0x16000)
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// Field Units
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Field(OPR0, ByteAcc, NoLock, Preserve) {FLU0, 70}
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Field(OPR1, ByteAcc, NoLock, Preserve) {FLU1, 71}
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Field(OPR2, ByteAcc, NoLock, Preserve) {FLU2, 72}
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Field(OPR3, ByteAcc, NoLock, Preserve) {FLU3, 73}
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Field(OPR4, BufferAcc, NoLock, Preserve) {FLU4, 74}
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Field(OPR5, ByteAcc, NoLock, Preserve) {FLU5, 75}
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Field(OPR6, ByteAcc, NoLock, Preserve) {FLU6, 76}
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Store (0xffffffffffffff00, FLU0)
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Store (0xffffffffffffff01, FLU1)
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Store (0xffffffffffffff02, FLU2)
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Store (0xffffffffffffff03, FLU3)
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// SMBus write requires Buffer
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// SMBus bidirectional buffer size
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// ACPI_SMBUS_BUFFER_SIZE 34
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Store (Buffer(34){0x04, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, FLU4)
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Store (0xffffffffffffff05, FLU5)
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Store (0xffffffffffffff06, FLU6)
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}
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// Access both static and dynamic OpRegions
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Method(TST7)
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{
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// Static
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TST1()
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// Dynamic
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TST6()
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// Static, Root located
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TST0()
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}
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Device (PCI1) {
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OperationRegion (IDE1, PCI_Config, 0x00, 0xFF)
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Field (IDE1, DWordAcc, NoLock, Preserve) {
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Offset (0x6C),
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IPDC, 32}
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Name (_HID, EisaId ("PNP0A03"))
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Name (_CID, Package (0x03) {
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0x00102E4F,
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EisaId ("PNP0A01"),
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0x130FD041})
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Name (_ADR, 0x11)
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Name (_BBN, 0x11)
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Name (REGC, 0x00) // Count
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Name (REGE, 0x00) // NumErrors
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Name (REGS, 0xFF) // Status (Activate/DeActivate)
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Method(_REG, 2)
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{
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Store("\\PCI1._REG:", Debug)
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Store(arg0, Debug)
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Store(arg1, Debug)
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Increment(REGC)
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if (LNotEqual(arg0, 2)) { // PCI_Config
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Increment(REGE)
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} elseif (LAnd(LNotEqual(arg1, 1), LNotEqual(arg1, 0))) {
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Increment(REGE)
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} else {
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Store(arg1, REGS)
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}
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}
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// Device
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Device(DEVA) {Name(s000, "DEVA")}
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Method(ACC0)
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{
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Store("\\PCI1.ACC0:", Debug)
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Store(0xABCD, \PCI1.IPDC)
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Store(\PCI1.IPDC, Debug)
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}
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}
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Device (PCI2) {
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Device(DEVA) {
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Name(s000, "DEVA")
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OperationRegion (IDE1, PCI_Config, 0x100, 0xFF)
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Field (IDE1, DWordAcc, NoLock, Preserve) {
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Offset (0x6C),
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IPDC, 32}
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Name (_HID, EisaId ("XXX0A03"))
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Name (_CID, Package (0x03) {
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0x00102E4F,
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EisaId ("PNP0A03"),
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0x130FD041})
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Name (_ADR, 0x22)
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Name (_BBN, 0x22)
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Name (REGC, 0x00) // Count
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Name (REGE, 0x00) // NumErrors
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Name (REGS, 0xFF) // Status (Activate/DeActivate)
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Method(_REG, 2)
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{
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Store("\\PCI2.DEVA._REG:", Debug)
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Store(arg0, Debug)
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Store(arg1, Debug)
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Increment(REGC)
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if (LNotEqual(arg0, 2)) { // PCI_Config
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Increment(REGE)
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} elseif (LAnd(LNotEqual(arg1, 1), LNotEqual(arg1, 0))) {
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Increment(REGE)
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} else {
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Store(arg1, REGS)
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}
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}
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Method(ACC0)
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{
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Store("\\PCI2.DEVA.ACC0:", Debug)
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Store(0xABCD, \PCI2.DEVA.IPDC)
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Store(\PCI2.DEVA.IPDC, Debug)
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}
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}
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Device(DEVB) {
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Name(s000, "DEVB")
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OperationRegion (IDE1, PCI_Config, 0x200, 0xFF)
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Field (IDE1, DWordAcc, NoLock, Preserve) {
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Offset (0x6C),
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IPDC, 32}
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Name (_HID, EisaId ("XXX0A03"))
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Name (_CID, Package (0x03) {
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0x00102E4F,
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EisaId ("XXX0A03"),
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0x130FD041})
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Name (_ADR, 0x33)
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Name (_BBN, 0x33)
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Name (REGC, 0x00) // Count
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Name (REGE, 0x00) // NumErrors
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Name (REGS, 0xFF) // Status (Activate/DeActivate)
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Method(_REG, 2)
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{
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Store("\\PCI2.DEVB._REG:", Debug)
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Store(arg0, Debug)
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Store(arg1, Debug)
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Increment(REGC)
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if (LNotEqual(arg0, 2)) { // PCI_Config
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Increment(REGE)
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} elseif (LAnd(LNotEqual(arg1, 1), LNotEqual(arg1, 0))) {
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Increment(REGE)
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} else {
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Store(arg1, REGS)
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}
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}
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Method(ACC0)
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{
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Store("\\PCI2.DEVB.ACC0:", Debug)
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Store(0xABCD, \PCI2.DEVB.IPDC)
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Store(\PCI2.DEVB.IPDC, Debug)
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}
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}
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}
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}
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