Use the 32-bit register addresses whenever they are non-zero. This means
that the 32-bit addresses are favored over the 64-bit (GAS) addresses. The
64-bit addresses are only used if the 32-bit addresses are zero. This
change provides compatibility with all versions of Windows. The worst
case that this solves is when both the 32-bit and 64-bit addresses are
non-zero, but only the 32-bit addresses are actually valid. This appears
to happen in some BIOSes because in this case, Windows uses the 32-bit
addresses.
The Linux OS no longer wants to respond true for this string.
The only safe strings are windows-related as they represent
the tested path through the BIOS-provided ASL.
As per the ACPI specification, preserve (read/modify/write) all
bits that are defined as either reserved or ignored (PM control
control registers only.)
Ignored bits must be preserved according to the ACPI spec.
Usually this means a read/modify/write when writing to the register.
However, for status registers, writing a one means clear the event.
Writing a zero means preserve the event (do not clear.) This behavior
is clarified in the ACPI 4.0 spec, and the ACPICA code now simply
always writes a zero to the ignored bit.
Added a reader/writer locking mechanism to allow multiple
concurrent namespace walks (readers), but a dynamic table
unload will have exclusive access to the namespace. This fixes
a problem where a table unload could delete the portion of
the namespace that is currently being examined by a walk.
Adds a new file, utlock.c that implements the reader/writer
lock mechanism. ACPICA BZ 749.
Incorrect register length mismatch between the 32 and 64 bit
registers in some cases. Code was was checking the wrong pointer
for non-zero, should be looking at the address within the GAS
structure.
Fixes problem introduced in 20090220, "Split out PM1 status registers
from the FADT". Must check for the case where the PM1B status reg
does not exist, before the GAS structure is constructed.
Junk-uk Kim.
Fixes a problem where a WalkNamespace user function could have a
namespace node deleted out from under it due to the execution of
an AML Unload operator. A new mutex has been defined to exclude
these two activities. ACPICA BZ 749.
Removed locking for reads from the ACPI bit registers in PM1 Status,
Enable, Control, and PM2 Control. The lock is not required when
reading the single-bit registers. The AcpiGetRegisterUnlocked function
is no longer needed and has been removed. This will improve performance
for reads on these registers.
ACPICA BZ 760.
Remove all instances of this obsolete macro, since it is now a simple
reference to ->common.type. There were about 150 invocations of the
macro across 41 files.
Added AcpiHwWritePm1Control. This function writes both of the PM1
control registers (A/B). These registers are
different than than the PM1 A/B status and enable registers
in that different values can be written to the A/B registers.
Most notably, the SLP_TYP bits can be different, as per the
values returned from the _Sx predefined methods.
Now return AE_BAD_PARAMETER if the input register pointer is null,
and AE_BAD_ADDRESS if the register has an address of zero.
Previously, these cases simply returned AE_OK. For optional registers
such as PM1B status/enable/control, the caller should check for a valid
register address before calling.
ACPICA BZ 748.
The PM1B registers are mirrors of the PM1A registers with different
bits actually implemented. From the ACPI specification:
"Although the bits can be split between the two register blocks (each
register block has a unique pointer within the FADT), the bit positions
are maintained. The register block with unimplemented bits (that is, those
implemented in the other register block) always returns zeros, and
writes have no side effects"
This function was writing an optional PM1B status register twice.
The existing call to the low-level AcpiHwRegisterWrite automatically
handles a possibly split PM1 A/B register.
ACPICA BZ 751.
On read, shift B register bits above the A bits. On write, shift B bits
down to zero before writing the B register. New: AcpiHwReadMultiple,
AcpiHwWriteMultiple. These two functions now transparently handle the
(possible) split registers for PM1 Status, Enable, and Control.
Add new globals for the PM1 status registers (A/B), similar to the
way the PM1 enable registers are handled. Instead of overloading the
FADT Event Register blocks. This makes the code clearer and less prone
to error.
Add 2009 copyright to all module headers and signons, including the Linux
header. This affects virtually every file in the ACPICA core subsystem,
iASL compiler, and all utilities.
Previously, the table override mechanism was implemented for the
DSDT only. Now, any table in the RSDT/XSDT can be replaced by the
host OS. (including the DSDT).
This returns the FADT support to the original behavior, which is to
use default register widths. However, now check each register
definition and report a warning if it differs from the default.
This is a first step to moving away from the default widths, rather
than outright believing the widths in all FADTs for all machines,
considered rather dangerous until more data is obtained.
