mirrors/acpica
1
0
Fork 0
mirror of https://github.com/acpica/acpica/ synced 2025-01-07 10:04:53 +03:00
Code Issues Packages Projects Releases Wiki Activity

ACPI 3.0 support

Browse Source 
date	2005.02.17.18.05.00;	author rmoore1;	state Exp;
This commit is contained in:
aystarik 2005-06-29 20:07:42 +00:00
parent 68242ca9d1
commit 5662ba5ce1
2 changed files with 81 additions and 52 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
source/include/actbl.h
View File

@ -1,7 +1,7 @@
/******************************************************************************
*
* Name: actbl.h - Table data structures defined in ACPI specification
* $Revision: 1.66 $
* $Revision: 1.68 $
*
*****************************************************************************/
@ -9,7 +9,7 @@
*
* 1. Copyright Notice
*
* Some or all of this work - Copyright (c) 1999 - 2004, Intel Corp.
* Some or all of this work - Copyright (c) 1999 - 2005, Intel Corp.
* All rights reserved.
*
* 2. License
@ -345,6 +345,8 @@ typedef struct madt_local_sapic
UINT8 LocalSapicEid; /* SAPIC EID */
UINT8 Reserved [3]; /* Reserved - must be zero */
LOCAL_APIC_FLAGS
UINT32 ProcessorUID; /* Numeric UID - ACPI 3.0 */
char ProcessorUIDString[1]; /* String UID - ACPI 3.0 */
} MADT_LOCAL_SAPIC;
@ -357,7 +359,7 @@ typedef struct madt_interrupt_source
UINT8 ProcessorEid; /* Processor EID */
UINT8 IoSapicVector; /* Vector value for PMI interrupts */
UINT32 Interrupt; /* Global system interrupt */
UINT32 Reserved; /* Reserved - must be zero */
UINT32 Flags; /* Interrupt Source Flags */
} MADT_INTERRUPT_SOURCE;

125
source/include/actbl2.h
View File

@ -1,7 +1,7 @@
/******************************************************************************
*
* Name: actbl2.h - ACPI Specification Revision 2.0 Tables
* $Revision: 1.34 $
* $Revision: 1.40 $
*
*****************************************************************************/
@ -9,7 +9,7 @@
*
* 1. Copyright Notice
*
* Some or all of this work - Copyright (c) 1999 - 2003, Intel Corp.
* Some or all of this work - Copyright (c) 1999 - 2005, Intel Corp.
* All rights reserved.
*
* 2. License
@ -135,6 +135,7 @@
#define BAF_8042_KEYBOARD_CONTROLLER 0x0002
#define FADT2_REVISION_ID 3
#define FADT2_MINUS_REVISION_ID 2
#pragma pack(1)
@ -171,7 +172,7 @@ typedef struct facs_descriptor_rev2
UINT32 HardwareSignature; /* Hardware configuration signature */
UINT32 FirmwareWakingVector; /* 32bit physical address of the Firmware Waking Vector. */
UINT32 GlobalLock; /* Global Lock used to synchronize access to shared hardware resources */
UINT32 S4Bios_f : 1; /* S4Bios_f - Indicates if S4BIOS support is present */
UINT32_BIT S4Bios_f : 1; /* S4Bios_f - Indicates if S4BIOS support is present */
UINT32_BIT Reserved1 : 31; /* Must be 0 */
UINT64 XFirmwareWakingVector; /* 64bit physical address of the Firmware Waking Vector. */
UINT8 Version; /* Version of this table */
@ -181,61 +182,64 @@ typedef struct facs_descriptor_rev2
/*
* ACPI 2.0 Generic Address Structure (GAS)
* ACPI 2.0+ Generic Address Structure (GAS)
*/
typedef struct acpi_generic_address
{
UINT8 AddressSpaceId; /* Address space where struct or register exists. */
UINT8 RegisterBitWidth; /* Size in bits of given register */
UINT8 RegisterBitOffset; /* Bit offset within the register */
UINT8 Reserved; /* Must be 0 */
UINT8 AccessWidth; /* Minimum Access size (ACPI 3.0) */
UINT64 Address; /* 64-bit address of struct or register */
} ACPI_GENERIC_ADDRESS;
#define FADT_REV2_COMMON \
UINT32 V1_FirmwareCtrl; /* 32-bit physical address of FACS */ \
UINT32 V1_Dsdt; /* 32-bit physical address of DSDT */ \
UINT8 Reserved1; /* System Interrupt Model isn't used in ACPI 2.0*/ \
UINT8 Prefer_PM_Profile; /* Conveys preferred power management profile to OSPM. */ \
UINT16 SciInt; /* System vector of SCI interrupt */ \
UINT32 SmiCmd; /* Port address of SMI command port */ \
UINT8 AcpiEnable; /* Value to write to smi_cmd to enable ACPI */ \
UINT8 AcpiDisable; /* Value to write to smi_cmd to disable ACPI */ \
UINT8 S4BiosReq; /* Value to write to SMI CMD to enter S4BIOS state */ \
UINT8 PstateCnt; /* Processor performance state control*/ \
UINT32 V1_Pm1aEvtBlk; /* Port address of Power Mgt 1a AcpiEvent Reg Blk */ \
UINT32 V1_Pm1bEvtBlk; /* Port address of Power Mgt 1b AcpiEvent Reg Blk */ \
UINT32 V1_Pm1aCntBlk; /* Port address of Power Mgt 1a Control Reg Blk */ \
UINT32 V1_Pm1bCntBlk; /* Port address of Power Mgt 1b Control Reg Blk */ \
UINT32 V1_Pm2CntBlk; /* Port address of Power Mgt 2 Control Reg Blk */ \
UINT32 V1_PmTmrBlk; /* Port address of Power Mgt Timer Ctrl Reg Blk */ \
UINT32 V1_Gpe0Blk; /* Port addr of General Purpose AcpiEvent 0 Reg Blk */ \
UINT32 V1_Gpe1Blk; /* Port addr of General Purpose AcpiEvent 1 Reg Blk */ \
UINT8 Pm1EvtLen; /* Byte Length of ports at pm1X_evt_blk */ \
UINT8 Pm1CntLen; /* Byte Length of ports at pm1X_cnt_blk */ \
UINT8 Pm2CntLen; /* Byte Length of ports at pm2_cnt_blk */ \
UINT8 PmTmLen; /* Byte Length of ports at pm_tm_blk */ \
UINT8 Gpe0BlkLen; /* Byte Length of ports at gpe0_blk */ \
UINT8 Gpe1BlkLen; /* Byte Length of ports at gpe1_blk */ \
UINT8 Gpe1Base; /* Offset in gpe model where gpe1 events start */ \
UINT8 CstCnt; /* Support for the _CST object and C States change notification.*/ \
UINT16 Plvl2Lat; /* Worst case HW latency to enter/exit C2 state */ \
UINT16 Plvl3Lat; /* Worst case HW latency to enter/exit C3 state */ \
UINT16 FlushSize; /* Number of flush strides that need to be read */ \
UINT16 FlushStride; /* Processor's memory cache line width, in bytes */ \
UINT8 DutyOffset; /* Processor's duty cycle index in processor's P_CNT reg*/ \
UINT8 DutyWidth; /* Processor's duty cycle value bit width in P_CNT register.*/ \
UINT8 DayAlrm; /* Index to day-of-month alarm in RTC CMOS RAM */ \
UINT8 MonAlrm; /* Index to month-of-year alarm in RTC CMOS RAM */ \
UINT8 Century; /* Index to century in RTC CMOS RAM */ \
UINT16 IapcBootArch; /* IA-PC Boot Architecture Flags. See Table 5-10 for description*/
/*
* ACPI 2.0 Fixed ACPI Description Table (FADT)
* ACPI 2.0+ Fixed ACPI Description Table (FADT)
*/
typedef struct fadt_descriptor_rev2
{
ACPI_TABLE_HEADER_DEF /* ACPI common table header */
UINT32 V1_FirmwareCtrl; /* 32-bit physical address of FACS */
UINT32 V1_Dsdt; /* 32-bit physical address of DSDT */
UINT8 Reserved1; /* System Interrupt Model isn't used in ACPI 2.0*/
UINT8 Prefer_PM_Profile; /* Conveys preferred power management profile to OSPM. */
UINT16 SciInt; /* System vector of SCI interrupt */
UINT32 SmiCmd; /* Port address of SMI command port */
UINT8 AcpiEnable; /* Value to write to smi_cmd to enable ACPI */
UINT8 AcpiDisable; /* Value to write to smi_cmd to disable ACPI */
UINT8 S4BiosReq; /* Value to write to SMI CMD to enter S4BIOS state */
UINT8 PstateCnt; /* Processor performance state control*/
UINT32 V1_Pm1aEvtBlk; /* Port address of Power Mgt 1a AcpiEvent Reg Blk */
UINT32 V1_Pm1bEvtBlk; /* Port address of Power Mgt 1b AcpiEvent Reg Blk */
UINT32 V1_Pm1aCntBlk; /* Port address of Power Mgt 1a Control Reg Blk */
UINT32 V1_Pm1bCntBlk; /* Port address of Power Mgt 1b Control Reg Blk */
UINT32 V1_Pm2CntBlk; /* Port address of Power Mgt 2 Control Reg Blk */
UINT32 V1_PmTmrBlk; /* Port address of Power Mgt Timer Ctrl Reg Blk */
UINT32 V1_Gpe0Blk; /* Port addr of General Purpose AcpiEvent 0 Reg Blk */
UINT32 V1_Gpe1Blk; /* Port addr of General Purpose AcpiEvent 1 Reg Blk */
UINT8 Pm1EvtLen; /* Byte Length of ports at pm1X_evt_blk */
UINT8 Pm1CntLen; /* Byte Length of ports at pm1X_cnt_blk */
UINT8 Pm2CntLen; /* Byte Length of ports at pm2_cnt_blk */
UINT8 PmTmLen; /* Byte Length of ports at pm_tm_blk */
UINT8 Gpe0BlkLen; /* Byte Length of ports at gpe0_blk */
UINT8 Gpe1BlkLen; /* Byte Length of ports at gpe1_blk */
UINT8 Gpe1Base; /* Offset in gpe model where gpe1 events start */
UINT8 CstCnt; /* Support for the _CST object and C States change notification.*/
UINT16 Plvl2Lat; /* Worst case HW latency to enter/exit C2 state */
UINT16 Plvl3Lat; /* Worst case HW latency to enter/exit C3 state */
UINT16 FlushSize; /* Number of flush strides that need to be read */
UINT16 FlushStride; /* Processor's memory cache line width, in bytes */
UINT8 DutyOffset; /* Processor's duty cycle index in processor's P_CNT reg*/
UINT8 DutyWidth; /* Processor's duty cycle value bit width in P_CNT register.*/
UINT8 DayAlrm; /* Index to day-of-month alarm in RTC CMOS RAM */
UINT8 MonAlrm; /* Index to month-of-year alarm in RTC CMOS RAM */
UINT8 Century; /* Index to century in RTC CMOS RAM */
UINT16 IapcBootArch; /* IA-PC Boot Architecture Flags. See Table 5-10 for description*/
FADT_REV2_COMMON
UINT8 Reserved2; /* Reserved */
UINT32_BIT WbInvd : 1; /* The wbinvd instruction works properly */
UINT32_BIT WbInvdFlush : 1; /* The wbinvd flushes but does not invalidate */
@ -245,17 +249,25 @@ typedef struct fadt_descriptor_rev2
UINT32_BIT SleepButton : 1; /* Sleep button is handled as a generic feature, or not present */
UINT32_BIT FixedRTC : 1; /* RTC wakeup stat not in fixed register space */
UINT32_BIT Rtcs4 : 1; /* RTC wakeup stat not possible from S4 */
UINT32_BIT TmrValExt : 1; /* Indicates tmr_val is 32 bits 0=24-bits*/
UINT32_BIT TmrValExt : 1; /* Indicates tmr_val is 32 bits 0=24-bits */
UINT32_BIT DockCap : 1; /* Supports Docking */
UINT32_BIT ResetRegSup : 1; /* Indicates system supports system reset via the FADT RESET_REG*/
UINT32_BIT SealedCase : 1; /* Indicates system has no internal expansion capabilities and case is sealed. */
UINT32_BIT Headless : 1; /* Indicates system does not have local video capabilities or local input devices.*/
UINT32_BIT ResetRegSup : 1; /* Indicates system supports system reset via the FADT RESET_REG */
UINT32_BIT SealedCase : 1; /* Indicates system has no internal expansion capabilities and case is sealed */
UINT32_BIT Headless : 1; /* Indicates system does not have local video capabilities or local input devices */
UINT32_BIT CpuSwSleep : 1; /* Indicates to OSPM that a processor native instruction */
/* Must be executed after writing the SLP_TYPx register. */
UINT32_BIT Reserved6 : 18; /* Reserved - must be zero */
/* must be executed after writing the SLP_TYPx register */
/* ACPI 3.0 flag bits */
UINT32_BIT PciExpWak : 1; /* System supports PCIEXP_WAKE (STS/EN) bits */
UINT32_BIT UsePlatformClock : 1; /* OSPM should use platform-provided timer */
UINT32_BIT S4RtcStsValid : 1; /* Contents of RTC_STS valid after S4 wake */
UINT32_BIT RemotePowerOnCapable : 1; /* System is compatible with remote power on */
UINT32_BIT ForceApicClusterModel : 1; /* All local APICs must use cluster model */
UINT32_BIT ForceApicPhysicalDestinationMode : 1; /* All local xAPICs must use physical dest mode */
UINT32_BIT Reserved6 : 12;/* Reserved - must be zero */
ACPI_GENERIC_ADDRESS ResetRegister; /* Reset register address in GAS format */
UINT8 ResetValue; /* Value to write to the ResetRegister port to reset the system. */
UINT8 ResetValue; /* Value to write to the ResetRegister port to reset the system */
UINT8 Reserved7[3]; /* These three bytes must be zero */
UINT64 XFirmwareCtrl; /* 64-bit physical address of FACS */
UINT64 XDsdt; /* 64-bit physical address of DSDT */
@ -271,6 +283,21 @@ typedef struct fadt_descriptor_rev2
} FADT_DESCRIPTOR_REV2;
/* "Downrevved" ACPI 2.0 FADT descriptor */
typedef struct fadt_descriptor_rev2_minus
{
ACPI_TABLE_HEADER_DEF /* ACPI common table header */
FADT_REV2_COMMON
UINT8 Reserved2; /* Reserved */
UINT32 Flags;
ACPI_GENERIC_ADDRESS ResetRegister; /* Reset register address in GAS format */
UINT8 ResetValue; /* Value to write to the ResetRegister port to reset the system. */
UINT8 Reserved7[3]; /* These three bytes must be zero */
} FADT_DESCRIPTOR_REV2_MINUS;
/* Embedded Controller */
typedef struct ec_boot_resources