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date	2000.06.13.21.22.00;	author rmoore1;	state Exp;
This commit is contained in:
aystarik 2005-06-29 16:51:05 +00:00
parent 65cc320ac9
commit 43dc1784ae
3 changed files with 322 additions and 319 deletions
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103
source/components/hardware/hwacpi.c
View File

@ -1,6 +1,6 @@
/******************************************************************************
*
*
* Module Name: hwmode - Functions for ACPI<->Legacy mode switching logic
*
*****************************************************************************/
@ -38,9 +38,9 @@
* The above copyright and patent license is granted only if the following
* conditions are met:
*
* 3. Conditions
* 3. Conditions
*
* 3.1. Redistribution of Source with Rights to Further Distribute Source.
* 3.1. Redistribution of Source with Rights to Further Distribute Source.
* Redistribution of source code of any substantial portion of the Covered
* Code or modification with rights to further distribute source must include
* the above Copyright Notice, the above License, this list of Conditions,
@ -48,11 +48,11 @@
* Licensee must cause all Covered Code to which Licensee contributes to
* contain a file documenting the changes Licensee made to create that Covered
* Code and the date of any change. Licensee must include in that file the
* documentation of any changes made by any predecessor Licensee. Licensee
* documentation of any changes made by any predecessor Licensee. Licensee
* must include a prominent statement that the modification is derived,
* directly or indirectly, from Original Intel Code.
*
* 3.2. Redistribution of Source with no Rights to Further Distribute Source.
* 3.2. Redistribution of Source with no Rights to Further Distribute Source.
* Redistribution of source code of any substantial portion of the Covered
* Code or modification without rights to further distribute source must
* include the following Disclaimer and Export Compliance provision in the
@ -86,7 +86,7 @@
* INSTALLATION, TRAINING OR OTHER SERVICES. INTEL WILL NOT PROVIDE ANY
* UPDATES, ENHANCEMENTS OR EXTENSIONS. INTEL SPECIFICALLY DISCLAIMS ANY
* IMPLIED WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT AND FITNESS FOR A
* PARTICULAR PURPOSE.
* PARTICULAR PURPOSE.
*
* 4.2. IN NO EVENT SHALL INTEL HAVE ANY LIABILITY TO LICENSEE, ITS LICENSEES
* OR ANY OTHER THIRD PARTY, FOR ANY LOST PROFITS, LOST DATA, LOSS OF USE OR
@ -116,8 +116,8 @@
#define __HWMODE_C__
#include <acpi.h>
#include <hardware.h>
#include "acpi.h"
#include "hardware.h"
#define _COMPONENT HARDWARE
@ -126,7 +126,7 @@
/******************************************************************************
*
* FUNCTION: HwSetMode
* FUNCTION: AcpiHwSetMode
*
* PARAMETERS: Mode - SYS_MODE_ACPI or SYS_MODE_LEGACY
*
@ -138,7 +138,7 @@
******************************************************************************/
ACPI_STATUS
HwSetMode (
AcpiHwSetMode (
UINT32 Mode)
{
@ -146,40 +146,40 @@ HwSetMode (
FUNCTION_TRACE ("HwSetMode");
if (Mode == SYS_MODE_ACPI)
{
/* BIOS should have disabled ALL fixed and GP events */
OsdOut8 (Gbl_FACP->SmiCmd, Gbl_FACP->AcpiEnable);
AcpiOsdOut8 (Acpi_GblFACP->SmiCmd, Acpi_GblFACP->AcpiEnable);
DEBUG_PRINT (ACPI_INFO, ("Attempting to enable ACPI mode\n"));
}
else if (Mode == SYS_MODE_LEGACY)
{
/*
/*
* BIOS should clear all fixed status bits and restore fixed event
* enable bits to default
*/
OsdOut8 (Gbl_FACP->SmiCmd, Gbl_FACP->AcpiDisable);
AcpiOsdOut8 (Acpi_GblFACP->SmiCmd, Acpi_GblFACP->AcpiDisable);
DEBUG_PRINT (ACPI_INFO, ("Attempting to enable Legacy (non-ACPI) mode\n"));
}
if (HwGetMode () == Mode)
if (AcpiHwGetMode () == Mode)
{
DEBUG_PRINT (ACPI_INFO, ("Mode %d successfully enabled\n", Mode));
Status = AE_OK;
}
return_ACPI_STATUS (Status);
}
/******************************************************************************
*
* FUNCTION: Hw
* FUNCTION: AcpiHw
*
* PARAMETERS: none
*
@ -191,13 +191,13 @@ HwSetMode (
******************************************************************************/
UINT32
HwGetMode (void)
AcpiHwGetMode (void)
{
FUNCTION_TRACE ("HwGetMode");
if (HwRegisterIO (ACPI_READ, MTX_LOCK, (INT32)SCI_EN))
if (AcpiHwRegisterIO (ACPI_READ, MTX_LOCK, (INT32)SCI_EN))
{
return_VALUE (SYS_MODE_ACPI);
}
@ -209,7 +209,7 @@ HwGetMode (void)
/******************************************************************************
*
* FUNCTION: HwGetModeCapabilities
* FUNCTION: AcpiHwGetModeCapabilities
*
* PARAMETERS: none
*
@ -221,52 +221,51 @@ HwGetMode (void)
******************************************************************************/
UINT32
HwGetModeCapabilities (void)
AcpiHwGetModeCapabilities (void)
{
FUNCTION_TRACE ("HwGetModeCapabilities");
if (!(Gbl_SystemFlags & SYS_MODES_MASK))
if (!(Acpi_GblSystemFlags & SYS_MODES_MASK))
{
if (HwGetMode () == SYS_MODE_LEGACY)
{
/*
if (AcpiHwGetMode () == SYS_MODE_LEGACY)
{
/*
* Assume that if this call is being made, AcpiInit has been called and
* ACPI support has been established by the presence of the tables.
* Therefore since we're in SYS_MODE_LEGACY, the system must support both
* modes
* modes
*/
Gbl_SystemFlags |= (SYS_MODE_ACPI | SYS_MODE_LEGACY);
}
else
{
/* TBD!!! this may be unsafe... */
/*
Acpi_GblSystemFlags |= (SYS_MODE_ACPI | SYS_MODE_LEGACY);
}
else
{
/* TBD: [Investigate] !!! this may be unsafe... */
/*
* system is is ACPI mode, so try to switch back to LEGACY to see if
* it is supported
* it is supported
*/
HwSetMode (SYS_MODE_LEGACY);
if (HwGetMode () == SYS_MODE_LEGACY)
{
AcpiHwSetMode (SYS_MODE_LEGACY);
if (AcpiHwGetMode () == SYS_MODE_LEGACY)
{
/* Now in SYS_MODE_LEGACY, so both are supported */
Gbl_SystemFlags |= (SYS_MODE_ACPI | SYS_MODE_LEGACY);
HwSetMode (SYS_MODE_ACPI);
Acpi_GblSystemFlags |= (SYS_MODE_ACPI | SYS_MODE_LEGACY);
AcpiHwSetMode (SYS_MODE_ACPI);
}
else
{
{
/* Still in SYS_MODE_ACPI so this must be an ACPI only system */
Gbl_SystemFlags |= SYS_MODE_ACPI;
Acpi_GblSystemFlags |= SYS_MODE_ACPI;
}
}
}
return_VALUE (Gbl_SystemFlags & SYS_MODES_MASK);
return_VALUE (Acpi_GblSystemFlags & SYS_MODES_MASK);
}

90
source/components/hardware/hwgpe.c
View File

@ -1,5 +1,5 @@
/******************************************************************************
*
*
* Module Name: hwgpe - Low level GPE enable/disable/clear functions
*
*****************************************************************************/
@ -37,9 +37,9 @@
* The above copyright and patent license is granted only if the following
* conditions are met:
*
* 3. Conditions
* 3. Conditions
*
* 3.1. Redistribution of Source with Rights to Further Distribute Source.
* 3.1. Redistribution of Source with Rights to Further Distribute Source.
* Redistribution of source code of any substantial portion of the Covered
* Code or modification with rights to further distribute source must include
* the above Copyright Notice, the above License, this list of Conditions,
@ -47,11 +47,11 @@
* Licensee must cause all Covered Code to which Licensee contributes to
* contain a file documenting the changes Licensee made to create that Covered
* Code and the date of any change. Licensee must include in that file the
* documentation of any changes made by any predecessor Licensee. Licensee
* documentation of any changes made by any predecessor Licensee. Licensee
* must include a prominent statement that the modification is derived,
* directly or indirectly, from Original Intel Code.
*
* 3.2. Redistribution of Source with no Rights to Further Distribute Source.
* 3.2. Redistribution of Source with no Rights to Further Distribute Source.
* Redistribution of source code of any substantial portion of the Covered
* Code or modification without rights to further distribute source must
* include the following Disclaimer and Export Compliance provision in the
@ -85,7 +85,7 @@
* INSTALLATION, TRAINING OR OTHER SERVICES. INTEL WILL NOT PROVIDE ANY
* UPDATES, ENHANCEMENTS OR EXTENSIONS. INTEL SPECIFICALLY DISCLAIMS ANY
* IMPLIED WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT AND FITNESS FOR A
* PARTICULAR PURPOSE.
* PARTICULAR PURPOSE.
*
* 4.2. IN NO EVENT SHALL INTEL HAVE ANY LIABILITY TO LICENSEE, ITS LICENSEES
* OR ANY OTHER THIRD PARTY, FOR ANY LOST PROFITS, LOST DATA, LOSS OF USE OR
@ -113,10 +113,10 @@
*
*****************************************************************************/
#include <acpi.h>
#include <hardware.h>
#include <namesp.h>
#include <events.h>
#include "acpi.h"
#include "hardware.h"
#include "namesp.h"
#include "events.h"
#define _COMPONENT HARDWARE
MODULE_NAME ("hwgpe");
@ -127,7 +127,7 @@ UINT8 DecodeTo8bit [8] = {1,2,4,8,16,32,64,128};
/******************************************************************************
*
* FUNCTION: HwEnableGpe
* FUNCTION: AcpiHwEnableGpe
*
* PARAMETERS: GpeNumber - The GPE
*
@ -138,35 +138,35 @@ UINT8 DecodeTo8bit [8] = {1,2,4,8,16,32,64,128};
******************************************************************************/
void
HwEnableGpe (
AcpiHwEnableGpe (
UINT32 GpeNumber)
{
UINT8 InByte;
UINT32 RegisterIndex;
UINT8 BitMask;
/*
/*
* Translate GPE number to index into global registers array.
*/
RegisterIndex = Gbl_GpeValid[GpeNumber];
RegisterIndex = Acpi_GblGpeValid[GpeNumber];
/*
/*
* Figure out the bit offset for this GPE within the target register.
*/
BitMask = DecodeTo8bit [MOD_8 (GpeNumber)];
/*
/*
* Read the current value of the register, set the appropriate bit
* to enable the GPE, and write out the new register.
*/
InByte = OsdIn8 (Gbl_GpeRegisters[RegisterIndex].EnableAddr);
OsdOut8 (Gbl_GpeRegisters[RegisterIndex].EnableAddr, (UINT8)(InByte | BitMask));
InByte = AcpiOsdIn8 (Acpi_GblGpeRegisters[RegisterIndex].EnableAddr);
AcpiOsdOut8 (Acpi_GblGpeRegisters[RegisterIndex].EnableAddr, (UINT8)(InByte | BitMask));
}
/******************************************************************************
*
* FUNCTION: HwDisableGpe
* FUNCTION: AcpiHwDisableGpe
*
* PARAMETERS: GpeNumber - The GPE
*
@ -177,72 +177,72 @@ HwEnableGpe (
******************************************************************************/
void
HwDisableGpe (
AcpiHwDisableGpe (
UINT32 GpeNumber)
{
UINT8 InByte;
UINT32 RegisterIndex;
UINT8 BitMask;
/*
/*
* Translate GPE number to index into global registers array.
*/
RegisterIndex = Gbl_GpeValid[GpeNumber];
RegisterIndex = Acpi_GblGpeValid[GpeNumber];
/*
/*
* Figure out the bit offset for this GPE within the target register.
*/
BitMask = DecodeTo8bit [MOD_8 (GpeNumber)];
/*
/*
* Read the current value of the register, clear the appropriate bit,
* and write out the new register value to disable the GPE.
*/
InByte = OsdIn8 (Gbl_GpeRegisters[RegisterIndex].EnableAddr);
OsdOut8 (Gbl_GpeRegisters[RegisterIndex].EnableAddr, (UINT8)(InByte & ~BitMask));
InByte = AcpiOsdIn8 (Acpi_GblGpeRegisters[RegisterIndex].EnableAddr);
AcpiOsdOut8 (Acpi_GblGpeRegisters[RegisterIndex].EnableAddr, (UINT8)(InByte & ~BitMask));
}
/******************************************************************************
*
* FUNCTION: HwClearGpe
* FUNCTION: AcpiHwClearGpe
*
* PARAMETERS: GpeNumber - The GPE
*
* RETURN: None
*
* DESCRIPTION: Clear a single GPE.
* DESCRIPTION: Clear a single GPE.
*
******************************************************************************/
void
HwClearGpe (
AcpiHwClearGpe (
UINT32 GpeNumber)
{
UINT32 RegisterIndex;
UINT8 BitMask;
/*
/*
* Translate GPE number to index into global registers array.
*/
RegisterIndex = Gbl_GpeValid[GpeNumber];
RegisterIndex = Acpi_GblGpeValid[GpeNumber];
/*
/*
* Figure out the bit offset for this GPE within the target register.
*/
BitMask = DecodeTo8bit [MOD_8 (GpeNumber)];
/*
* Write a one to the appropriate bit in the status register to
/*
* Write a one to the appropriate bit in the status register to
* clear this GPE.
*/
OsdOut8 (Gbl_GpeRegisters[RegisterIndex].StatusAddr, BitMask);
AcpiOsdOut8 (Acpi_GblGpeRegisters[RegisterIndex].StatusAddr, BitMask);
}
/******************************************************************************
*
* FUNCTION: HwGetGpeStatus
* FUNCTION: AcpiHwGetGpeStatus
*
* PARAMETERS: GpeNumber - The GPE
*
@ -253,7 +253,7 @@ HwClearGpe (
******************************************************************************/
void
HwGetGpeStatus (
AcpiHwGetGpeStatus (
UINT32 GpeNumber,
ACPI_EVENT_STATUS *EventStatus)
{
@ -263,35 +263,35 @@ HwGetGpeStatus (
if (!EventStatus)
{
return;
return;
}
(*EventStatus) = 0;
/*
/*
* Translate GPE number to index into global registers array.
*/
RegisterIndex = Gbl_GpeValid[GpeNumber];
RegisterIndex = Acpi_GblGpeValid[GpeNumber];
/*
/*
* Figure out the bit offset for this GPE within the target register.
*/
BitMask = DecodeTo8bit [MOD_8 (GpeNumber)];
/*
/*
* Enabled?:
*/
InByte = OsdIn8 (Gbl_GpeRegisters[RegisterIndex].EnableAddr);
InByte = AcpiOsdIn8 (Acpi_GblGpeRegisters[RegisterIndex].EnableAddr);
if (BitMask & InByte)
{
(*EventStatus) |= EVENT_FLAG_ENABLED;
}
/*
/*
* Set?
*/
InByte = OsdIn8 (Gbl_GpeRegisters[RegisterIndex].StatusAddr);
InByte = AcpiOsdIn8 (Acpi_GblGpeRegisters[RegisterIndex].StatusAddr);
if (BitMask & InByte)
{

448
source/components/hardware/hwregs.c
View File

@ -1,6 +1,6 @@
/******************************************************************************
*
*
* Module Name: hwregs - Read/write access functions for the various ACPI
* control and status registers.
*
@ -39,9 +39,9 @@
* The above copyright and patent license is granted only if the following
* conditions are met:
*
* 3. Conditions
* 3. Conditions
*
* 3.1. Redistribution of Source with Rights to Further Distribute Source.
* 3.1. Redistribution of Source with Rights to Further Distribute Source.
* Redistribution of source code of any substantial portion of the Covered
* Code or modification with rights to further distribute source must include
* the above Copyright Notice, the above License, this list of Conditions,
@ -49,11 +49,11 @@
* Licensee must cause all Covered Code to which Licensee contributes to
* contain a file documenting the changes Licensee made to create that Covered
* Code and the date of any change. Licensee must include in that file the
* documentation of any changes made by any predecessor Licensee. Licensee
* documentation of any changes made by any predecessor Licensee. Licensee
* must include a prominent statement that the modification is derived,
* directly or indirectly, from Original Intel Code.
*
* 3.2. Redistribution of Source with no Rights to Further Distribute Source.
* 3.2. Redistribution of Source with no Rights to Further Distribute Source.
* Redistribution of source code of any substantial portion of the Covered
* Code or modification without rights to further distribute source must
* include the following Disclaimer and Export Compliance provision in the
@ -87,7 +87,7 @@
* INSTALLATION, TRAINING OR OTHER SERVICES. INTEL WILL NOT PROVIDE ANY
* UPDATES, ENHANCEMENTS OR EXTENSIONS. INTEL SPECIFICALLY DISCLAIMS ANY
* IMPLIED WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT AND FITNESS FOR A
* PARTICULAR PURPOSE.
* PARTICULAR PURPOSE.
*
* 4.2. IN NO EVENT SHALL INTEL HAVE ANY LIABILITY TO LICENSEE, ITS LICENSEES
* OR ANY OTHER THIRD PARTY, FOR ANY LOST PROFITS, LOST DATA, LOSS OF USE OR
@ -117,9 +117,9 @@
#define __HWREGS_C__
#include <acpi.h>
#include <hardware.h>
#include <namesp.h>
#include "acpi.h"
#include "hardware.h"
#include "namesp.h"
#define _COMPONENT HARDWARE
MODULE_NAME ("hwregs");
@ -135,7 +135,7 @@ ACPI_STRING SleepStateTable[] = {"\\_S0_","\\_S1_","\\_S2_","\\_S3_",
/******************************************************************************
*
* FUNCTION: HwGetBitShift
* FUNCTION: AcpiHwGetBitShift
*
* PARAMETERS: Mask - Input mask to determine bit shift from. Must
* have at least 1 bit set.
@ -147,7 +147,7 @@ ACPI_STRING SleepStateTable[] = {"\\_S0_","\\_S1_","\\_S2_","\\_S3_",
******************************************************************************/
INT32
HwGetBitShift (
AcpiHwGetBitShift (
UINT32 Mask)
{
INT32 Shift;
@ -165,7 +165,7 @@ HwGetBitShift (
/******************************************************************************
*
* FUNCTION: HwClearAcpiStatus
* FUNCTION: AcpiHwClearAcpiStatus
*
* PARAMETERS: none
*
@ -175,8 +175,8 @@ HwGetBitShift (
*
******************************************************************************/
void
HwClearAcpiStatus (void)
void
AcpiHwClearAcpiStatus (void)
{
UINT16 GpeLength;
UINT16 Index;
@ -185,49 +185,49 @@ HwClearAcpiStatus (void)
FUNCTION_TRACE ("HwClearAcpiStatus");
DEBUG_PRINT (TRACE_IO, ("About to write %04X to %04X\n",
ALL_FIXED_STS_BITS, (UINT16) Gbl_FACP->Pm1aEvtBlk));
DEBUG_PRINT (TRACE_IO, ("About to write %04X to %04X\n",
ALL_FIXED_STS_BITS, (UINT16) Acpi_GblFACP->Pm1aEvtBlk));
CmAcquireMutex (MTX_HARDWARE);
AcpiCmAcquireMutex (MTX_HARDWARE);
OsdOut16 (Gbl_FACP->Pm1aEvtBlk, (UINT16) ALL_FIXED_STS_BITS);
if (Gbl_FACP->Pm1bEvtBlk)
AcpiOsdOut16 (Acpi_GblFACP->Pm1aEvtBlk, (UINT16) ALL_FIXED_STS_BITS);
if (Acpi_GblFACP->Pm1bEvtBlk)
{
OsdOut16 ((UINT16) Gbl_FACP->Pm1bEvtBlk, (UINT16) ALL_FIXED_STS_BITS);
AcpiOsdOut16 ((UINT16) Acpi_GblFACP->Pm1bEvtBlk, (UINT16) ALL_FIXED_STS_BITS);
}
/* now clear the GPE Bits */
if (Gbl_FACP->Gpe0BlkLen)
if (Acpi_GblFACP->Gpe0BlkLen)
{
GpeLength = (UINT16) (Gbl_FACP->Gpe0BlkLen / 2);
GpeLength = (UINT16) DIV_2 (Acpi_GblFACP->Gpe0BlkLen);
for (Index = 0; Index < GpeLength; Index++)
{
OsdOut8 ((Gbl_FACP->Gpe0Blk + Index), (UINT8) 0xff);
AcpiOsdOut8 ((Acpi_GblFACP->Gpe0Blk + Index), (UINT8) 0xff);
}
}
if (Gbl_FACP->Gpe1BlkLen)
if (Acpi_GblFACP->Gpe1BlkLen)
{
GpeLength = (UINT16) (Gbl_FACP->Gpe1BlkLen / 2);
GpeLength = (UINT16) DIV_2 (Acpi_GblFACP->Gpe1BlkLen);
for (Index = 0; Index < GpeLength; Index++)
{
OsdOut8 ((Gbl_FACP->Gpe1Blk + Index), (UINT8) 0xff);
AcpiOsdOut8 ((Acpi_GblFACP->Gpe1Blk + Index), (UINT8) 0xff);
}
}
CmReleaseMutex (MTX_HARDWARE);
AcpiCmReleaseMutex (MTX_HARDWARE);
return_VOID;
}
/****************************************************************************
*
* FUNCTION: HwObtainSleepTypeRegisterData
* FUNCTION: AcpiHwObtainSleepTypeRegisterData
*
* PARAMETERS: SleepState - Numeric state requested
* *Slp_TypA - Pointer to byte to receive SLP_TYPa value
@ -235,22 +235,22 @@ HwClearAcpiStatus (void)
*
* RETURN: Status - ACPI status
*
* DESCRIPTION: HwObtainSleepTypeRegisterData() obtains the SLP_TYP and
* DESCRIPTION: AcpiHwObtainSleepTypeRegisterData() obtains the SLP_TYP and
* SLP_TYPb values for the sleep state requested.
*
***************************************************************************/
ACPI_STATUS
HwObtainSleepTypeRegisterData (
UINT8 SleepState,
AcpiHwObtainSleepTypeRegisterData (
UINT8 SleepState,
UINT8 *Slp_TypA,
UINT8 *Slp_TypB)
{
ACPI_STATUS Status = AE_OK;
ACPI_OBJECT_INTERNAL *ObjDesc;
FUNCTION_TRACE ("HwObtainSleepTypeRegisterData");
@ -260,17 +260,17 @@ HwObtainSleepTypeRegisterData (
if ((SleepState > ACPI_S_STATES_MAX) ||
!Slp_TypA || !Slp_TypB)
{
{
return_ACPI_STATUS (AE_BAD_PARAMETER);
}
/*
* Evaluate the namespace object containing the values for this state
* AcpiEvaluate the namespace object containing the values for this state
*/
Status = NsEvaluateByName (SleepStateTable[SleepState], NULL, &ObjDesc);
Status = AcpiNsEvaluateByName (SleepStateTable[SleepState], NULL, &ObjDesc);
if (AE_OK == Status)
{
{
if (ObjDesc)
{
/*
@ -279,17 +279,17 @@ HwObtainSleepTypeRegisterData (
* two elements
*/
if ((ObjDesc->Common.Type != ACPI_TYPE_Package) ||
((ObjDesc->Package.Elements[0])->Common.Type != ACPI_TYPE_Number) ||
((ObjDesc->Package.Elements[1])->Common.Type != ACPI_TYPE_Number))
{
if ((ObjDesc->Common.Type != ACPI_TYPE_PACKAGE) ||
((ObjDesc->Package.Elements[0])->Common.Type != ACPI_TYPE_NUMBER) ||
((ObjDesc->Package.Elements[1])->Common.Type != ACPI_TYPE_NUMBER))
{
/* Invalid _Sx_ package type or value */
REPORT_ERROR ("Object type returned from interpreter differs from expected value");
Status = AE_ERROR;
}
else
{
{
/*
* Valid _Sx_ package size, type, and value
*/
@ -297,7 +297,7 @@ HwObtainSleepTypeRegisterData (
*Slp_TypB = (UINT8) (ObjDesc->Package.Elements[1])->Number.Value;
}
CmRemoveReference (ObjDesc);
AcpiCmRemoveReference (ObjDesc);
}
}
@ -307,9 +307,10 @@ HwObtainSleepTypeRegisterData (
/******************************************************************************
*
* FUNCTION: HwRegisterIO
* FUNCTION: AcpiHwRegisterIO
*
* PARAMETERS: ReadWrite - Either ACPI_READ or ACPI_WRITE.
* UseLock - Lock the hardware
* RegisterId - index of ACPI register to access
* Value - (only used on write) value to write to the
* register. Shifted all the way right.
@ -322,21 +323,21 @@ HwObtainSleepTypeRegisterData (
******************************************************************************/
UINT32
HwRegisterIO (
INT32 ReadWrite,
UINT32 UseLock,
INT32 RegisterId,
...)
AcpiHwRegisterIO (
NATIVE_UINT ReadWrite,
BOOLEAN UseLock,
UINT32 RegisterId,
...) /* Value (only used on write) */
{
UINT32 RegisterValue = 0;
UINT32 Mask = 0;
UINT32 Value = 0;
UINT32 GpeReg = 0;
ACPI_IO_ADDRESS GpeReg = 0;
FUNCTION_TRACE ("HwRegisterIO");
if (ReadWrite == ACPI_WRITE)
{
va_list marker;
@ -346,7 +347,8 @@ HwRegisterIO (
va_end (marker);
}
/* TBD: [Restructure] May want to split the AcpiEvent code and the Control code */
/*
* Decode the Register ID
*/
@ -355,24 +357,25 @@ HwRegisterIO (
{
case PM1_EVT:
if (RegisterId < (INT32) TMR_EN)
{
if(MTX_LOCK == UseLock)
{
CmAcquireMutex (MTX_HARDWARE);
}
if (RegisterId < TMR_EN)
{
/* status register */
RegisterValue = (UINT32) OsdIn16 (Gbl_FACP->Pm1aEvtBlk);
DEBUG_PRINT (TRACE_IO, ("PM1a status: Read 0x%X from 0x%X\n",
RegisterValue, Gbl_FACP->Pm1aEvtBlk));
if (Gbl_FACP->Pm1bEvtBlk)
if (MTX_LOCK == UseLock)
{
RegisterValue |= (UINT32) OsdIn16 (Gbl_FACP->Pm1bEvtBlk);
DEBUG_PRINT (TRACE_IO, ("PM1b status: Read 0x%X from 0x%X\n",
RegisterValue, Gbl_FACP->Pm1bEvtBlk));
AcpiCmAcquireMutex (MTX_HARDWARE);
}
RegisterValue = (UINT32) AcpiOsdIn16 (Acpi_GblFACP->Pm1aEvtBlk);
DEBUG_PRINT (TRACE_IO, ("PM1a status: Read 0x%X from 0x%X\n",
RegisterValue, Acpi_GblFACP->Pm1aEvtBlk));
if (Acpi_GblFACP->Pm1bEvtBlk)
{
RegisterValue |= (UINT32) AcpiOsdIn16 (Acpi_GblFACP->Pm1bEvtBlk);
DEBUG_PRINT (TRACE_IO, ("PM1b status: Read 0x%X from 0x%X\n",
RegisterValue, Acpi_GblFACP->Pm1bEvtBlk));
}
switch (RegisterId)
@ -380,89 +383,89 @@ HwRegisterIO (
case TMR_STS:
Mask = TMR_STS_MASK;
break;
case BM_STS:
Mask = BM_STS_MASK;
break;
case GBL_STS:
Mask = GBL_STS_MASK;
break;
case PWRBTN_STS:
Mask = PWRBTN_STS_MASK;
break;
case SLPBTN_STS:
Mask = SLPBTN_STS_MASK;
break;
case RTC_STS:
Mask = RTC_STS_MASK;
break;
case WAK_STS:
Mask = WAK_STS_MASK;
break;
default:
Mask = 0;
break;
}
if (ReadWrite == ACPI_WRITE)
{
/*
/*
* Status registers are different from the rest. Clear by writing 1, writing 0
* has no effect. So, the only relevent information is the single bit we're
* interested in, all others should be written as 0 so they will be left
* unchanged
* unchanged
*/
Value <<= HwGetBitShift (Mask);
Value <<= AcpiHwGetBitShift (Mask);
Value &= Mask;
if (Value)
{
DEBUG_PRINT (TRACE_IO, ("About to write %04X to %04X\n", Value, Gbl_FACP->Pm1aEvtBlk));
DEBUG_PRINT (TRACE_IO, ("About to write %04X to %04X\n", Value, Acpi_GblFACP->Pm1aEvtBlk));
OsdOut16 (Gbl_FACP->Pm1aEvtBlk, (UINT16) Value);
if (Gbl_FACP->Pm1bEvtBlk)
AcpiOsdOut16 (Acpi_GblFACP->Pm1aEvtBlk, (UINT16) Value);
if (Acpi_GblFACP->Pm1bEvtBlk)
{
OsdOut16 (Gbl_FACP->Pm1bEvtBlk, (UINT16) Value);
AcpiOsdOut16 (Acpi_GblFACP->Pm1bEvtBlk, (UINT16) Value);
}
RegisterValue = 0;
}
}
if(MTX_LOCK == UseLock)
{
CmReleaseMutex (MTX_HARDWARE);
}
}
else
{
/* enable register */
if(MTX_LOCK == UseLock)
{
CmAcquireMutex (MTX_HARDWARE);
}
RegisterValue = (UINT32) OsdIn16 ((Gbl_FACP->Pm1aEvtBlk + Gbl_FACP->Pm1EvtLen / 2));
DEBUG_PRINT (TRACE_IO, ("PM1a enable: Read 0x%X from 0x%X\n",
RegisterValue, (Gbl_FACP->Pm1aEvtBlk + Gbl_FACP->Pm1EvtLen / 2)));
if (Gbl_FACP->Pm1bEvtBlk)
if (MTX_LOCK == UseLock)
{
RegisterValue |= (UINT32) OsdIn16 ((Gbl_FACP->Pm1bEvtBlk + Gbl_FACP->Pm1EvtLen / 2));
AcpiCmReleaseMutex (MTX_HARDWARE);
}
}
DEBUG_PRINT (TRACE_IO, ("PM1b enable: Read 0x%X from 0x%X\n",
RegisterValue, (Gbl_FACP->Pm1bEvtBlk + Gbl_FACP->Pm1EvtLen / 2)));
else
{
/* enable register */
if (MTX_LOCK == UseLock)
{
AcpiCmAcquireMutex (MTX_HARDWARE);
}
RegisterValue = (UINT32) AcpiOsdIn16 (Acpi_GblFACP->Pm1aEvtBlk + DIV_2 (Acpi_GblFACP->Pm1EvtLen));
DEBUG_PRINT (TRACE_IO, ("PM1a enable: Read 0x%X from 0x%X\n",
RegisterValue, (Acpi_GblFACP->Pm1aEvtBlk + DIV_2 (Acpi_GblFACP->Pm1EvtLen))));
if (Acpi_GblFACP->Pm1bEvtBlk)
{
RegisterValue |= (UINT32) AcpiOsdIn16 (Acpi_GblFACP->Pm1bEvtBlk + DIV_2 (Acpi_GblFACP->Pm1EvtLen));
DEBUG_PRINT (TRACE_IO, ("PM1b enable: Read 0x%X from 0x%X\n",
RegisterValue, (Acpi_GblFACP->Pm1bEvtBlk + DIV_2 (Acpi_GblFACP->Pm1EvtLen))));
}
switch (RegisterId)
@ -470,83 +473,83 @@ HwRegisterIO (
case TMR_EN:
Mask = TMR_EN_MASK;
break;
case GBL_EN:
Mask = GBL_EN_MASK;
break;
case PWRBTN_EN:
Mask = PWRBTN_EN_MASK;
break;
case SLPBTN_EN:
Mask = SLPBTN_EN_MASK;
break;
case RTC_EN:
Mask = RTC_EN_MASK;
break;
default:
Mask = 0;
break;
}
if (ReadWrite == ACPI_WRITE)
{
RegisterValue &= ~Mask;
Value <<= HwGetBitShift (Mask);
Value <<= AcpiHwGetBitShift (Mask);
Value &= Mask;
RegisterValue |= Value;
DEBUG_PRINT (TRACE_IO, ("About to write %04X to %04X\n", RegisterValue,
(Gbl_FACP->Pm1aEvtBlk + Gbl_FACP->Pm1EvtLen / 2)));
DEBUG_PRINT (TRACE_IO, ("About to write %04X to %04X\n", RegisterValue,
(Acpi_GblFACP->Pm1aEvtBlk + DIV_2 (Acpi_GblFACP->Pm1EvtLen))));
OsdOut16 ((Gbl_FACP->Pm1aEvtBlk + Gbl_FACP->Pm1EvtLen / 2),
AcpiOsdOut16 ((Acpi_GblFACP->Pm1aEvtBlk + DIV_2 (Acpi_GblFACP->Pm1EvtLen)),
(UINT16) RegisterValue);
if (Gbl_FACP->Pm1bEvtBlk)
if (Acpi_GblFACP->Pm1bEvtBlk)
{
OsdOut16 ((Gbl_FACP->Pm1bEvtBlk + Gbl_FACP->Pm1EvtLen / 2),
AcpiOsdOut16 ((Acpi_GblFACP->Pm1bEvtBlk + DIV_2 (Acpi_GblFACP->Pm1EvtLen)),
(UINT16) RegisterValue);
}
}
if(MTX_LOCK == UseLock)
{
CmReleaseMutex (MTX_HARDWARE);
}
{
AcpiCmReleaseMutex (MTX_HARDWARE);
}
}
break;
case PM1_CONTROL:
RegisterValue = 0;
if(MTX_LOCK == UseLock)
{
CmAcquireMutex (MTX_HARDWARE);
}
if (RegisterId != (INT32) SLP_TYPb)
if (MTX_LOCK == UseLock)
{
/*
AcpiCmAcquireMutex (MTX_HARDWARE);
}
if (RegisterId != SLP_TYPb)
{
/*
* SLP_TYPx registers are written differently
* than any other control registers with
* respect to A and B registers. The value
* for A may be different than the value for B
* for A may be different than the value for B
*/
RegisterValue = (UINT32) OsdIn16 (Gbl_FACP->Pm1aCntBlk);
DEBUG_PRINT (TRACE_IO, ("PM1a control: Read 0x%X from 0x%X\n",
RegisterValue, Gbl_FACP->Pm1aCntBlk));
RegisterValue = (UINT32) AcpiOsdIn16 (Acpi_GblFACP->Pm1aCntBlk);
DEBUG_PRINT (TRACE_IO, ("PM1a control: Read 0x%X from 0x%X\n",
RegisterValue, Acpi_GblFACP->Pm1aCntBlk));
}
if (Gbl_FACP->Pm1bCntBlk && RegisterId != (INT32) SLP_TYPa)
if (Acpi_GblFACP->Pm1bCntBlk && RegisterId != (INT32) SLP_TYPa)
{
RegisterValue |= (UINT32) OsdIn16 (Gbl_FACP->Pm1bCntBlk);
DEBUG_PRINT (TRACE_IO, ("PM1b control: Read 0x%X from 0x%X\n",
RegisterValue, Gbl_FACP->Pm1bCntBlk));
RegisterValue |= (UINT32) AcpiOsdIn16 (Acpi_GblFACP->Pm1bCntBlk);
DEBUG_PRINT (TRACE_IO, ("PM1b control: Read 0x%X from 0x%X\n",
RegisterValue, Acpi_GblFACP->Pm1bCntBlk));
}
switch (RegisterId)
@ -554,20 +557,20 @@ HwRegisterIO (
case SCI_EN:
Mask = SCI_EN_MASK;
break;
case BM_RLD:
Mask = BM_RLD_MASK;
break;
case GBL_RLS:
Mask = GBL_RLS_MASK;
break;
case SLP_TYPa:
case SLP_TYPb:
Mask = SLP_TYPx_MASK;
break;
case SLP_EN:
Mask = SLP_EN_MASK;
break;
@ -576,115 +579,116 @@ HwRegisterIO (
Mask = 0;
break;
}
if (ReadWrite == ACPI_WRITE)
{
RegisterValue &= ~Mask;
Value <<= HwGetBitShift (Mask);
Value <<= AcpiHwGetBitShift (Mask);
Value &= Mask;
RegisterValue |= Value;
/*
/*
* SLP_TYPx registers are written differently
* than any other control registers with
* respect to A and B registers. The value
* for A may be different than the value for B
*/
if (RegisterId != (INT32) SLP_TYPb)
if (RegisterId != SLP_TYPb)
{
if (Mask == SLP_EN_MASK)
{
disable(); /* disable interrupts */
}
OsdOut16 (Gbl_FACP->Pm1aCntBlk, (UINT16) RegisterValue);
AcpiOsdOut16 (Acpi_GblFACP->Pm1aCntBlk, (UINT16) RegisterValue);
if (Mask == SLP_EN_MASK)
{
/*
/*
* Enable interrupts, the SCI handler is likely going to be invoked as
* soon as interrupts are enabled, since gpe's and most fixed resume
* events also generate SCI's.
* events also generate SCI's.
*/
enable();
}
}
if (Gbl_FACP->Pm1bCntBlk && RegisterId != (INT32) SLP_TYPa)
if (Acpi_GblFACP->Pm1bCntBlk && RegisterId != (INT32) SLP_TYPa)
{
OsdOut16 (Gbl_FACP->Pm1bCntBlk, (UINT16) RegisterValue);
AcpiOsdOut16 (Acpi_GblFACP->Pm1bCntBlk, (UINT16) RegisterValue);
}
}
if(MTX_LOCK == UseLock)
{
CmReleaseMutex (MTX_HARDWARE);
}
if (MTX_LOCK == UseLock)
{
AcpiCmReleaseMutex (MTX_HARDWARE);
}
break;
case PM2_CONTROL:
if(MTX_LOCK == UseLock)
{
CmAcquireMutex (MTX_HARDWARE);
}
RegisterValue = (UINT32) OsdIn16 (Gbl_FACP->Pm2CntBlk);
DEBUG_PRINT (TRACE_IO, ("PM2 control: Read 0x%X from 0x%X\n",
RegisterValue, Gbl_FACP->Pm2CntBlk));
if (MTX_LOCK == UseLock)
{
AcpiCmAcquireMutex (MTX_HARDWARE);
}
RegisterValue = (UINT32) AcpiOsdIn16 (Acpi_GblFACP->Pm2CntBlk);
DEBUG_PRINT (TRACE_IO, ("PM2 control: Read 0x%X from 0x%X\n",
RegisterValue, Acpi_GblFACP->Pm2CntBlk));
switch (RegisterId)
{
case ARB_DIS:
Mask = ARB_DIS_MASK;
break;
default:
Mask = 0;
break;
}
if (ReadWrite == ACPI_WRITE)
{
RegisterValue &= ~Mask;
Value <<= HwGetBitShift (Mask);
Value <<= AcpiHwGetBitShift (Mask);
Value &= Mask;
RegisterValue |= Value;
DEBUG_PRINT (TRACE_IO, ("About to write %04X to %04X\n", RegisterValue, Gbl_FACP->Pm2CntBlk));
DEBUG_PRINT (TRACE_IO, ("About to write %04X to %04X\n", RegisterValue, Acpi_GblFACP->Pm2CntBlk));
OsdOut16 (Gbl_FACP->Pm2CntBlk, (UINT16) RegisterValue);
AcpiOsdOut16 (Acpi_GblFACP->Pm2CntBlk, (UINT16) RegisterValue);
}
if(MTX_LOCK == UseLock)
{
CmReleaseMutex (MTX_HARDWARE);
}
if (MTX_LOCK == UseLock)
{
AcpiCmReleaseMutex (MTX_HARDWARE);
}
break;
case PM_TIMER:
RegisterValue = OsdIn32 (Gbl_FACP->PmTmrBlk);
DEBUG_PRINT (TRACE_IO, ("PM_TIMER: Read 0x%X from 0x%X\n",
RegisterValue, Gbl_FACP->PmTmrBlk));
RegisterValue = AcpiOsdIn32 (Acpi_GblFACP->PmTmrBlk);
DEBUG_PRINT (TRACE_IO, ("PM_TIMER: Read 0x%X from 0x%X\n",
RegisterValue, Acpi_GblFACP->PmTmrBlk));
Mask = 0xFFFFFFFF;
break;
case GPE1_EN_BLOCK:
GpeReg = (Gbl_FACP->Gpe1Blk + (UINT32) Gbl_FACP->Gpe1Base) + (GpeReg +
((UINT32) ((Gbl_FACP->Gpe1BlkLen) / 2)));
GpeReg = (Acpi_GblFACP->Gpe1Blk + Acpi_GblFACP->Gpe1Base) +
(GpeReg + (DIV_2 (Acpi_GblFACP->Gpe1BlkLen)));
case GPE1_STS_BLOCK:
if (!GpeReg)
{
GpeReg = (Gbl_FACP->Gpe1Blk + (UINT32) Gbl_FACP->Gpe1Base);
GpeReg = (Acpi_GblFACP->Gpe1Blk + Acpi_GblFACP->Gpe1Base);
}
@ -692,71 +696,71 @@ HwRegisterIO (
if (!GpeReg)
{
GpeReg = Gbl_FACP->Gpe0Blk + ((UINT32) ((Gbl_FACP->Gpe0BlkLen) / 2));
GpeReg = Acpi_GblFACP->Gpe0Blk + DIV_2 (Acpi_GblFACP->Gpe0BlkLen);
}
case GPE0_STS_BLOCK:
if (!GpeReg)
{
GpeReg = Gbl_FACP->Gpe0Blk;
GpeReg = Acpi_GblFACP->Gpe0Blk;
}
/* Determine the bit to be accessed */
Mask = (((UINT32) RegisterId) & BIT_IN_REGISTER_MASK);
Mask = 1 << (Mask-1);
/* The base address of the GPE 0 Register Block */
/* Plus 1/2 the length of the GPE 0 Register Block */
/* The enable register is the register following the Status Register */
/* and each register is defined as 1/2 of the total Register Block */
/* This sets the bit within EnableBit that needs to be written to */
/* the register indicated in Mask to a 1, all others are 0 */
if (Mask > LOW_BYTE)
{
/* Shift the value 1 byte to the right and add 1 to the register */
Mask >>= ONE_BYTE;
GpeReg++;
}
/* Now get the current Enable Bits in the selected Reg */
if(MTX_LOCK == UseLock)
{
CmAcquireMutex (MTX_HARDWARE);
}
RegisterValue = (UINT32) OsdIn8 (GpeReg);
/* Now get the current Enable Bits in the selected Reg */
if(MTX_LOCK == UseLock)
{
AcpiCmAcquireMutex (MTX_HARDWARE);
}
RegisterValue = (UINT32) AcpiOsdIn8 (GpeReg);
DEBUG_PRINT (TRACE_IO, ("GPE Enable bits: Read 0x%X from 0x%X\n", RegisterValue, GpeReg));
if (ReadWrite == ACPI_WRITE)
{
{
RegisterValue &= ~Mask;
Value <<= HwGetBitShift (Mask);
Value <<= AcpiHwGetBitShift (Mask);
Value &= Mask;
RegisterValue |= Value;
/* This write will put the Action state into the General Purpose */
/* Enable Register indexed by the value in Mask */
DEBUG_PRINT (TRACE_IO, ("About to write %04X to %04X\n", RegisterValue, GpeReg));
OsdOut8 (GpeReg, (UINT8) RegisterValue);
RegisterValue = (UINT32) OsdIn8 (GpeReg);
AcpiOsdOut8 (GpeReg, (UINT8) RegisterValue);
RegisterValue = (UINT32) AcpiOsdIn8 (GpeReg);
}
if(MTX_LOCK == UseLock)
{
CmReleaseMutex (MTX_HARDWARE);
}
{
AcpiCmReleaseMutex (MTX_HARDWARE);
}
break;
case PROCESSOR_BLOCK:
default:
@ -767,7 +771,7 @@ HwRegisterIO (
RegisterValue &= Mask;
RegisterValue >>= HwGetBitShift (Mask);
RegisterValue >>= AcpiHwGetBitShift (Mask);
DEBUG_PRINT (TRACE_IO, ("Register I/O: returning 0x%X\n", RegisterValue));
return_VALUE (RegisterValue);