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Rename ACPI_GAS to ACPI_GENERIC_ADDRESS

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date	2001.03.28.16.33.00;	author rmoore1;	state Exp;
This commit is contained in:
aystarik 2005-06-29 20:09:14 +00:00
parent b4d8ae6cca
commit 3706d46989
1 changed files with 125 additions and 128 deletions
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253
source/include/actbl2.h
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@ -1,7 +1,7 @@
/******************************************************************************
*
* Name: actbl2.h - ACPI Specification Revision 2.0 Tables
* $Revision: 1.19 $
* $Revision: 1.22 $
*
*****************************************************************************/
@ -9,8 +9,8 @@
*
* 1. Copyright Notice
*
* Some or all of this work - Copyright (c) 1999, Intel Corp. All rights
* reserved.
* Some or all of this work - Copyright (c) 1999, 2000, 2001, Intel Corp.
* All rights reserved.
*
* 2. License
*
@ -117,159 +117,156 @@
#ifndef __ACTBL2_H__
#define __ACTBL2_H__
/**************************************/
/* Prefered Power Management Profiles */
/**************************************/
#define PM_UNSPECIFIED 0
#define PM_DESKTOP 1
#define PM_MOBILE 2
#define PM_WORKSTATION 3
#define PM_ENTERPRISE_SERVER 4
#define PM_SOHO_SERVER 5
#define PM_APPLIANCE_PC 6
/*
* Prefered Power Management Profiles
*/
#define PM_UNSPECIFIED 0
#define PM_DESKTOP 1
#define PM_MOBILE 2
#define PM_WORKSTATION 3
#define PM_ENTERPRISE_SERVER 4
#define PM_SOHO_SERVER 5
#define PM_APPLIANCE_PC 6
/*********************************************/
/* ACPI Boot Arch Flags, See spec Table 5-10 */
/*********************************************/
#define BAF_LEGACY_DEVICES 0x0001
#define BAF_8042_KEYBOARD_CONTROLLER 0x0002
/*
* ACPI Boot Arch Flags
*/
#define BAF_LEGACY_DEVICES 0x0001
#define BAF_8042_KEYBOARD_CONTROLLER 0x0002
#define FADT2_REVISION_ID 3
#define FADT2_REVISION_ID 3
#pragma pack(1)
/*************************************/
/* ACPI Specification Rev 2.0 for */
/* the Root System Description Table */
/*************************************/
/*
* ACPI Specification Rev 2.0 for the Root System Description Table
*/
typedef struct
{
ACPI_TABLE_HEADER header; /* Table header */
UINT32 TableOffsetEntry [1]; /* Array of pointers to */
/* other tables' headers */
ACPI_TABLE_HEADER header; /* Table header */
UINT32 TableOffsetEntry [1]; /* Array of pointers to */
/* other tables' headers */
} RSDT_DESCRIPTOR_REV2;
/********************************************/
/* ACPI Specification Rev 2.0 for the */
/* Extended System Description Table (XSDT) */
/********************************************/
/*
* ACPI Specification Rev 2.0 for the Extended System Description Table (XSDT)
*/
typedef struct
{
ACPI_TABLE_HEADER Header; /* Table header */
UINT64 TableOffsetEntry [1]; /* Array of pointers to */
/* other tables' headers */
ACPI_TABLE_HEADER Header; /* Table header */
UINT64 TableOffsetEntry [1]; /* Array of pointers to */
/* other tables' headers */
} XSDT_DESCRIPTOR_REV2;
/***************************************/
/* ACPI Specification Rev 2.0 for */
/* the Firmware ACPI Control Structure */
/***************************************/
/*
* ACPI Specification Rev 2.0 for the Firmware ACPI Control Structure
*/
typedef struct
{
NATIVE_CHAR Signature[4]; /* signature "FACS" */
UINT32 Length; /* length of structure, in bytes */
UINT32 HardwareSignature; /* hardware configuration signature */
UINT32 FirmwareWakingVector; /* 32bit physical address of the Firmware Waking Vector. */
UINT32 GlobalLock; /* Global Lock used to synchronize access to shared hardware resources */
UINT32_BIT S4Bios_f : 1; /* Indicates if S4BIOS support is present */
UINT32_BIT Reserved1 : 31; /* must be 0 */
UINT64 XFirmwareWakingVector; /* 64bit physical address of the Firmware Waking Vector. */
UINT8 Version; /* Version of this table */
UINT8 Reserved3 [31]; /* reserved - must be zero */
NATIVE_CHAR Signature[4]; /* signature "FACS" */
UINT32 Length; /* length of structure, in bytes */
UINT32 HardwareSignature; /* hardware configuration signature */
UINT32 FirmwareWakingVector; /* 32bit physical address of the Firmware Waking Vector. */
UINT32 GlobalLock; /* Global Lock used to synchronize access to shared hardware resources */
UINT32_BIT S4Bios_f : 1; /* Indicates if S4BIOS support is present */
UINT32_BIT Reserved1 : 31; /* must be 0 */
UINT64 XFirmwareWakingVector; /* 64bit physical address of the Firmware Waking Vector. */
UINT8 Version; /* Version of this table */
UINT8 Reserved3 [31]; /* reserved - must be zero */
} FACS_DESCRIPTOR_REV2;
/***************************************/
/* ACPI Specification Rev 2.0 for */
/* the Generic Address Structure (GAS) */
/***************************************/
/*
* ACPI Specification Rev 2.0 for the Generic Address Structure (GAS)
*/
typedef struct
{
UINT8 AddressSpaceId; /* Address space where struct or register exists. */
UINT8 RegisterBitWidth; /* Size in bits of given register */
UINT8 RegisterBitOffset; /* Bit offset within the register */
UINT8 Reserved; /* Must be 0 */
UINT64 Address; /* 64-bit address of struct or register */
UINT8 AddressSpaceId; /* Address space where struct or register exists. */
UINT8 RegisterBitWidth; /* Size in bits of given register */
UINT8 RegisterBitOffset; /* Bit offset within the register */
UINT8 Reserved; /* Must be 0 */
UINT64 Address; /* 64-bit address of struct or register */
} ACPI_GAS;
} ACPI_GENERIC_ADDRESS;
/************************************/
/* ACPI Specification Rev 2.0 for */
/* the Fixed ACPI Description Table */
/************************************/
/*
/* ACPI Specification Rev 2.0 for the Fixed ACPI Description Table
*/
typedef struct
{
ACPI_TABLE_HEADER header; /* table header */
UINT32 V1_FirmwareCtrl; /* 32-bit physical address of FACS */
UINT32 V1_Dsdt; /* 32-bit physical address of DSDT */
UINT8 Reserved1; /* System Interrupt Model isn't used in ACPI 2.0*/
UINT8 Prefer_PM_Profile; /* Conveys preferred power management profile to OSPM. */
UINT16 SciInt; /* System vector of SCI interrupt */
UINT32 SmiCmd; /* Port address of SMI command port */
UINT8 AcpiEnable; /* value to write to smi_cmd to enable ACPI */
UINT8 AcpiDisable; /* value to write to smi_cmd to disable ACPI */
UINT8 S4BiosReq; /* Value to write to SMI CMD to enter S4BIOS state */
UINT8 PstateCnt; /* processor performance state control*/
UINT32 V1_Pm1aEvtBlk; /* Port address of Power Mgt 1a AcpiEvent Reg Blk */
UINT32 V1_Pm1bEvtBlk; /* Port address of Power Mgt 1b AcpiEvent Reg Blk */
UINT32 V1_Pm1aCntBlk; /* Port address of Power Mgt 1a Control Reg Blk */
UINT32 V1_Pm1bCntBlk; /* Port address of Power Mgt 1b Control Reg Blk */
UINT32 V1_Pm2CntBlk; /* Port address of Power Mgt 2 Control Reg Blk */
UINT32 V1_PmTmrBlk; /* Port address of Power Mgt Timer Ctrl Reg Blk */
UINT32 V1_Gpe0Blk; /* Port addr of General Purpose AcpiEvent 0 Reg Blk */
UINT32 V1_Gpe1Blk; /* Port addr of General Purpose AcpiEvent 1 Reg Blk */
UINT8 Pm1EvtLen; /* Byte Length of ports at pm1X_evt_blk */
UINT8 Pm1CntLen; /* Byte Length of ports at pm1X_cnt_blk */
UINT8 Pm2CntLen; /* Byte Length of ports at pm2_cnt_blk */
UINT8 PmTmLen; /* Byte Length of ports at pm_tm_blk */
UINT8 Gpe0BlkLen; /* Byte Length of ports at gpe0_blk */
UINT8 Gpe1BlkLen; /* Byte Length of ports at gpe1_blk */
UINT8 Gpe1Base; /* offset in gpe model where gpe1 events start */
UINT8 CstCnt; /* Support for the _CST object and C States change notification.*/
UINT16 Plvl2Lat; /* worst case HW latency to enter/exit C2 state */
UINT16 Plvl3Lat; /* worst case HW latency to enter/exit C3 state */
UINT16 FlushSize; /* number of flush strides that need to be read */
UINT16 FlushStride; /* Processor's memory cache line width, in bytes */
UINT8 DutyOffset; /* Processor’s duty cycle index in processor's P_CNT reg*/
UINT8 DutyWidth; /* Processor’s duty cycle value bit width in P_CNT register.*/
UINT8 DayAlrm; /* index to day-of-month alarm in RTC CMOS RAM */
UINT8 MonAlrm; /* index to month-of-year alarm in RTC CMOS RAM */
UINT8 Century; /* index to century in RTC CMOS RAM */
UINT16 IapcBootArch; /* IA-PC Boot Architecture Flags. See Table 5-10 for description*/
UINT8 Reserved2; /* reserved */
UINT32_BIT WbInvd : 1; /* wbinvd instruction works properly */
UINT32_BIT WbInvdFlush : 1; /* wbinvd flushes but does not invalidate */
UINT32_BIT ProcC1 : 1; /* all processors support C1 state */
UINT32_BIT Plvl2Up : 1; /* C2 state works on MP system */
UINT32_BIT PwrButton : 1; /* Power button is handled as a generic feature */
UINT32_BIT SleepButton : 1; /* Sleep button is handled as a generic feature, or not present */
UINT32_BIT FixedRTC : 1; /* RTC wakeup stat not in fixed register space */
UINT32_BIT Rtcs4 : 1; /* RTC wakeup stat not possible from S4 */
UINT32_BIT TmrValExt : 1; /* tmr_val is 32 bits */
UINT32_BIT DockCap : 1; /* Supports Docking */
UINT32_BIT ResetRegSup : 1; /* Indicates system supports system reset via the FADT RESET_REG*/
UINT32_BIT SealedCase : 1; /* Indicates system has no internal expansion capabilities and case is sealed. */
UINT32_BIT Headless : 1; /* Indicates system does not have local video capabilities or local input devices.*/
UINT32_BIT CpuSwSleep : 1; /* Indicates to OSPM that a processor native instruction */
/* must be executed after writing the SLP_TYPx register. */
UINT32_BIT Reserved6 : 18; /* reserved - must be zero */
ACPI_TABLE_HEADER header; /* table header */
UINT32 V1_FirmwareCtrl; /* 32-bit physical address of FACS */
UINT32 V1_Dsdt; /* 32-bit physical address of DSDT */
UINT8 Reserved1; /* System Interrupt Model isn't used in ACPI 2.0*/
UINT8 Prefer_PM_Profile; /* Conveys preferred power management profile to OSPM. */
UINT16 SciInt; /* System vector of SCI interrupt */
UINT32 SmiCmd; /* Port address of SMI command port */
UINT8 AcpiEnable; /* value to write to smi_cmd to enable ACPI */
UINT8 AcpiDisable; /* value to write to smi_cmd to disable ACPI */
UINT8 S4BiosReq; /* Value to write to SMI CMD to enter S4BIOS state */
UINT8 PstateCnt; /* processor performance state control*/
UINT32 V1_Pm1aEvtBlk; /* Port address of Power Mgt 1a AcpiEvent Reg Blk */
UINT32 V1_Pm1bEvtBlk; /* Port address of Power Mgt 1b AcpiEvent Reg Blk */
UINT32 V1_Pm1aCntBlk; /* Port address of Power Mgt 1a Control Reg Blk */
UINT32 V1_Pm1bCntBlk; /* Port address of Power Mgt 1b Control Reg Blk */
UINT32 V1_Pm2CntBlk; /* Port address of Power Mgt 2 Control Reg Blk */
UINT32 V1_PmTmrBlk; /* Port address of Power Mgt Timer Ctrl Reg Blk */
UINT32 V1_Gpe0Blk; /* Port addr of General Purpose AcpiEvent 0 Reg Blk */
UINT32 V1_Gpe1Blk; /* Port addr of General Purpose AcpiEvent 1 Reg Blk */
UINT8 Pm1EvtLen; /* Byte Length of ports at pm1X_evt_blk */
UINT8 Pm1CntLen; /* Byte Length of ports at pm1X_cnt_blk */
UINT8 Pm2CntLen; /* Byte Length of ports at pm2_cnt_blk */
UINT8 PmTmLen; /* Byte Length of ports at pm_tm_blk */
UINT8 Gpe0BlkLen; /* Byte Length of ports at gpe0_blk */
UINT8 Gpe1BlkLen; /* Byte Length of ports at gpe1_blk */
UINT8 Gpe1Base; /* offset in gpe model where gpe1 events start */
UINT8 CstCnt; /* Support for the _CST object and C States change notification.*/
UINT16 Plvl2Lat; /* worst case HW latency to enter/exit C2 state */
UINT16 Plvl3Lat; /* worst case HW latency to enter/exit C3 state */
UINT16 FlushSize; /* number of flush strides that need to be read */
UINT16 FlushStride; /* Processor's memory cache line width, in bytes */
UINT8 DutyOffset; /* Processor’s duty cycle index in processor's P_CNT reg*/
UINT8 DutyWidth; /* Processor’s duty cycle value bit width in P_CNT register.*/
UINT8 DayAlrm; /* index to day-of-month alarm in RTC CMOS RAM */
UINT8 MonAlrm; /* index to month-of-year alarm in RTC CMOS RAM */
UINT8 Century; /* index to century in RTC CMOS RAM */
UINT16 IapcBootArch; /* IA-PC Boot Architecture Flags. See Table 5-10 for description*/
UINT8 Reserved2; /* reserved */
UINT32_BIT WbInvd : 1; /* wbinvd instruction works properly */
UINT32_BIT WbInvdFlush : 1; /* wbinvd flushes but does not invalidate */
UINT32_BIT ProcC1 : 1; /* all processors support C1 state */
UINT32_BIT Plvl2Up : 1; /* C2 state works on MP system */
UINT32_BIT PwrButton : 1; /* Power button is handled as a generic feature */
UINT32_BIT SleepButton : 1; /* Sleep button is handled as a generic feature, or not present */
UINT32_BIT FixedRTC : 1; /* RTC wakeup stat not in fixed register space */
UINT32_BIT Rtcs4 : 1; /* RTC wakeup stat not possible from S4 */
UINT32_BIT TmrValExt : 1; /* tmr_val is 32 bits */
UINT32_BIT DockCap : 1; /* Supports Docking */
UINT32_BIT ResetRegSup : 1; /* Indicates system supports system reset via the FADT RESET_REG*/
UINT32_BIT SealedCase : 1; /* Indicates system has no internal expansion capabilities and case is sealed. */
UINT32_BIT Headless : 1; /* Indicates system does not have local video capabilities or local input devices.*/
UINT32_BIT CpuSwSleep : 1; /* Indicates to OSPM that a processor native instruction */
/* must be executed after writing the SLP_TYPx register. */
UINT32_BIT Reserved6 : 18; /* reserved - must be zero */
ACPI_GAS ResetRegister; /* Reset register address in GAS format */
UINT8 ResetValue; /* Value to write to the ResetRegister port to reset the system. */
UINT8 Reserved7[3]; /* These three bytes must be zero */
UINT64 XFirmwareCtrl; /* 64-bit physical address of FACS */
UINT64 XDsdt; /* 64-bit physical address of DSDT */
ACPI_GAS XPm1aEvtBlk; /* Extended Power Mgt 1a AcpiEvent Reg Blk address */
ACPI_GAS XPm1bEvtBlk; /* Extended Power Mgt 1b AcpiEvent Reg Blk address */
ACPI_GAS XPm1aCntBlk; /* Extended Power Mgt 1a Control Reg Blk address */
ACPI_GAS XPm1bCntBlk; /* Extended Power Mgt 1b Control Reg Blk address */
ACPI_GAS XPm2CntBlk; /* Extended Power Mgt 2 Control Reg Blk address */
ACPI_GAS XPmTmrBlk; /* Extended Power Mgt Timer Ctrl Reg Blk address */
ACPI_GAS XGpe0Blk; /* Extended General Purpose AcpiEvent 0 Reg Blk address */
ACPI_GAS XGpe1Blk; /* Extended General Purpose AcpiEvent 1 Reg Blk address */
ACPI_GENERIC_ADDRESS ResetRegister; /* Reset register address in GAS format */
UINT8 ResetValue; /* Value to write to the ResetRegister port to reset the system. */
UINT8 Reserved7[3]; /* These three bytes must be zero */
UINT64 XFirmwareCtrl; /* 64-bit physical address of FACS */
UINT64 XDsdt; /* 64-bit physical address of DSDT */
ACPI_GENERIC_ADDRESS XPm1aEvtBlk; /* Extended Power Mgt 1a AcpiEvent Reg Blk address */
ACPI_GENERIC_ADDRESS XPm1bEvtBlk; /* Extended Power Mgt 1b AcpiEvent Reg Blk address */
ACPI_GENERIC_ADDRESS XPm1aCntBlk; /* Extended Power Mgt 1a Control Reg Blk address */
ACPI_GENERIC_ADDRESS XPm1bCntBlk; /* Extended Power Mgt 1b Control Reg Blk address */
ACPI_GENERIC_ADDRESS XPm2CntBlk; /* Extended Power Mgt 2 Control Reg Blk address */
ACPI_GENERIC_ADDRESS XPmTmrBlk; /* Extended Power Mgt Timer Ctrl Reg Blk address */
ACPI_GENERIC_ADDRESS XGpe0Blk; /* Extended General Purpose AcpiEvent 0 Reg Blk address */
ACPI_GENERIC_ADDRESS XGpe1Blk; /* Extended General Purpose AcpiEvent 1 Reg Blk address */
} FADT_DESCRIPTOR_REV2;