2005-06-29 16:54:00 +00:00
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/*
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__________________________________________________________________________
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| Copyright (C) Intel Corporation 1994-1996
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| All rights reserved. No part of this program or publication may be
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| reproduced, transmitted, transcribed, stored in a retrieval system, or
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| translated into any language or computer language, in any form or by any
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| means, electronic, mechanical, magnetic, optical, chemical, manual, or
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| otherwise, without the prior written permission of Intel Corporation.
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|__________________________________________________________________________
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2005-06-29 16:54:04 +00:00
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| Read/write access functions for the various ACPI
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| control and status registers.
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2005-06-29 16:54:00 +00:00
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|__________________________________________________________________________
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2005-06-29 16:54:12 +00:00
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| $Revision: 1.12 $
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| $Date: 2005/06/29 16:54:12 $
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2005-06-29 16:54:00 +00:00
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| $Log: hwregs.c,v $
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2005-06-29 16:54:12 +00:00
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| Revision 1.12 2005/06/29 16:54:12 aystarik
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| Major header file consolidation
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2005-06-29 16:54:00 +00:00
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2005-06-29 16:54:12 +00:00
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| date 99.04.07.22.33.00; author rmoore1; state Exp;
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2005-06-29 16:54:00 +00:00
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*
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2005-06-29 16:54:12 +00:00
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* 12 4/07/99 3:33p Rmoore1
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* Major header file consolidation
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*
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2005-06-29 16:54:11 +00:00
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* 11 4/05/99 4:09p Rmoore1
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* Header cleanup; Split debug switch into component_id and level
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*
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2005-06-29 16:54:10 +00:00
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* 10 4/02/99 2:40p Rmoore1
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* New version of DEBUG_PRINT
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*
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2005-06-29 16:54:09 +00:00
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* 9 3/31/99 2:32p Rmoore1
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* Integrated with 03/99 OPSD code
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*
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2005-06-29 16:54:08 +00:00
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* 8 3/09/99 4:05p Rmoore1
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* 16/32/64-bit common data types
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*
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2005-06-29 16:54:06 +00:00
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* 7 2/16/99 9:35a Rmosgrov
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* Anti-Polish Complete - Compiles
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*
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2005-06-29 16:54:05 +00:00
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* 6 2/11/99 5:51p Rmosgrov
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* Anti-Polish
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*
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2005-06-29 16:54:04 +00:00
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* 5 1/20/99 9:38a Rmoore1
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* Major Cleanup
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*
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2005-06-29 16:54:03 +00:00
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* 4 1/13/99 2:53p Rmoore1
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* includes acpiasm.h
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*
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2005-06-29 16:54:02 +00:00
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* 3 1/13/99 2:39p Grsmith1
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*
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2005-06-29 16:54:01 +00:00
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* 2 1/11/99 4:07p Grsmith1
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* Detabified.
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*
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2005-06-29 16:54:00 +00:00
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* 1 1/11/99 2:07p Rmoore1
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* Hardware Specific Modules
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//
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// Rev 1.0 Apr 14 1997 14:10:58 kdbranno
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// Initial revision.
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|__________________________________________________________________________
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*/
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2005-06-29 16:54:04 +00:00
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#define __DVREGS_C__
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2005-06-29 16:54:09 +00:00
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#include <acpi.h>
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2005-06-29 16:54:12 +00:00
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#include <devices.h>
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2005-06-29 16:54:00 +00:00
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#include <stdarg.h>
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2005-06-29 16:54:09 +00:00
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2005-06-29 16:54:11 +00:00
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#define _THIS_MODULE "dvregs.c"
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#define _COMPONENT DEVICE_MANAGER
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2005-06-29 16:54:00 +00:00
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#pragma check_stack (off)
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2005-06-29 15:40:01 +00:00
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2005-06-29 16:54:04 +00:00
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2005-06-29 15:40:01 +00:00
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/******************************************************************************
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*
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2005-06-29 16:54:05 +00:00
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* FUNCTION: GetBitShift
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2005-06-29 16:54:04 +00:00
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*
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2005-06-29 16:54:08 +00:00
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* PARAMETERS: UINT32 Mask - input mask to determine bit shift from. Must
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2005-06-29 16:54:04 +00:00
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* have at least 1 bit set.
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2005-06-29 16:53:22 +00:00
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*
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2005-06-29 16:54:04 +00:00
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* RETURN: bit location of the lsb of the mask
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2005-06-29 16:52:01 +00:00
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*
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2005-06-29 16:54:01 +00:00
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* DESCRIPTION: returns the bit number for the low order bit that's set.
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2005-06-29 16:53:22 +00:00
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*
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******************************************************************************/
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2005-06-29 16:54:04 +00:00
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2005-06-29 16:54:08 +00:00
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INT32
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GetBitShift (UINT32 Mask)
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2005-06-29 16:53:22 +00:00
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{
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2005-06-29 16:54:08 +00:00
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INT32 Shift;
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2005-06-29 16:54:04 +00:00
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2005-06-29 16:54:05 +00:00
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FUNCTION_TRACE ("GetBitShift");
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2005-06-29 16:53:36 +00:00
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2005-06-29 16:54:05 +00:00
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for (Shift = 0; ((Mask >> Shift) & 1) == 0; Shift++)
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2005-06-29 16:54:04 +00:00
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{ ; }
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2005-06-29 16:54:05 +00:00
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return (Shift);
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2005-06-29 16:53:22 +00:00
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}
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2005-06-29 16:53:06 +00:00
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2005-06-29 16:54:04 +00:00
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2005-06-29 16:53:06 +00:00
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/******************************************************************************
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*
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2005-06-29 16:54:05 +00:00
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* FUNCTION: AcpiRegisterIO
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2005-06-29 16:53:06 +00:00
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*
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2005-06-29 16:54:08 +00:00
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* PARAMETERS: INT32 ReadWrite - Either ACPI_READ or ACPI_WRITE.
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* INT32 RegisterId - index of ACPI register to access
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* UINT32 Value - (only used on write) value to write to the
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* register. This value is shifted all the way right.
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2005-06-29 16:54:04 +00:00
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*
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* RETURN: value written to or read from specified register. This value
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* is shifted all the way right.
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2005-06-29 16:53:06 +00:00
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*
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2005-06-29 16:54:01 +00:00
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* DESCRIPTION: Generic ACPI register read/write function.
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2005-06-29 16:53:06 +00:00
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*
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******************************************************************************/
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2005-06-29 16:54:04 +00:00
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2005-06-29 16:54:08 +00:00
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UINT32
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AcpiRegisterIO (INT32 ReadWrite, INT32 RegisterId, ... /* UINT32 Value */)
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2005-06-29 16:53:06 +00:00
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{
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2005-06-29 16:54:08 +00:00
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UINT32 RegisterValue;
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UINT32 Mask;
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UINT32 Value;
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UINT32 GpeReg = 0;
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2005-06-29 16:54:04 +00:00
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2005-06-29 16:54:05 +00:00
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FUNCTION_TRACE ("AcpiRegisterIO");
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2005-06-29 16:54:00 +00:00
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2005-06-29 16:54:01 +00:00
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2005-06-29 16:54:05 +00:00
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if (ReadWrite == ACPI_WRITE)
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2005-06-29 16:54:01 +00:00
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{
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2005-06-29 16:54:04 +00:00
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va_list marker;
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2005-06-29 16:54:00 +00:00
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2005-06-29 16:54:05 +00:00
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va_start (marker, RegisterId);
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2005-06-29 16:54:08 +00:00
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Value = va_arg (marker, INT32);
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2005-06-29 16:54:01 +00:00
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va_end (marker);
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}
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2005-06-29 16:54:00 +00:00
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2005-06-29 16:54:05 +00:00
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switch (RegisterId & REGISTER_BLOCK_MASK)
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2005-06-29 16:54:01 +00:00
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{
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case PM1_EVT:
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2005-06-29 16:54:08 +00:00
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if (RegisterId < (INT32) TMR_EN)
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2005-06-29 16:54:04 +00:00
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{
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/* status register */
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2005-06-29 16:54:08 +00:00
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RegisterValue = (UINT32) OsdIn16 ((UINT16) FACP->Pm1aEvtBlk);
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2005-06-29 16:54:04 +00:00
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2005-06-29 16:54:05 +00:00
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if (FACP->Pm1bEvtBlk)
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2005-06-29 16:54:04 +00:00
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{
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2005-06-29 16:54:08 +00:00
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RegisterValue |= (UINT32) OsdIn16 ((UINT16) FACP->Pm1bEvtBlk);
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2005-06-29 16:54:04 +00:00
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}
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2005-06-29 16:54:05 +00:00
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switch (RegisterId)
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2005-06-29 16:54:01 +00:00
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{
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case TMR_STS:
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2005-06-29 16:54:05 +00:00
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Mask = TMR_STS_MASK;
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2005-06-29 16:54:01 +00:00
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break;
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2005-06-29 16:54:04 +00:00
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2005-06-29 16:54:01 +00:00
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case BM_STS:
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2005-06-29 16:54:05 +00:00
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Mask = BM_STS_MASK;
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2005-06-29 16:54:01 +00:00
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break;
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2005-06-29 16:54:04 +00:00
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2005-06-29 16:54:01 +00:00
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case GBL_STS:
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2005-06-29 16:54:05 +00:00
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Mask = GBL_STS_MASK;
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2005-06-29 16:54:01 +00:00
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break;
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2005-06-29 16:54:04 +00:00
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2005-06-29 16:54:01 +00:00
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case PWRBTN_STS:
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2005-06-29 16:54:05 +00:00
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Mask = PWRBTN_STS_MASK;
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2005-06-29 16:54:01 +00:00
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break;
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2005-06-29 16:54:04 +00:00
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2005-06-29 16:54:01 +00:00
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case SLPBTN_STS:
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2005-06-29 16:54:05 +00:00
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Mask = SLPBTN_STS_MASK;
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2005-06-29 16:54:01 +00:00
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break;
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2005-06-29 16:54:04 +00:00
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2005-06-29 16:54:01 +00:00
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case RTC_STS:
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2005-06-29 16:54:05 +00:00
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Mask = RTC_STS_MASK;
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2005-06-29 16:54:01 +00:00
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break;
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2005-06-29 16:54:04 +00:00
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2005-06-29 16:54:01 +00:00
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case WAK_STS:
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2005-06-29 16:54:05 +00:00
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Mask = WAK_STS_MASK;
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2005-06-29 16:54:01 +00:00
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break;
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2005-06-29 16:54:04 +00:00
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2005-06-29 16:54:01 +00:00
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default:
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2005-06-29 16:54:05 +00:00
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Mask = 0;
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2005-06-29 16:54:01 +00:00
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break;
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}
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2005-06-29 16:54:04 +00:00
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2005-06-29 16:54:05 +00:00
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if (ReadWrite == ACPI_WRITE)
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2005-06-29 16:54:01 +00:00
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{
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2005-06-29 16:54:04 +00:00
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/*
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* status registers are different from the rest. Clear by writing 1, writing 0
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* has no effect. So, the only relevent information is the single bit we're
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* interested in, all others should be written as 0 so they will be left
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* unchanged
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*/
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2005-06-29 16:54:05 +00:00
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Value <<= GetBitShift (Mask);
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Value &= Mask;
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2005-06-29 16:54:04 +00:00
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2005-06-29 16:54:05 +00:00
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if (Value)
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2005-06-29 16:54:01 +00:00
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{
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2005-06-29 16:54:11 +00:00
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DEBUG_PRINT (ACPI_INFO, ("About to write %04X to %04X\n", (UINT16) Value,
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2005-06-29 16:54:10 +00:00
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(UINT16) FACP->Pm1aEvtBlk));
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2005-06-29 16:54:08 +00:00
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OsdOut16 ((UINT16) FACP->Pm1aEvtBlk, (UINT16) Value);
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2005-06-29 16:54:04 +00:00
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2005-06-29 16:54:05 +00:00
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if (FACP->Pm1bEvtBlk)
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2005-06-29 16:54:04 +00:00
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{
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2005-06-29 16:54:08 +00:00
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OsdOut16 ((UINT16) FACP->Pm1bEvtBlk, (UINT16) Value);
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2005-06-29 16:54:04 +00:00
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}
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2005-06-29 16:54:05 +00:00
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RegisterValue = 0;
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2005-06-29 16:54:01 +00:00
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}
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}
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}
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2005-06-29 16:54:04 +00:00
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2005-06-29 16:54:01 +00:00
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else
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2005-06-29 16:54:04 +00:00
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{
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/* enable register */
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2005-06-29 16:54:08 +00:00
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RegisterValue = (UINT32) OsdIn16 ((UINT16) (FACP->Pm1aEvtBlk + FACP->Pm1EvtLen / 2));
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2005-06-29 16:54:04 +00:00
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2005-06-29 16:54:05 +00:00
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if (FACP->Pm1bEvtBlk)
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2005-06-29 16:54:04 +00:00
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{
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2005-06-29 16:54:08 +00:00
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RegisterValue |= (UINT32) OsdIn16 ((UINT16) (FACP->Pm1bEvtBlk + FACP->Pm1EvtLen / 2));
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2005-06-29 16:54:04 +00:00
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}
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2005-06-29 16:54:05 +00:00
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switch (RegisterId)
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2005-06-29 16:54:01 +00:00
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{
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case TMR_EN:
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2005-06-29 16:54:05 +00:00
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Mask = TMR_EN_MASK;
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2005-06-29 16:54:01 +00:00
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break;
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2005-06-29 16:54:04 +00:00
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2005-06-29 16:54:01 +00:00
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case GBL_EN:
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2005-06-29 16:54:05 +00:00
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Mask = GBL_EN_MASK;
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2005-06-29 16:54:01 +00:00
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break;
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2005-06-29 16:54:04 +00:00
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2005-06-29 16:54:01 +00:00
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case PWRBTN_EN:
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2005-06-29 16:54:05 +00:00
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Mask = PWRBTN_EN_MASK;
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2005-06-29 16:54:01 +00:00
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break;
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2005-06-29 16:54:04 +00:00
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2005-06-29 16:54:01 +00:00
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case SLPBTN_EN:
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2005-06-29 16:54:05 +00:00
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Mask = SLPBTN_EN_MASK;
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2005-06-29 16:54:01 +00:00
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break;
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2005-06-29 16:54:04 +00:00
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2005-06-29 16:54:01 +00:00
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case RTC_EN:
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2005-06-29 16:54:05 +00:00
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Mask = RTC_EN_MASK;
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2005-06-29 16:54:01 +00:00
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break;
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2005-06-29 16:54:04 +00:00
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2005-06-29 16:54:01 +00:00
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default:
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2005-06-29 16:54:05 +00:00
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Mask = 0;
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2005-06-29 16:54:01 +00:00
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break;
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}
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2005-06-29 16:54:04 +00:00
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2005-06-29 16:54:05 +00:00
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if (ReadWrite == ACPI_WRITE)
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2005-06-29 16:54:01 +00:00
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{
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2005-06-29 16:54:05 +00:00
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RegisterValue &= ~Mask;
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Value <<= GetBitShift (Mask);
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Value &= Mask;
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RegisterValue |= Value;
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2005-06-29 16:54:09 +00:00
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2005-06-29 16:54:11 +00:00
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DEBUG_PRINT (ACPI_INFO, ("About to write %04X to %04X\n", (UINT16) RegisterValue,
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2005-06-29 16:54:10 +00:00
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|
|
(UINT16) (FACP->Pm1aEvtBlk + FACP->Pm1EvtLen / 2)));
|
2005-06-29 16:54:09 +00:00
|
|
|
|
2005-06-29 16:54:08 +00:00
|
|
|
OsdOut16 ((UINT16) (FACP->Pm1aEvtBlk + FACP->Pm1EvtLen / 2),
|
|
|
|
(UINT16) RegisterValue);
|
2005-06-29 16:54:04 +00:00
|
|
|
|
2005-06-29 16:54:05 +00:00
|
|
|
if (FACP->Pm1bEvtBlk)
|
2005-06-29 16:54:04 +00:00
|
|
|
{
|
2005-06-29 16:54:08 +00:00
|
|
|
OsdOut16 ((UINT16)(FACP->Pm1bEvtBlk + FACP->Pm1EvtLen / 2),
|
|
|
|
(UINT16) RegisterValue);
|
2005-06-29 16:54:04 +00:00
|
|
|
}
|
2005-06-29 16:54:01 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
break;
|
2005-06-29 16:54:04 +00:00
|
|
|
|
2005-06-29 16:54:01 +00:00
|
|
|
case PM1_CONTROL:
|
2005-06-29 16:54:05 +00:00
|
|
|
RegisterValue = 0;
|
2005-06-29 16:54:04 +00:00
|
|
|
|
2005-06-29 16:54:08 +00:00
|
|
|
if (RegisterId != (INT32) SLP_TYPb)
|
2005-06-29 16:54:04 +00:00
|
|
|
{
|
|
|
|
/*
|
|
|
|
* SLP_TYPx registers are written differently
|
|
|
|
* than any other control registers with
|
|
|
|
* respect to A and B registers. The value
|
|
|
|
* for A may be different than the value for B
|
|
|
|
*/
|
|
|
|
|
2005-06-29 16:54:08 +00:00
|
|
|
RegisterValue = (UINT32) OsdIn16 ((UINT16) FACP->Pm1aCntBlk);
|
2005-06-29 16:54:04 +00:00
|
|
|
}
|
|
|
|
|
2005-06-29 16:54:09 +00:00
|
|
|
if (FACP->Pm1bEvtBlk && RegisterId != (INT32) SLP_TYPa)
|
2005-06-29 16:54:04 +00:00
|
|
|
{
|
2005-06-29 16:54:08 +00:00
|
|
|
RegisterValue |= (UINT32) OsdIn16 ((UINT16) FACP->Pm1bCntBlk);
|
2005-06-29 16:54:04 +00:00
|
|
|
}
|
|
|
|
|
2005-06-29 16:54:05 +00:00
|
|
|
switch (RegisterId)
|
2005-06-29 16:54:01 +00:00
|
|
|
{
|
|
|
|
case SCI_EN:
|
2005-06-29 16:54:05 +00:00
|
|
|
Mask = SCI_EN_MASK;
|
2005-06-29 16:54:01 +00:00
|
|
|
break;
|
2005-06-29 16:54:04 +00:00
|
|
|
|
2005-06-29 16:54:01 +00:00
|
|
|
case BM_RLD:
|
2005-06-29 16:54:05 +00:00
|
|
|
Mask = BM_RLD_MASK;
|
2005-06-29 16:54:01 +00:00
|
|
|
break;
|
2005-06-29 16:54:04 +00:00
|
|
|
|
2005-06-29 16:54:01 +00:00
|
|
|
case GBL_RLS:
|
2005-06-29 16:54:05 +00:00
|
|
|
Mask = GBL_RLS_MASK;
|
2005-06-29 16:54:01 +00:00
|
|
|
break;
|
2005-06-29 16:54:04 +00:00
|
|
|
|
2005-06-29 16:54:01 +00:00
|
|
|
case SLP_TYPa:
|
|
|
|
case SLP_TYPb:
|
2005-06-29 16:54:05 +00:00
|
|
|
Mask = SLP_TYPx_MASK;
|
2005-06-29 16:54:01 +00:00
|
|
|
break;
|
2005-06-29 16:54:04 +00:00
|
|
|
|
2005-06-29 16:54:01 +00:00
|
|
|
case SLP_EN:
|
2005-06-29 16:54:05 +00:00
|
|
|
Mask = SLP_EN_MASK;
|
2005-06-29 16:54:01 +00:00
|
|
|
break;
|
2005-06-29 16:54:09 +00:00
|
|
|
|
2005-06-29 16:54:01 +00:00
|
|
|
default:
|
2005-06-29 16:54:05 +00:00
|
|
|
Mask = 0;
|
2005-06-29 16:54:01 +00:00
|
|
|
break;
|
|
|
|
}
|
2005-06-29 16:54:04 +00:00
|
|
|
|
2005-06-29 16:54:05 +00:00
|
|
|
if (ReadWrite == ACPI_WRITE)
|
2005-06-29 16:54:01 +00:00
|
|
|
{
|
2005-06-29 16:54:05 +00:00
|
|
|
RegisterValue &= ~Mask;
|
|
|
|
Value <<= GetBitShift (Mask);
|
|
|
|
Value &= Mask;
|
|
|
|
RegisterValue |= Value;
|
2005-06-29 16:54:04 +00:00
|
|
|
|
|
|
|
/*
|
|
|
|
* SLP_TYPx registers are written differently
|
|
|
|
* than any other control registers with
|
|
|
|
* respect to A and B registers. The value
|
|
|
|
* for A may be different than the value for B
|
|
|
|
*/
|
|
|
|
|
2005-06-29 16:54:08 +00:00
|
|
|
if (RegisterId != (INT32) SLP_TYPb)
|
2005-06-29 16:54:01 +00:00
|
|
|
{
|
2005-06-29 16:54:05 +00:00
|
|
|
if (Mask == SLP_EN_MASK)
|
2005-06-29 16:54:04 +00:00
|
|
|
{
|
2005-06-29 16:54:01 +00:00
|
|
|
disable(); /* disable interrupts */
|
2005-06-29 16:54:04 +00:00
|
|
|
}
|
|
|
|
|
2005-06-29 16:54:08 +00:00
|
|
|
OsdOut16 ((UINT16) FACP->Pm1aCntBlk, (UINT16) RegisterValue);
|
2005-06-29 16:54:04 +00:00
|
|
|
|
2005-06-29 16:54:05 +00:00
|
|
|
if (Mask == SLP_EN_MASK)
|
2005-06-29 16:54:04 +00:00
|
|
|
{
|
|
|
|
/*
|
|
|
|
* enable interrupts, the SCI handler is likely going to be invoked as
|
|
|
|
* soon as interrupts are enabled, since gpe's and most fixed resume
|
|
|
|
* events also generate SCI's.
|
|
|
|
*/
|
2005-06-29 16:54:01 +00:00
|
|
|
enable();
|
2005-06-29 16:54:04 +00:00
|
|
|
}
|
2005-06-29 16:54:01 +00:00
|
|
|
}
|
|
|
|
|
2005-06-29 16:54:08 +00:00
|
|
|
if (FACP->Pm1bEvtBlk && RegisterId != (INT32) SLP_TYPa)
|
2005-06-29 16:54:04 +00:00
|
|
|
{
|
2005-06-29 16:54:08 +00:00
|
|
|
OsdOut16 ((UINT16) FACP->Pm1bCntBlk, (UINT16) RegisterValue);
|
2005-06-29 16:54:04 +00:00
|
|
|
}
|
2005-06-29 16:54:01 +00:00
|
|
|
}
|
|
|
|
break;
|
2005-06-29 16:54:04 +00:00
|
|
|
|
2005-06-29 16:54:01 +00:00
|
|
|
case PM2_CONTROL:
|
2005-06-29 16:54:08 +00:00
|
|
|
RegisterValue = (UINT32) OsdIn16 ((UINT16) FACP->Pm2CntBlk);
|
2005-06-29 16:54:04 +00:00
|
|
|
|
2005-06-29 16:54:05 +00:00
|
|
|
switch (RegisterId)
|
2005-06-29 16:54:01 +00:00
|
|
|
{
|
|
|
|
case ARB_DIS:
|
2005-06-29 16:54:05 +00:00
|
|
|
Mask = ARB_DIS_MASK;
|
2005-06-29 16:54:01 +00:00
|
|
|
break;
|
2005-06-29 16:54:04 +00:00
|
|
|
|
2005-06-29 16:54:01 +00:00
|
|
|
default:
|
2005-06-29 16:54:05 +00:00
|
|
|
Mask = 0;
|
2005-06-29 16:54:01 +00:00
|
|
|
break;
|
|
|
|
}
|
2005-06-29 16:54:04 +00:00
|
|
|
|
2005-06-29 16:54:05 +00:00
|
|
|
if (ReadWrite == ACPI_WRITE)
|
2005-06-29 16:54:01 +00:00
|
|
|
{
|
2005-06-29 16:54:05 +00:00
|
|
|
RegisterValue &= ~Mask;
|
|
|
|
Value <<= GetBitShift (Mask);
|
|
|
|
Value &= Mask;
|
|
|
|
RegisterValue |= Value;
|
2005-06-29 16:54:09 +00:00
|
|
|
|
2005-06-29 16:54:11 +00:00
|
|
|
DEBUG_PRINT (ACPI_INFO, ("About to write %04X to %04X\n", (UINT16) RegisterValue,
|
2005-06-29 16:54:10 +00:00
|
|
|
(UINT16) FACP->Pm2CntBlk));
|
2005-06-29 16:54:09 +00:00
|
|
|
|
2005-06-29 16:54:08 +00:00
|
|
|
OsdOut16 ((UINT16) FACP->Pm2CntBlk, (UINT16) RegisterValue);
|
2005-06-29 16:54:01 +00:00
|
|
|
}
|
|
|
|
break;
|
2005-06-29 16:54:04 +00:00
|
|
|
|
2005-06-29 16:54:01 +00:00
|
|
|
case PM_TIMER:
|
2005-06-29 16:54:08 +00:00
|
|
|
RegisterValue = OsdIn32 ((UINT16) FACP->PmTmrBlk);
|
2005-06-29 16:54:05 +00:00
|
|
|
Mask = 0xFFFFFFFF;
|
2005-06-29 16:54:01 +00:00
|
|
|
break;
|
2005-06-29 16:54:04 +00:00
|
|
|
|
2005-06-29 16:54:01 +00:00
|
|
|
case GPE1_EN_BLOCK:
|
2005-06-29 16:54:08 +00:00
|
|
|
GpeReg = (FACP->Gpe1Blk + (UINT32) FACP->Gpe1Base) + (GpeReg +
|
|
|
|
((UINT32) ((FACP->Gpe1BlkLen) / 2)));
|
2005-06-29 16:54:04 +00:00
|
|
|
|
2005-06-29 16:54:01 +00:00
|
|
|
case GPE1_STS_BLOCK:
|
2005-06-29 16:54:05 +00:00
|
|
|
if (!GpeReg)
|
2005-06-29 16:54:04 +00:00
|
|
|
{
|
2005-06-29 16:54:08 +00:00
|
|
|
GpeReg = (FACP->Gpe1Blk + (UINT32) FACP->Gpe1Base);
|
2005-06-29 16:54:04 +00:00
|
|
|
}
|
|
|
|
|
2005-06-29 16:54:01 +00:00
|
|
|
case GPE0_EN_BLOCK:
|
2005-06-29 16:54:05 +00:00
|
|
|
if (!GpeReg)
|
2005-06-29 16:54:04 +00:00
|
|
|
{
|
2005-06-29 16:54:08 +00:00
|
|
|
GpeReg = FACP->Gpe0Blk + ((UINT32) ((FACP->Gpe0BlkLen) / 2));
|
2005-06-29 16:54:04 +00:00
|
|
|
}
|
2005-06-29 16:54:01 +00:00
|
|
|
|
|
|
|
case GPE0_STS_BLOCK:
|
2005-06-29 16:54:05 +00:00
|
|
|
if (!GpeReg)
|
2005-06-29 16:54:04 +00:00
|
|
|
{
|
2005-06-29 16:54:05 +00:00
|
|
|
GpeReg = FACP->Gpe0Blk;
|
2005-06-29 16:54:04 +00:00
|
|
|
}
|
|
|
|
|
2005-06-29 16:54:01 +00:00
|
|
|
/* Determine the bit to be accessed */
|
2005-06-29 16:54:04 +00:00
|
|
|
|
2005-06-29 16:54:08 +00:00
|
|
|
Mask = (((UINT32) RegisterId) & BIT_IN_REGISTER_MASK);
|
2005-06-29 16:54:05 +00:00
|
|
|
Mask = 1 << (Mask-1);
|
2005-06-29 16:54:04 +00:00
|
|
|
|
2005-06-29 16:54:01 +00:00
|
|
|
/* The base address of the GPE 0 Register Block */
|
|
|
|
/* Plus 1/2 the length of the GPE 0 Register Block */
|
|
|
|
/* The enable register is the register following the Status Register */
|
|
|
|
/* and each register is defined as 1/2 of the total Register Block */
|
|
|
|
|
|
|
|
/* This sets the bit within wEnableBit that needs to be written to */
|
2005-06-29 16:54:05 +00:00
|
|
|
/* the register indicated in Mask to a 1, all others are 0 */
|
2005-06-29 16:54:01 +00:00
|
|
|
|
2005-06-29 16:54:05 +00:00
|
|
|
if (Mask > LOW_BYTE)
|
2005-06-29 16:54:01 +00:00
|
|
|
{
|
|
|
|
/* Shift the value 1 byte to the right and add 1 to the register */
|
2005-06-29 16:54:04 +00:00
|
|
|
|
2005-06-29 16:54:05 +00:00
|
|
|
Mask >>= ONE_BYTE;
|
|
|
|
GpeReg++;
|
2005-06-29 16:54:01 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
/* Now get the current Enable Bits in the selected Reg */
|
2005-06-29 16:54:04 +00:00
|
|
|
|
2005-06-29 16:54:08 +00:00
|
|
|
RegisterValue = (UINT32) OsdIn8 ((UINT16) GpeReg);
|
2005-06-29 16:54:01 +00:00
|
|
|
|
2005-06-29 16:54:05 +00:00
|
|
|
if (ReadWrite == ACPI_WRITE)
|
2005-06-29 16:54:01 +00:00
|
|
|
{
|
2005-06-29 16:54:05 +00:00
|
|
|
RegisterValue &= ~Mask;
|
|
|
|
Value <<= GetBitShift (Mask);
|
|
|
|
Value &= Mask;
|
|
|
|
RegisterValue |= Value;
|
2005-06-29 16:54:04 +00:00
|
|
|
|
2005-06-29 16:54:01 +00:00
|
|
|
/* This write will put the iAction state into the General Purpose */
|
2005-06-29 16:54:05 +00:00
|
|
|
/* Enable Register indexed by the value in Mask */
|
2005-06-29 16:54:09 +00:00
|
|
|
|
2005-06-29 16:54:11 +00:00
|
|
|
DEBUG_PRINT (ACPI_INFO, ("About to write %04X to %04X\n", (UINT16) RegisterValue,
|
2005-06-29 16:54:10 +00:00
|
|
|
(UINT16) GpeReg));
|
2005-06-29 16:54:09 +00:00
|
|
|
|
2005-06-29 16:54:08 +00:00
|
|
|
OsdOut8 ((UINT16) GpeReg, (UINT8) RegisterValue);
|
|
|
|
RegisterValue = (UINT32) OsdIn8 ((UINT16) GpeReg);
|
2005-06-29 16:54:01 +00:00
|
|
|
}
|
|
|
|
break;
|
2005-06-29 16:54:04 +00:00
|
|
|
|
2005-06-29 16:54:01 +00:00
|
|
|
case PROCESSOR_BLOCK:
|
|
|
|
default:
|
2005-06-29 16:54:05 +00:00
|
|
|
Mask = 0;
|
2005-06-29 16:54:01 +00:00
|
|
|
break;
|
|
|
|
}
|
2005-06-29 16:54:00 +00:00
|
|
|
|
2005-06-29 16:54:05 +00:00
|
|
|
RegisterValue &= Mask;
|
|
|
|
RegisterValue >>= GetBitShift (Mask);
|
2005-06-29 16:54:00 +00:00
|
|
|
|
2005-06-29 16:54:05 +00:00
|
|
|
return (RegisterValue);
|
2005-06-29 16:53:06 +00:00
|
|
|
}
|
2005-06-29 16:54:04 +00:00
|
|
|
|
2005-06-29 16:54:00 +00:00
|
|
|
#pragma check_stack ()
|
2005-06-29 16:53:06 +00:00
|
|
|
|
2005-06-29 16:54:04 +00:00
|
|
|
|
2005-06-29 16:53:06 +00:00
|
|
|
/******************************************************************************
|
|
|
|
*
|
2005-06-29 16:54:05 +00:00
|
|
|
* FUNCTION: ClearAllAcpiChipsetStatusBits
|
2005-06-29 16:54:04 +00:00
|
|
|
*
|
|
|
|
* PARAMETERS: none
|
2005-06-29 16:53:06 +00:00
|
|
|
*
|
2005-06-29 16:54:04 +00:00
|
|
|
* RETURN: none
|
2005-06-29 16:53:06 +00:00
|
|
|
*
|
2005-06-29 16:54:01 +00:00
|
|
|
* DESCRIPTION: Clears all fixed and general purpose status bits
|
2005-06-29 16:53:06 +00:00
|
|
|
*
|
|
|
|
******************************************************************************/
|
2005-06-29 16:54:04 +00:00
|
|
|
|
|
|
|
void
|
2005-06-29 16:54:05 +00:00
|
|
|
ClearAllAcpiChipsetStatusBits (void)
|
2005-06-29 16:53:06 +00:00
|
|
|
{
|
2005-06-29 16:54:08 +00:00
|
|
|
UINT16 GpeLength;
|
|
|
|
UINT16 Index;
|
2005-06-29 16:54:04 +00:00
|
|
|
|
|
|
|
|
2005-06-29 16:54:05 +00:00
|
|
|
FUNCTION_TRACE ("ClearAllAcpiChipsetStatusBits");
|
2005-06-29 16:54:04 +00:00
|
|
|
|
2005-06-29 16:54:00 +00:00
|
|
|
|
2005-06-29 16:54:11 +00:00
|
|
|
DEBUG_PRINT (ACPI_INFO, ("About to write %04X to %04X\n",
|
2005-06-29 16:54:10 +00:00
|
|
|
ALL_FIXED_STS_BITS, (UINT16) FACP->Pm1aEvtBlk));
|
2005-06-29 16:54:04 +00:00
|
|
|
|
2005-06-29 16:54:08 +00:00
|
|
|
OsdOut16 ((UINT16) FACP->Pm1aEvtBlk, (UINT16) ALL_FIXED_STS_BITS);
|
2005-06-29 16:54:04 +00:00
|
|
|
|
2005-06-29 16:54:05 +00:00
|
|
|
if (FACP->Pm1bEvtBlk)
|
2005-06-29 16:54:04 +00:00
|
|
|
{
|
2005-06-29 16:54:08 +00:00
|
|
|
OsdOut16 ((UINT16) FACP->Pm1bEvtBlk, (UINT16) ALL_FIXED_STS_BITS);
|
2005-06-29 16:54:04 +00:00
|
|
|
}
|
|
|
|
|
2005-06-29 16:54:09 +00:00
|
|
|
/* now clear the GPE Bits */
|
2005-06-29 16:54:04 +00:00
|
|
|
|
2005-06-29 16:54:05 +00:00
|
|
|
if (FACP->Gpe0BlkLen)
|
2005-06-29 16:54:01 +00:00
|
|
|
{
|
2005-06-29 16:54:05 +00:00
|
|
|
GpeLength = FACP->Gpe0BlkLen / 2;
|
2005-06-29 16:54:04 +00:00
|
|
|
|
2005-06-29 16:54:05 +00:00
|
|
|
for (Index = 0; Index < GpeLength; Index++)
|
2005-06-29 16:54:04 +00:00
|
|
|
{
|
2005-06-29 16:54:08 +00:00
|
|
|
OsdOut8 ((UINT16) (FACP->Gpe0Blk + Index), (UINT8) 0xff);
|
2005-06-29 16:54:04 +00:00
|
|
|
}
|
2005-06-29 16:54:01 +00:00
|
|
|
}
|
2005-06-29 16:54:04 +00:00
|
|
|
|
2005-06-29 16:54:05 +00:00
|
|
|
if (FACP->Gpe1BlkLen)
|
2005-06-29 16:54:01 +00:00
|
|
|
{
|
2005-06-29 16:54:05 +00:00
|
|
|
GpeLength = FACP->Gpe1BlkLen / 2;
|
2005-06-29 16:54:04 +00:00
|
|
|
|
2005-06-29 16:54:05 +00:00
|
|
|
for (Index = 0; Index < GpeLength; Index++)
|
2005-06-29 16:54:04 +00:00
|
|
|
{
|
2005-06-29 16:54:08 +00:00
|
|
|
OsdOut8 ((UINT16) (FACP->Gpe1Blk + Index), (UINT8) 0xff);
|
2005-06-29 16:54:04 +00:00
|
|
|
}
|
2005-06-29 16:54:01 +00:00
|
|
|
}
|
|
|
|
}
|