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Using android cpufeatures library for detection.

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This commit is contained in:
Armin Novak 2017-01-24 09:56:45 +01:00
parent ec06c24794
commit 0106405fff
8 changed files with 2088 additions and 125 deletions
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4
winpr/libwinpr/sysinfo/CMakeLists.txt
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@ -15,6 +15,10 @@
# See the License for the specific language governing permissions and
# limitations under the License.
if(ANDROID)
add_subdirectory(cpufeatures)
endif()
winpr_module_add(sysinfo.c)
if((NOT WIN32) AND (NOT APPLE) AND (NOT ANDROID) AND (NOT OPENBSD))

22
winpr/libwinpr/sysinfo/cpufeatures/Android.mk Normal file
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@ -0,0 +1,22 @@
LOCAL_PATH := $(call my-dir)
ifdef HISTORICAL_NDK_VERSIONS_ROOT
# This is included by the platform build system.
include $(CLEAR_VARS)
LOCAL_MODULE := cpufeatures
LOCAL_SRC_FILES := cpu-features.c
LOCAL_SDK_VERSION := 9
LOCAL_EXPORT_C_INCLUDE_DIRS := $(LOCAL_PATH)
include $(BUILD_STATIC_LIBRARY)
else # NDK build system
include $(CLEAR_VARS)
LOCAL_MODULE := cpufeatures
LOCAL_SRC_FILES := cpu-features.c
LOCAL_CFLAGS := -Wall -Wextra -Werror
LOCAL_EXPORT_C_INCLUDES := $(LOCAL_PATH)
LOCAL_EXPORT_LDLIBS := -ldl
include $(BUILD_STATIC_LIBRARY)
endif # HISTORICAL_NDK_VERSIONS_ROOT

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winpr/libwinpr/sysinfo/cpufeatures/CMakeLists.txt Normal file
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@ -0,0 +1,20 @@
# WinPR: Windows Portable Runtime
# libwinpr-sysinfo cmake build script
#
# Copyright 2017 Armin Novak <armin.novak@thincast.com>
# Copyright 2017 Thincast Technologies GmbH
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.
winpr_module_add(cpu-features.c cpu-features.h)

13
winpr/libwinpr/sysinfo/cpufeatures/NOTICE Normal file
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@ -0,0 +1,13 @@
Copyright (C) 2016 The Android Open Source Project
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.

1472
winpr/libwinpr/sysinfo/cpufeatures/cpu-features.c Normal file
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328
winpr/libwinpr/sysinfo/cpufeatures/cpu-features.h Normal file
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@ -0,0 +1,328 @@
/*
* Copyright (C) 2010 The Android Open Source Project
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
#ifndef CPU_FEATURES_H
#define CPU_FEATURES_H
#include <sys/cdefs.h>
#include <stdint.h>
__BEGIN_DECLS
/* A list of valid values returned by android_getCpuFamily().
* They describe the CPU Architecture of the current process.
*/
typedef enum
{
ANDROID_CPU_FAMILY_UNKNOWN = 0,
ANDROID_CPU_FAMILY_ARM,
ANDROID_CPU_FAMILY_X86,
ANDROID_CPU_FAMILY_MIPS,
ANDROID_CPU_FAMILY_ARM64,
ANDROID_CPU_FAMILY_X86_64,
ANDROID_CPU_FAMILY_MIPS64,
ANDROID_CPU_FAMILY_MAX /* do not remove */
} AndroidCpuFamily;
/* Return the CPU family of the current process.
*
* Note that this matches the bitness of the current process. I.e. when
* running a 32-bit binary on a 64-bit capable CPU, this will return the
* 32-bit CPU family value.
*/
extern AndroidCpuFamily android_getCpuFamily(void);
/* Return a bitmap describing a set of optional CPU features that are
* supported by the current device's CPU. The exact bit-flags returned
* depend on the value returned by android_getCpuFamily(). See the
* documentation for the ANDROID_CPU_*_FEATURE_* flags below for details.
*/
extern uint64_t android_getCpuFeatures(void);
/* The list of feature flags for ANDROID_CPU_FAMILY_ARM that can be
* recognized by the library (see note below for 64-bit ARM). Value details
* are:
*
* VFPv2:
* CPU supports the VFPv2 instruction set. Many, but not all, ARMv6 CPUs
* support these instructions. VFPv2 is a subset of VFPv3 so this will
* be set whenever VFPv3 is set too.
*
* ARMv7:
* CPU supports the ARMv7-A basic instruction set.
* This feature is mandated by the 'armeabi-v7a' ABI.
*
* VFPv3:
* CPU supports the VFPv3-D16 instruction set, providing hardware FPU
* support for single and double precision floating point registers.
* Note that only 16 FPU registers are available by default, unless
* the D32 bit is set too. This feature is also mandated by the
* 'armeabi-v7a' ABI.
*
* VFP_D32:
* CPU VFP optional extension that provides 32 FPU registers,
* instead of 16. Note that ARM mandates this feature is the 'NEON'
* feature is implemented by the CPU.
*
* NEON:
* CPU FPU supports "ARM Advanced SIMD" instructions, also known as
* NEON. Note that this mandates the VFP_D32 feature as well, per the
* ARM Architecture specification.
*
* VFP_FP16:
* Half-width floating precision VFP extension. If set, the CPU
* supports instructions to perform floating-point operations on
* 16-bit registers. This is part of the VFPv4 specification, but
* not mandated by any Android ABI.
*
* VFP_FMA:
* Fused multiply-accumulate VFP instructions extension. Also part of
* the VFPv4 specification, but not mandated by any Android ABI.
*
* NEON_FMA:
* Fused multiply-accumulate NEON instructions extension. Optional
* extension from the VFPv4 specification, but not mandated by any
* Android ABI.
*
* IDIV_ARM:
* Integer division available in ARM mode. Only available
* on recent CPUs (e.g. Cortex-A15).
*
* IDIV_THUMB2:
* Integer division available in Thumb-2 mode. Only available
* on recent CPUs (e.g. Cortex-A15).
*
* iWMMXt:
* Optional extension that adds MMX registers and operations to an
* ARM CPU. This is only available on a few XScale-based CPU designs
* sold by Marvell. Pretty rare in practice.
*
* AES:
* CPU supports AES instructions. These instructions are only
* available for 32-bit applications running on ARMv8 CPU.
*
* CRC32:
* CPU supports CRC32 instructions. These instructions are only
* available for 32-bit applications running on ARMv8 CPU.
*
* SHA2:
* CPU supports SHA2 instructions. These instructions are only
* available for 32-bit applications running on ARMv8 CPU.
*
* SHA1:
* CPU supports SHA1 instructions. These instructions are only
* available for 32-bit applications running on ARMv8 CPU.
*
* PMULL:
* CPU supports 64-bit PMULL and PMULL2 instructions. These
* instructions are only available for 32-bit applications
* running on ARMv8 CPU.
*
* If you want to tell the compiler to generate code that targets one of
* the feature set above, you should probably use one of the following
* flags (for more details, see technical note at the end of this file):
*
* -mfpu=vfp
* -mfpu=vfpv2
* These are equivalent and tell GCC to use VFPv2 instructions for
* floating-point operations. Use this if you want your code to
* run on *some* ARMv6 devices, and any ARMv7-A device supported
* by Android.
*
* Generated code requires VFPv2 feature.
*
* -mfpu=vfpv3-d16
* Tell GCC to use VFPv3 instructions (using only 16 FPU registers).
* This should be generic code that runs on any CPU that supports the
* 'armeabi-v7a' Android ABI. Note that no ARMv6 CPU supports this.
*
* Generated code requires VFPv3 feature.
*
* -mfpu=vfpv3
* Tell GCC to use VFPv3 instructions with 32 FPU registers.
* Generated code requires VFPv3|VFP_D32 features.
*
* -mfpu=neon
* Tell GCC to use VFPv3 instructions with 32 FPU registers, and
* also support NEON intrinsics (see <arm_neon.h>).
* Generated code requires VFPv3|VFP_D32|NEON features.
*
* -mfpu=vfpv4-d16
* Generated code requires VFPv3|VFP_FP16|VFP_FMA features.
*
* -mfpu=vfpv4
* Generated code requires VFPv3|VFP_FP16|VFP_FMA|VFP_D32 features.
*
* -mfpu=neon-vfpv4
* Generated code requires VFPv3|VFP_FP16|VFP_FMA|VFP_D32|NEON|NEON_FMA
* features.
*
* -mcpu=cortex-a7
* -mcpu=cortex-a15
* Generated code requires VFPv3|VFP_FP16|VFP_FMA|VFP_D32|
* NEON|NEON_FMA|IDIV_ARM|IDIV_THUMB2
* This flag implies -mfpu=neon-vfpv4.
*
* -mcpu=iwmmxt
* Allows the use of iWMMXt instrinsics with GCC.
*
* IMPORTANT NOTE: These flags should only be tested when
* android_getCpuFamily() returns ANDROID_CPU_FAMILY_ARM, i.e. this is a
* 32-bit process.
*
* When running a 64-bit ARM process on an ARMv8 CPU,
* android_getCpuFeatures() will return a different set of bitflags
*/
enum
{
ANDROID_CPU_ARM_FEATURE_ARMv7 = (1 << 0),
ANDROID_CPU_ARM_FEATURE_VFPv3 = (1 << 1),
ANDROID_CPU_ARM_FEATURE_NEON = (1 << 2),
ANDROID_CPU_ARM_FEATURE_LDREX_STREX = (1 << 3),
ANDROID_CPU_ARM_FEATURE_VFPv2 = (1 << 4),
ANDROID_CPU_ARM_FEATURE_VFP_D32 = (1 << 5),
ANDROID_CPU_ARM_FEATURE_VFP_FP16 = (1 << 6),
ANDROID_CPU_ARM_FEATURE_VFP_FMA = (1 << 7),
ANDROID_CPU_ARM_FEATURE_NEON_FMA = (1 << 8),
ANDROID_CPU_ARM_FEATURE_IDIV_ARM = (1 << 9),
ANDROID_CPU_ARM_FEATURE_IDIV_THUMB2 = (1 << 10),
ANDROID_CPU_ARM_FEATURE_iWMMXt = (1 << 11),
ANDROID_CPU_ARM_FEATURE_AES = (1 << 12),
ANDROID_CPU_ARM_FEATURE_PMULL = (1 << 13),
ANDROID_CPU_ARM_FEATURE_SHA1 = (1 << 14),
ANDROID_CPU_ARM_FEATURE_SHA2 = (1 << 15),
ANDROID_CPU_ARM_FEATURE_CRC32 = (1 << 16),
};
/* The bit flags corresponding to the output of android_getCpuFeatures()
* when android_getCpuFamily() returns ANDROID_CPU_FAMILY_ARM64. Value details
* are:
*
* FP:
* CPU has Floating-point unit.
*
* ASIMD:
* CPU has Advanced SIMD unit.
*
* AES:
* CPU supports AES instructions.
*
* CRC32:
* CPU supports CRC32 instructions.
*
* SHA2:
* CPU supports SHA2 instructions.
*
* SHA1:
* CPU supports SHA1 instructions.
*
* PMULL:
* CPU supports 64-bit PMULL and PMULL2 instructions.
*/
enum
{
ANDROID_CPU_ARM64_FEATURE_FP = (1 << 0),
ANDROID_CPU_ARM64_FEATURE_ASIMD = (1 << 1),
ANDROID_CPU_ARM64_FEATURE_AES = (1 << 2),
ANDROID_CPU_ARM64_FEATURE_PMULL = (1 << 3),
ANDROID_CPU_ARM64_FEATURE_SHA1 = (1 << 4),
ANDROID_CPU_ARM64_FEATURE_SHA2 = (1 << 5),
ANDROID_CPU_ARM64_FEATURE_CRC32 = (1 << 6),
};
/* The bit flags corresponding to the output of android_getCpuFeatures()
* when android_getCpuFamily() returns ANDROID_CPU_FAMILY_X86 or
* ANDROID_CPU_FAMILY_X86_64.
*/
enum
{
ANDROID_CPU_X86_FEATURE_SSSE3 = (1 << 0),
ANDROID_CPU_X86_FEATURE_POPCNT = (1 << 1),
ANDROID_CPU_X86_FEATURE_MOVBE = (1 << 2),
ANDROID_CPU_X86_FEATURE_SSE4_1 = (1 << 3),
ANDROID_CPU_X86_FEATURE_SSE4_2 = (1 << 4),
ANDROID_CPU_X86_FEATURE_AES_NI = (1 << 5),
ANDROID_CPU_X86_FEATURE_AVX = (1 << 6),
ANDROID_CPU_X86_FEATURE_RDRAND = (1 << 7),
ANDROID_CPU_X86_FEATURE_AVX2 = (1 << 8),
ANDROID_CPU_X86_FEATURE_SHA_NI = (1 << 9),
};
/* The bit flags corresponding to the output of android_getCpuFeatures()
* when android_getCpuFamily() returns ANDROID_CPU_FAMILY_MIPS
* or ANDROID_CPU_FAMILY_MIPS64. Values are:
*
* R6:
* CPU executes MIPS Release 6 instructions natively, and
* supports obsoleted R1..R5 instructions only via kernel traps.
*
* MSA:
* CPU supports Mips SIMD Architecture instructions.
*/
enum
{
ANDROID_CPU_MIPS_FEATURE_R6 = (1 << 0),
ANDROID_CPU_MIPS_FEATURE_MSA = (1 << 1),
};
/* Return the number of CPU cores detected on this device. */
extern int android_getCpuCount(void);
/* The following is used to force the CPU count and features
* mask in sandboxed processes. Under 4.1 and higher, these processes
* cannot access /proc, which is the only way to get information from
* the kernel about the current hardware (at least on ARM).
*
* It _must_ be called only once, and before any android_getCpuXXX
* function, any other case will fail.
*
* This function return 1 on success, and 0 on failure.
*/
extern int android_setCpu(int cpu_count,
uint64_t cpu_features);
#ifdef __arm__
/* Retrieve the ARM 32-bit CPUID value from the kernel.
* Note that this cannot work on sandboxed processes under 4.1 and
* higher, unless you called android_setCpuArm() before.
*/
extern uint32_t android_getCpuIdArm(void);
/* An ARM-specific variant of android_setCpu() that also allows you
* to set the ARM CPUID field.
*/
extern int android_setCpuArm(int cpu_count,
uint64_t cpu_features,
uint32_t cpu_id);
#endif
__END_DECLS
#endif /* CPU_FEATURES_H */

55
winpr/libwinpr/sysinfo/cpufeatures/repo.prop Normal file
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@ -0,0 +1,55 @@
platform/bionic ed9e6a41c92c9552be84ecc126e29b4604eee246
platform/development 33b95fc1d131d4b07a67d14dce776217f4c36d9a
platform/external/googletest 013ee6fccb6bb9ebd6215b504f0eef45dccfde4e
platform/external/libcxx 45e09a55b249d0d97942702c26850e4b3c424b92
platform/external/libcxxabi 9711d72e91f48830db3f4e8133d1e2e328e8504c
platform/external/libunwind_llvm fecc6f26cfdbfc9cf0ea2021629ac6e85b7c0113
platform/external/llvm c62dc90488ad1807fab24cb56f98fb88585c08a2
platform/external/shaderc/glslang 59ebccccee399c0577230aeb608259fa71d7b1b7
platform/external/shaderc/shaderc fcd85bc9ec80390d39d204360d2c36a6423146f0
platform/external/shaderc/spirv-headers 9bec171dc9ffda91c2291102c04d75b10bf01e8a
platform/external/shaderc/spirv-tools 410cd1fca9703990880d4ddc53bb0b367889b173
platform/external/vulkan-validation-layers cbc75f522adb1f0cc3d86caae467faccce840b04
platform/manifest c421db3ebcf25f0642b4032118d4a2754f6f457c
platform/ndk d982fe4778a3d7d00c4df53502d630c808f025a3
platform/prebuilts/clang/host/darwin-x86 e60e8d81fb820b988728ea5b2ab6c8f34bc2d978
platform/prebuilts/clang/host/linux-x86 860bed8090d2d47e5646b34ef2ed7e756d222bc4
platform/prebuilts/clang/host/windows-x86 90efd850fcd95bfdd9945e4c0e90e4cb396d2a6c
platform/prebuilts/cmake/darwin-x86 289589930105f9db21313bfd5aaa4a5fe02509e5
platform/prebuilts/cmake/linux-x86 ee96b2ec399702e23faee15863fed3ae33144fdd
platform/prebuilts/gcc/darwin-x86/aarch64/aarch64-linux-android-4.9 51fa77f10f8c5ee658bfaf3e5a2a29ebd8de50d2
platform/prebuilts/gcc/darwin-x86/arm/arm-eabi-4.8 6d08ca9f45ff685648fd13c75bf5cac4b11c19bb
platform/prebuilts/gcc/darwin-x86/arm/arm-linux-androideabi-4.9 39fd9577fe3895a68a921216836ebdd46b4255a8
platform/prebuilts/gcc/darwin-x86/host/headers 4ac4f7cc41cf3c9e36fc3d6cf37fd1cfa9587a68
platform/prebuilts/gcc/darwin-x86/host/i686-apple-darwin-4.2.1 ec5aa66aaa4964c27564d0ec84dc1f18a2d72b7e
platform/prebuilts/gcc/darwin-x86/mips/mips64el-linux-android-4.9 4ba48d4ace63404304f201dc7d5e87ac55fc7d59
platform/prebuilts/gcc/darwin-x86/x86/x86_64-linux-android-4.9 2500bd9aaa640c179730df7f7315d5ee90e4c3c1
platform/prebuilts/gcc/linux-x86/aarch64/aarch64-linux-android-4.9 423c0265176bcabd1c885f8cf6f0cedf67d3f59b
platform/prebuilts/gcc/linux-x86/arm/arm-eabi-4.8 26e93f6af47f7bd3a9beb5c102a5f45e19bfa38a
platform/prebuilts/gcc/linux-x86/arm/arm-linux-androideabi-4.9 887574f98e97475d6fb2f91a8f7b24602466017a
platform/prebuilts/gcc/linux-x86/host/x86_64-linux-glibc2.11-4.8 1273431a189717842f033573eb8c777e13dd88b7
platform/prebuilts/gcc/linux-x86/host/x86_64-linux-glibc2.15-4.8 73ca99196723f810dad42390d154654354f57c16
platform/prebuilts/gcc/linux-x86/host/x86_64-w64-mingw32-4.8 c795eed743bc6cee4ead5407cc237c43abf6fa26
platform/prebuilts/gcc/linux-x86/mips/mips64el-linux-android-4.9 88bfecab5b700a1f6a601434d5816fab6c9261fc
platform/prebuilts/gcc/linux-x86/x86/x86_64-linux-android-4.9 e3b93a8f44d43101b396d41ef30562885714e130
platform/prebuilts/ndk adc9927c0f3f5107a777a67b94a4b1f447255681
platform/prebuilts/ninja/darwin-x86 cc147ae2956e96279085abfadda2767b50edc2cc
platform/prebuilts/ninja/linux-x86 543112c6744acb7a018ac36118eb2a862834809b
platform/prebuilts/python/darwin-x86/2.7.5 0c5958b1636c47ed7c284f859c8e805fd06a0e63
platform/prebuilts/python/linux-x86/2.7.5 ce294655f981e19b420f2201b7c499a435ef1ce2
platform/prebuilts/simpleperf 7323ef4840428a32b6e9d8b58fcce87e05295b05
toolchain/binutils 6422a80df992e4542dbd4fb70a04f316065674af
toolchain/build f280657461aee54b6d2807881d8a77832f4e794c
toolchain/cloog 604793eab97d360aef729f064674569ee6dbf3e1
toolchain/expat 40172a0ae9d40a068f1e1a48ffcf6a1ccf765ed5
toolchain/gcc 535de7eb0179bdcd01fcd99f1dad6208250d3706
toolchain/gdb b66267cc5491513a9ad0369761a1c1b52bf15fed
toolchain/gmp b2acd5dbf47868ac5b5bc844e16d2cadcbd4c810
toolchain/isl 0ccf95726af8ce58ad61ff474addbce3a31ba99c
toolchain/mpc 835d16e92eed875638a8b5d552034c3b1aae045b
toolchain/mpfr de979fc377db766591e7feaf052f0de59be46e76
toolchain/ppl 979062d362bc5a1c00804237b408b19b4618fb24
toolchain/python 6a7fc9bfd21da85dda97a8bcd2952e0bfbded424
toolchain/sed 45df23d6dc8b51ea5cd903d023c10fd7d72415b9
toolchain/xz 595407f5a237e9bfd6821d70096d38825ec9c4e0
toolchain/yasm a159fe073809b4138cf90b7298ea31ea17af85c0

299
winpr/libwinpr/sysinfo/sysinfo.c
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@ -25,7 +25,11 @@
#include <winpr/sysinfo.h>
#include <winpr/platform.h>
#if defined(__linux__) && defined(__GNUC__)
#if defined(ANDROID)
#include "cpufeatures/cpu-features.h"
#endif
#if defined(__linux__)
#include <sys/types.h>
#include <sys/stat.h>
#include <fcntl.h>
@ -75,7 +79,34 @@ defined(__OpenBSD__) || defined(__DragonFly__)
static DWORD GetProcessorArchitecture(void)
{
DWORD cpuArch = PROCESSOR_ARCHITECTURE_UNKNOWN;
#if defined(_M_ARM)
#if defined(ANDROID)
AndroidCpuFamily family = android_getCpuFamily();
switch (family)
{
case ANDROID_CPU_FAMILY_ARM:
return PROCESSOR_ARCHITECTURE_ARM;
case ANDROID_CPU_FAMILY_X86:
return PROCESSOR_ARCHITECTURE_INTEL;
case ANDROID_CPU_FAMILY_MIPS:
return PROCESSOR_ARCHITECTURE_MIPS;
case ANDROID_CPU_FAMILY_ARM64:
return PROCESSOR_ARCHITECTURE_ARM64;
case ANDROID_CPU_FAMILY_X86_64:
return PROCESSOR_ARCHITECTURE_AMD64;
case ANDROID_CPU_FAMILY_MIPS64:
return PROCESSOR_ARCHITECTURE_MIPS64;
default:
return PROCESSOR_ARCHITECTURE_UNKNOWN;
}
#elif defined(_M_ARM)
cpuArch = PROCESSOR_ARCHITECTURE_ARM;
#elif defined(_M_IX86)
cpuArch = PROCESSOR_ARCHITECTURE_INTEL;
@ -99,8 +130,10 @@ static DWORD GetProcessorArchitecture(void)
static DWORD GetNumberOfProcessors(void)
{
DWORD numCPUs = 1;
#if defined(ANDROID)
return android_getCpuCount();
/* TODO: iOS */
#if defined(__linux__) || defined(__sun) || defined(_AIX)
#elif defined(__linux__) || defined(__sun) || defined(_AIX)
numCPUs = (DWORD) sysconf(_SC_NPROCESSORS_ONLN);
#elif defined(__MACOSX__) || \
defined(__FreeBSD__) || defined(__NetBSD__) || \
@ -204,6 +237,7 @@ void GetSystemTime(LPSYSTEMTIME lpSystemTime)
BOOL SetSystemTime(CONST SYSTEMTIME* lpSystemTime)
{
/* TODO: Implement */
return FALSE;
}
@ -232,6 +266,7 @@ VOID GetLocalTime(LPSYSTEMTIME lpSystemTime)
BOOL SetLocalTime(CONST SYSTEMTIME* lpSystemTime)
{
/* TODO: Implement */
return FALSE;
}
@ -249,6 +284,7 @@ VOID GetSystemTimeAsFileTime(LPFILETIME lpSystemTimeAsFileTime)
BOOL GetSystemTimeAdjustment(PDWORD lpTimeAdjustment, PDWORD lpTimeIncrement,
PBOOL lpTimeAdjustmentDisabled)
{
/* TODO: Implement */
return FALSE;
}
@ -398,13 +434,13 @@ BOOL GetComputerNameExA(COMPUTER_NAME_FORMAT NameType, LPSTR lpBuffer, LPDWORD l
switch (NameType)
{
case ComputerNameDnsHostname:
case ComputerNameDnsDomain:
case ComputerNameDnsFullyQualified:
case ComputerNamePhysicalDnsHostname:
case ComputerNamePhysicalDnsDomain:
case ComputerNamePhysicalDnsFullyQualified:
if (*lpnSize <= (DWORD) length)
case ComputerNameDnsHostname:
case ComputerNameDnsDomain:
case ComputerNameDnsFullyQualified:
case ComputerNamePhysicalDnsHostname:
case ComputerNamePhysicalDnsDomain:
case ComputerNamePhysicalDnsFullyQualified:
if (*lpnSize <= (DWORD) length)
{
*lpnSize = length + 1;
SetLastError(ERROR_MORE_DATA);
@ -416,10 +452,10 @@ BOOL GetComputerNameExA(COMPUTER_NAME_FORMAT NameType, LPSTR lpBuffer, LPDWORD l
CopyMemory(lpBuffer, hostname, length);
lpBuffer[length] = '\0';
break;
break;
default:
return FALSE;
default:
return FALSE;
}
return TRUE;
@ -512,8 +548,8 @@ static void cpuid(
__asm volatile
(
/* The EBX (or RBX register on x86_64) is used for the PIC base address
* and must not be corrupted by our inline assembly.
*/
* and must not be corrupted by our inline assembly.
*/
#ifdef _M_IX86
"mov %%ebx, %%esi;"
"cpuid;"
@ -603,85 +639,98 @@ static unsigned GetARMCPUCaps(void)
BOOL IsProcessorFeaturePresent(DWORD ProcessorFeature)
{
BOOL ret = FALSE;
#ifdef _M_ARM
#if defined(ANDROID)
const uint64_t features = android_getCpuFeatures();
switch (ProcessorFeature)
{
case PF_ARM_NEON_INSTRUCTIONS_AVAILABLE:
case PF_ARM_NEON:
return features & ANDROID_CPU_ARM_FEATURE_NEON;
default:
return FALSE;
}
#elif defined(_M_ARM)
#ifdef __linux__
const unsigned caps = GetARMCPUCaps();
switch (ProcessorFeature)
{
case PF_ARM_NEON_INSTRUCTIONS_AVAILABLE:
case PF_ARM_NEON:
if (caps & HWCAP_NEON)
case PF_ARM_NEON_INSTRUCTIONS_AVAILABLE:
case PF_ARM_NEON:
if (caps & HWCAP_NEON)
ret = TRUE;
break;
break;
case PF_ARM_THUMB:
if (caps & HWCAP_THUMB)
case PF_ARM_THUMB:
if (caps & HWCAP_THUMB)
ret = TRUE;
case PF_ARM_VFP_32_REGISTERS_AVAILABLE:
if (caps & HWCAP_VFPD32)
case PF_ARM_VFP_32_REGISTERS_AVAILABLE:
if (caps & HWCAP_VFPD32)
ret = TRUE;
case PF_ARM_DIVIDE_INSTRUCTION_AVAILABLE:
if ((caps & HWCAP_IDIVA) || (caps & HWCAP_IDIVT))
case PF_ARM_DIVIDE_INSTRUCTION_AVAILABLE:
if ((caps & HWCAP_IDIVA) || (caps & HWCAP_IDIVT))
ret = TRUE;
case PF_ARM_VFP3:
if (caps & HWCAP_VFPv3)
case PF_ARM_VFP3:
if (caps & HWCAP_VFPv3)
ret = TRUE;
break;
break;
case PF_ARM_JAZELLE:
if (caps & HWCAP_JAVA)
case PF_ARM_JAZELLE:
if (caps & HWCAP_JAVA)
ret = TRUE;
break;
break;
case PF_ARM_DSP:
if (caps & HWCAP_EDSP)
case PF_ARM_DSP:
if (caps & HWCAP_EDSP)
ret = TRUE;
break;
break;
case PF_ARM_MPU:
if (caps & HWCAP_EDSP)
case PF_ARM_MPU:
if (caps & HWCAP_EDSP)
ret = TRUE;
break;
break;
case PF_ARM_THUMB2:
if ((caps & HWCAP_IDIVT) || (caps & HWCAP_VFPv4))
case PF_ARM_THUMB2:
if ((caps & HWCAP_IDIVT) || (caps & HWCAP_VFPv4))
ret = TRUE;
break;
break;
case PF_ARM_T2EE:
if (caps & HWCAP_THUMBEE)
case PF_ARM_T2EE:
if (caps & HWCAP_THUMBEE)
ret = TRUE;
break;
break;
case PF_ARM_INTEL_WMMX:
if (caps & HWCAP_IWMMXT)
case PF_ARM_INTEL_WMMX:
if (caps & HWCAP_IWMMXT)
ret = TRUE;
break;
break;
default:
break;
default:
break;
}
#elif defined(__APPLE__) // __linux__
switch (ProcessorFeature)
{
case PF_ARM_NEON_INSTRUCTIONS_AVAILABLE:
case PF_ARM_NEON:
ret = TRUE;
break;
case PF_ARM_NEON_INSTRUCTIONS_AVAILABLE:
case PF_ARM_NEON:
ret = TRUE;
break;
}
#endif // __linux__
@ -692,38 +741,38 @@ BOOL IsProcessorFeaturePresent(DWORD ProcessorFeature)
switch (ProcessorFeature)
{
case PF_MMX_INSTRUCTIONS_AVAILABLE:
if (d & D_BIT_MMX)
case PF_MMX_INSTRUCTIONS_AVAILABLE:
if (d & D_BIT_MMX)
ret = TRUE;
break;
break;
case PF_XMMI_INSTRUCTIONS_AVAILABLE:
if (d & D_BIT_SSE)
case PF_XMMI_INSTRUCTIONS_AVAILABLE:
if (d & D_BIT_SSE)
ret = TRUE;
break;
break;
case PF_XMMI64_INSTRUCTIONS_AVAILABLE:
if (d & D_BIT_SSE2)
case PF_XMMI64_INSTRUCTIONS_AVAILABLE:
if (d & D_BIT_SSE2)
ret = TRUE;
break;
break;
case PF_3DNOW_INSTRUCTIONS_AVAILABLE:
if (d & D_BIT_3DN)
case PF_3DNOW_INSTRUCTIONS_AVAILABLE:
if (d & D_BIT_3DN)
ret = TRUE;
break;
break;
case PF_SSE3_INSTRUCTIONS_AVAILABLE:
if (c & C_BIT_SSE3)
case PF_SSE3_INSTRUCTIONS_AVAILABLE:
if (c & C_BIT_SSE3)
ret = TRUE;
break;
break;
default:
break;
default:
break;
}
#endif // __GNUC__
@ -756,35 +805,35 @@ BOOL IsProcessorFeaturePresentEx(DWORD ProcessorFeature)
switch (ProcessorFeature)
{
case PF_EX_ARM_VFP1:
if (caps & HWCAP_VFP)
case PF_EX_ARM_VFP1:
if (caps & HWCAP_VFP)
ret = TRUE;
break;
break;
case PF_EX_ARM_VFP3D16:
if (caps & HWCAP_VFPv3D16)
case PF_EX_ARM_VFP3D16:
if (caps & HWCAP_VFPv3D16)
ret = TRUE;
break;
break;
case PF_EX_ARM_VFP4:
if (caps & HWCAP_VFPv4)
case PF_EX_ARM_VFP4:
if (caps & HWCAP_VFPv4)
ret = TRUE;
break;
break;
case PF_EX_ARM_IDIVA:
if (caps & HWCAP_IDIVA)
case PF_EX_ARM_IDIVA:
if (caps & HWCAP_IDIVA)
ret = TRUE;
break;
break;
case PF_EX_ARM_IDIVT:
if (caps & HWCAP_IDIVT)
case PF_EX_ARM_IDIVT:
if (caps & HWCAP_IDIVT)
ret = TRUE;
break;
break;
}
#endif // __linux__
@ -794,48 +843,48 @@ BOOL IsProcessorFeaturePresentEx(DWORD ProcessorFeature)
switch (ProcessorFeature)
{
case PF_EX_LZCNT:
{
unsigned a81, b81, c81, d81;
case PF_EX_LZCNT:
{
unsigned a81, b81, c81, d81;
cpuid(0x80000001, &a81, &b81, &c81, &d81);
if (c81 & C81_BIT_LZCNT)
ret = TRUE;
}
break;
}
break;
case PF_EX_3DNOW_PREFETCH:
if (c & C_BIT_3DNP)
case PF_EX_3DNOW_PREFETCH:
if (c & C_BIT_3DNP)
ret = TRUE;
break;
break;
case PF_EX_SSSE3:
if (c & C_BIT_SSSE3)
case PF_EX_SSSE3:
if (c & C_BIT_SSSE3)
ret = TRUE;
break;
break;
case PF_EX_SSE41:
if (c & C_BIT_SSE41)
case PF_EX_SSE41:
if (c & C_BIT_SSE41)
ret = TRUE;
break;
break;
case PF_EX_SSE42:
if (c & C_BIT_SSE42)
case PF_EX_SSE42:
if (c & C_BIT_SSE42)
ret = TRUE;
break;
break;
#if defined(__GNUC__) && defined(__AVX__)
case PF_EX_AVX:
case PF_EX_FMA:
case PF_EX_AVX_AES:
case PF_EX_AVX_PCLMULQDQ:
{
/* Check for general AVX support */
if ((c & C_BITS_AVX) != C_BITS_AVX)
case PF_EX_AVX:
case PF_EX_FMA:
case PF_EX_AVX_AES:
case PF_EX_AVX_PCLMULQDQ:
{
/* Check for general AVX support */
if ((c & C_BITS_AVX) != C_BITS_AVX)
break;
int e, f;
@ -846,35 +895,35 @@ BOOL IsProcessorFeaturePresentEx(DWORD ProcessorFeature)
{
switch (ProcessorFeature)
{
case PF_EX_AVX:
ret = TRUE;
break;
case PF_EX_AVX:
ret = TRUE;
break;
case PF_EX_FMA:
if (c & C_BIT_FMA)
case PF_EX_FMA:
if (c & C_BIT_FMA)
ret = TRUE;
break;
break;
case PF_EX_AVX_AES:
if (c & C_BIT_AES)
case PF_EX_AVX_AES:
if (c & C_BIT_AES)
ret = TRUE;
break;
break;
case PF_EX_AVX_PCLMULQDQ:
if (c & C_BIT_PCLMULQDQ)
case PF_EX_AVX_PCLMULQDQ:
if (c & C_BIT_PCLMULQDQ)
ret = TRUE;
break;
break;
}
}
}
break;
}
break;
#endif //__AVX__
default:
break;
default:
break;
}
#endif