2013-01-19 02:32:58 +04:00
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/* prim_templates.h
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* vi:ts=4 sw=4
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*
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* (c) Copyright 2012 Hewlett-Packard Development Company, L.P.
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* Licensed under the Apache License, Version 2.0 (the "License"); you may
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* not use this file except in compliance with the License. You may obtain
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* a copy of the License at http://www.apache.org/licenses/LICENSE-2.0.
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express
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* or implied. See the License for the specific language governing
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* permissions and limitations under the License. Algorithms used by
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* this code may be covered by patents by HP, Microsoft, or other parties.
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*/
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#ifdef __GNUC__
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2019-11-06 17:24:51 +03:00
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#pragma once
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2013-01-19 02:32:58 +04:00
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#endif
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2017-06-06 15:01:41 +03:00
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#ifndef FREERDP_LIB_PRIM_TEMPLATES_H
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#define FREERDP_LIB_PRIM_TEMPLATES_H
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2013-01-19 02:32:58 +04:00
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2016-04-05 18:07:45 +03:00
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/* These are prototypes for SSE (potentially NEON) routines that do a
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2013-01-19 02:32:58 +04:00
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* simple SSE operation over an array of data. Since so much of this
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* code is shared except for the operation itself, these prototypes are
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* used rather than duplicating code. The naming convention depends on
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* the parameters: S=Source param; C=Constant; D=Destination.
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* All the macros have parameters for a fallback procedure if the data
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* is too small and an operation "the slow way" for use at 16-byte edges.
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*/
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/* SSE3 note: If someone needs to support an SSE2 version of these without
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* SSE3 support, an alternative version could be added that merely checks
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2016-04-05 18:07:45 +03:00
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* that 16-byte alignment on both destination and source(s) can be
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2013-01-19 02:32:58 +04:00
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* achieved, rather than use LDDQU for unaligned reads.
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*/
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/* Note: the compiler is good at turning (16/sizeof(_type_)) into a constant.
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* It easily can't do that if the value is stored in a variable.
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* So don't save it as an intermediate value.
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*/
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/* ----------------------------------------------------------------------------
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* SCD = Source, Constant, Destination
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*/
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2019-11-06 17:24:51 +03:00
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#define SSE3_SCD_ROUTINE(_name_, _type_, _fallback_, _op_, _slowWay_) \
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static pstatus_t _name_(const _type_* pSrc, UINT32 val, _type_* pDst, UINT32 len) \
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{ \
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INT32 shifts = 0; \
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UINT32 offBeatMask; \
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const _type_* sptr = pSrc; \
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_type_* dptr = pDst; \
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2021-07-29 11:07:04 +03:00
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int count; \
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2020-05-15 17:04:28 +03:00
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if (val == 0) \
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return PRIMITIVES_SUCCESS; \
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if (val >= 16) \
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return -1; \
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2019-11-06 17:24:51 +03:00
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if (len < 16) /* pointless if too small */ \
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{ \
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return _fallback_(pSrc, val, pDst, len); \
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} \
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if (sizeof(_type_) == 1) \
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shifts = 1; \
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else if (sizeof(_type_) == 2) \
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shifts = 2; \
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else if (sizeof(_type_) == 4) \
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shifts = 3; \
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else if (sizeof(_type_) == 8) \
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shifts = 4; \
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offBeatMask = (1 << (shifts - 1)) - 1; \
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if ((ULONG_PTR)pDst & offBeatMask) \
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{ \
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/* Incrementing the pointer skips over 16-byte boundary. */ \
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return _fallback_(pSrc, val, pDst, len); \
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} \
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/* Get to the 16-byte boundary now. */ \
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while ((ULONG_PTR)dptr & 0x0f) \
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{ \
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_slowWay_; \
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if (--len == 0) \
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return PRIMITIVES_SUCCESS; \
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} \
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/* Use 8 128-bit SSE registers. */ \
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count = len >> (8 - shifts); \
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len -= count << (8 - shifts); \
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2021-08-02 13:13:34 +03:00
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if ((const ULONG_PTR)sptr & 0x0f) \
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2019-11-06 17:24:51 +03:00
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{ \
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while (count--) \
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{ \
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__m128i xmm0, xmm1, xmm2, xmm3, xmm4, xmm5, xmm6, xmm7; \
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2021-08-02 13:13:34 +03:00
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xmm0 = _mm_lddqu_si128((const __m128i*)sptr); \
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2019-11-06 17:24:51 +03:00
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sptr += (16 / sizeof(_type_)); \
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2021-08-02 13:13:34 +03:00
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xmm1 = _mm_lddqu_si128((const __m128i*)sptr); \
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2019-11-06 17:24:51 +03:00
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sptr += (16 / sizeof(_type_)); \
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2021-08-02 13:13:34 +03:00
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xmm2 = _mm_lddqu_si128((const __m128i*)sptr); \
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2019-11-06 17:24:51 +03:00
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sptr += (16 / sizeof(_type_)); \
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2021-08-02 13:13:34 +03:00
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xmm3 = _mm_lddqu_si128((const __m128i*)sptr); \
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2019-11-06 17:24:51 +03:00
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sptr += (16 / sizeof(_type_)); \
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2021-08-02 13:13:34 +03:00
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xmm4 = _mm_lddqu_si128((const __m128i*)sptr); \
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2019-11-06 17:24:51 +03:00
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sptr += (16 / sizeof(_type_)); \
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2021-08-02 13:13:34 +03:00
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xmm5 = _mm_lddqu_si128((const __m128i*)sptr); \
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2019-11-06 17:24:51 +03:00
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sptr += (16 / sizeof(_type_)); \
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2021-08-02 13:13:34 +03:00
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xmm6 = _mm_lddqu_si128((const __m128i*)sptr); \
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2019-11-06 17:24:51 +03:00
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sptr += (16 / sizeof(_type_)); \
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2021-08-02 13:13:34 +03:00
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xmm7 = _mm_lddqu_si128((const __m128i*)sptr); \
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2019-11-06 17:24:51 +03:00
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sptr += (16 / sizeof(_type_)); \
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xmm0 = _op_(xmm0, val); \
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xmm1 = _op_(xmm1, val); \
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xmm2 = _op_(xmm2, val); \
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xmm3 = _op_(xmm3, val); \
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xmm4 = _op_(xmm4, val); \
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xmm5 = _op_(xmm5, val); \
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xmm6 = _op_(xmm6, val); \
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xmm7 = _op_(xmm7, val); \
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_mm_store_si128((__m128i*)dptr, xmm0); \
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dptr += (16 / sizeof(_type_)); \
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_mm_store_si128((__m128i*)dptr, xmm1); \
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dptr += (16 / sizeof(_type_)); \
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_mm_store_si128((__m128i*)dptr, xmm2); \
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dptr += (16 / sizeof(_type_)); \
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_mm_store_si128((__m128i*)dptr, xmm3); \
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dptr += (16 / sizeof(_type_)); \
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_mm_store_si128((__m128i*)dptr, xmm4); \
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dptr += (16 / sizeof(_type_)); \
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_mm_store_si128((__m128i*)dptr, xmm5); \
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dptr += (16 / sizeof(_type_)); \
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_mm_store_si128((__m128i*)dptr, xmm6); \
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dptr += (16 / sizeof(_type_)); \
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_mm_store_si128((__m128i*)dptr, xmm7); \
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dptr += (16 / sizeof(_type_)); \
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} \
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} \
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else \
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{ \
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while (count--) \
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{ \
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__m128i xmm0, xmm1, xmm2, xmm3, xmm4, xmm5, xmm6, xmm7; \
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2021-08-02 13:13:34 +03:00
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xmm0 = _mm_load_si128((const __m128i*)sptr); \
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2019-11-06 17:24:51 +03:00
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sptr += (16 / sizeof(_type_)); \
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2021-08-02 13:13:34 +03:00
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xmm1 = _mm_load_si128((const __m128i*)sptr); \
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2019-11-06 17:24:51 +03:00
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sptr += (16 / sizeof(_type_)); \
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2021-08-02 13:13:34 +03:00
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xmm2 = _mm_load_si128((const __m128i*)sptr); \
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2019-11-06 17:24:51 +03:00
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sptr += (16 / sizeof(_type_)); \
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2021-08-02 13:13:34 +03:00
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xmm3 = _mm_load_si128((const __m128i*)sptr); \
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2019-11-06 17:24:51 +03:00
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sptr += (16 / sizeof(_type_)); \
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2021-08-02 13:13:34 +03:00
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xmm4 = _mm_load_si128((const __m128i*)sptr); \
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2019-11-06 17:24:51 +03:00
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sptr += (16 / sizeof(_type_)); \
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2021-08-02 13:13:34 +03:00
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xmm5 = _mm_load_si128((const __m128i*)sptr); \
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2019-11-06 17:24:51 +03:00
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sptr += (16 / sizeof(_type_)); \
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2021-08-02 13:13:34 +03:00
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xmm6 = _mm_load_si128((const __m128i*)sptr); \
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2019-11-06 17:24:51 +03:00
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sptr += (16 / sizeof(_type_)); \
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2021-08-02 13:13:34 +03:00
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xmm7 = _mm_load_si128((const __m128i*)sptr); \
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2019-11-06 17:24:51 +03:00
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sptr += (16 / sizeof(_type_)); \
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xmm0 = _op_(xmm0, val); \
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xmm1 = _op_(xmm1, val); \
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xmm2 = _op_(xmm2, val); \
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xmm3 = _op_(xmm3, val); \
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xmm4 = _op_(xmm4, val); \
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xmm5 = _op_(xmm5, val); \
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xmm6 = _op_(xmm6, val); \
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xmm7 = _op_(xmm7, val); \
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_mm_store_si128((__m128i*)dptr, xmm0); \
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dptr += (16 / sizeof(_type_)); \
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_mm_store_si128((__m128i*)dptr, xmm1); \
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dptr += (16 / sizeof(_type_)); \
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_mm_store_si128((__m128i*)dptr, xmm2); \
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dptr += (16 / sizeof(_type_)); \
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_mm_store_si128((__m128i*)dptr, xmm3); \
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dptr += (16 / sizeof(_type_)); \
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_mm_store_si128((__m128i*)dptr, xmm4); \
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dptr += (16 / sizeof(_type_)); \
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_mm_store_si128((__m128i*)dptr, xmm5); \
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dptr += (16 / sizeof(_type_)); \
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_mm_store_si128((__m128i*)dptr, xmm6); \
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dptr += (16 / sizeof(_type_)); \
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_mm_store_si128((__m128i*)dptr, xmm7); \
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dptr += (16 / sizeof(_type_)); \
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} \
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} \
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/* Use a single 128-bit SSE register. */ \
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count = len >> (5 - shifts); \
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len -= count << (5 - shifts); \
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while (count--) \
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{ \
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__m128i xmm0 = LOAD_SI128(sptr); \
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sptr += (16 / sizeof(_type_)); \
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xmm0 = _op_(xmm0, val); \
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_mm_store_si128((__m128i*)dptr, xmm0); \
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dptr += (16 / sizeof(_type_)); \
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} \
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/* Finish off the remainder. */ \
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while (len--) \
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{ \
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_slowWay_; \
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} \
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return PRIMITIVES_SUCCESS; \
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2016-04-05 18:07:45 +03:00
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}
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2013-01-19 02:32:58 +04:00
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/* ----------------------------------------------------------------------------
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* SCD = Source, Constant, Destination
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* PRE = preload xmm0 with the constant.
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*/
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2019-11-20 13:30:14 +03:00
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#define SSE3_SCD_PRE_ROUTINE(_name_, _type_, _fallback_, _op_, _slowWay_) \
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static pstatus_t _name_(const _type_* pSrc, _type_ val, _type_* pDst, INT32 len) \
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{ \
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int shifts = 0; \
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UINT32 offBeatMask; \
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const _type_* sptr = pSrc; \
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_type_* dptr = pDst; \
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size_t count; \
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__m128i xmm0; \
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if (len < 16) /* pointless if too small */ \
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{ \
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return _fallback_(pSrc, val, pDst, len); \
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} \
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if (sizeof(_type_) == 1) \
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shifts = 1; \
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else if (sizeof(_type_) == 2) \
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shifts = 2; \
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else if (sizeof(_type_) == 4) \
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shifts = 3; \
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else if (sizeof(_type_) == 8) \
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shifts = 4; \
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offBeatMask = (1 << (shifts - 1)) - 1; \
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if ((ULONG_PTR)pDst & offBeatMask) \
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{ \
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/* Incrementing the pointer skips over 16-byte boundary. */ \
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return _fallback_(pSrc, val, pDst, len); \
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} \
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/* Get to the 16-byte boundary now. */ \
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while ((ULONG_PTR)dptr & 0x0f) \
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{ \
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_slowWay_; \
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if (--len == 0) \
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return PRIMITIVES_SUCCESS; \
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} \
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/* Use 4 128-bit SSE registers. */ \
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count = len >> (7 - shifts); \
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len -= count << (7 - shifts); \
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xmm0 = _mm_set1_epi32(val); \
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2021-08-02 13:13:34 +03:00
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if ((const ULONG_PTR)sptr & 0x0f) \
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2019-11-20 13:30:14 +03:00
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{ \
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while (count--) \
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{ \
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__m128i xmm1, xmm2, xmm3, xmm4; \
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2021-08-02 13:13:34 +03:00
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xmm1 = _mm_lddqu_si128((const __m128i*)sptr); \
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2019-11-20 13:30:14 +03:00
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sptr += (16 / sizeof(_type_)); \
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2021-08-02 13:13:34 +03:00
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xmm2 = _mm_lddqu_si128((const __m128i*)sptr); \
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2019-11-20 13:30:14 +03:00
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sptr += (16 / sizeof(_type_)); \
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2021-08-02 13:13:34 +03:00
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xmm3 = _mm_lddqu_si128((const __m128i*)sptr); \
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2019-11-20 13:30:14 +03:00
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sptr += (16 / sizeof(_type_)); \
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2021-08-02 13:13:34 +03:00
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xmm4 = _mm_lddqu_si128((const __m128i*)sptr); \
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2019-11-20 13:30:14 +03:00
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sptr += (16 / sizeof(_type_)); \
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xmm1 = _op_(xmm1, xmm0); \
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xmm2 = _op_(xmm2, xmm0); \
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xmm3 = _op_(xmm3, xmm0); \
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xmm4 = _op_(xmm4, xmm0); \
|
|
|
|
|
_mm_store_si128((__m128i*)dptr, xmm1); \
|
|
|
|
|
dptr += (16 / sizeof(_type_)); \
|
|
|
|
|
_mm_store_si128((__m128i*)dptr, xmm2); \
|
|
|
|
|
dptr += (16 / sizeof(_type_)); \
|
|
|
|
|
_mm_store_si128((__m128i*)dptr, xmm3); \
|
|
|
|
|
dptr += (16 / sizeof(_type_)); \
|
|
|
|
|
_mm_store_si128((__m128i*)dptr, xmm4); \
|
|
|
|
|
dptr += (16 / sizeof(_type_)); \
|
|
|
|
|
} \
|
|
|
|
|
} \
|
|
|
|
|
else \
|
|
|
|
|
{ \
|
|
|
|
|
while (count--) \
|
|
|
|
|
{ \
|
|
|
|
|
__m128i xmm1, xmm2, xmm3, xmm4; \
|
2021-08-02 13:13:34 +03:00
|
|
|
xmm1 = _mm_load_si128((const __m128i*)sptr); \
|
2019-11-20 13:30:14 +03:00
|
|
|
sptr += (16 / sizeof(_type_)); \
|
2021-08-02 13:13:34 +03:00
|
|
|
xmm2 = _mm_load_si128((const __m128i*)sptr); \
|
2019-11-20 13:30:14 +03:00
|
|
|
sptr += (16 / sizeof(_type_)); \
|
2021-08-02 13:13:34 +03:00
|
|
|
xmm3 = _mm_load_si128((const __m128i*)sptr); \
|
2019-11-20 13:30:14 +03:00
|
|
|
sptr += (16 / sizeof(_type_)); \
|
2021-08-02 13:13:34 +03:00
|
|
|
xmm4 = _mm_load_si128((const __m128i*)sptr); \
|
2019-11-20 13:30:14 +03:00
|
|
|
sptr += (16 / sizeof(_type_)); \
|
|
|
|
|
xmm1 = _op_(xmm1, xmm0); \
|
|
|
|
|
xmm2 = _op_(xmm2, xmm0); \
|
|
|
|
|
xmm3 = _op_(xmm3, xmm0); \
|
|
|
|
|
xmm4 = _op_(xmm4, xmm0); \
|
|
|
|
|
_mm_store_si128((__m128i*)dptr, xmm1); \
|
|
|
|
|
dptr += (16 / sizeof(_type_)); \
|
|
|
|
|
_mm_store_si128((__m128i*)dptr, xmm2); \
|
|
|
|
|
dptr += (16 / sizeof(_type_)); \
|
|
|
|
|
_mm_store_si128((__m128i*)dptr, xmm3); \
|
|
|
|
|
dptr += (16 / sizeof(_type_)); \
|
|
|
|
|
_mm_store_si128((__m128i*)dptr, xmm4); \
|
|
|
|
|
dptr += (16 / sizeof(_type_)); \
|
|
|
|
|
} \
|
|
|
|
|
} \
|
|
|
|
|
/* Use a single 128-bit SSE register. */ \
|
|
|
|
|
count = len >> (5 - shifts); \
|
|
|
|
|
len -= count << (5 - shifts); \
|
|
|
|
|
while (count--) \
|
|
|
|
|
{ \
|
|
|
|
|
__m128i xmm1 = LOAD_SI128(sptr); \
|
|
|
|
|
sptr += (16 / sizeof(_type_)); \
|
|
|
|
|
xmm1 = _op_(xmm1, xmm0); \
|
|
|
|
|
_mm_store_si128((__m128i*)dptr, xmm1); \
|
|
|
|
|
dptr += (16 / sizeof(_type_)); \
|
|
|
|
|
} \
|
|
|
|
|
/* Finish off the remainder. */ \
|
|
|
|
|
while (len--) \
|
|
|
|
|
{ \
|
|
|
|
|
_slowWay_; \
|
|
|
|
|
} \
|
|
|
|
|
return PRIMITIVES_SUCCESS; \
|
2016-04-05 18:07:45 +03:00
|
|
|
}
|
2013-01-19 02:32:58 +04:00
|
|
|
|
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
|
|
|
* SSD = Source1, Source2, Destination
|
|
|
|
|
*/
|
2019-11-20 13:30:14 +03:00
|
|
|
#define SSE3_SSD_ROUTINE(_name_, _type_, _fallback_, _op_, _slowWay_) \
|
|
|
|
|
static pstatus_t _name_(const _type_* pSrc1, const _type_* pSrc2, _type_* pDst, UINT32 len) \
|
|
|
|
|
{ \
|
|
|
|
|
int shifts = 0; \
|
|
|
|
|
UINT32 offBeatMask; \
|
|
|
|
|
const _type_* sptr1 = pSrc1; \
|
|
|
|
|
const _type_* sptr2 = pSrc2; \
|
|
|
|
|
_type_* dptr = pDst; \
|
|
|
|
|
size_t count; \
|
|
|
|
|
if (len < 16) /* pointless if too small */ \
|
|
|
|
|
{ \
|
|
|
|
|
return _fallback_(pSrc1, pSrc2, pDst, len); \
|
|
|
|
|
} \
|
|
|
|
|
if (sizeof(_type_) == 1) \
|
|
|
|
|
shifts = 1; \
|
|
|
|
|
else if (sizeof(_type_) == 2) \
|
|
|
|
|
shifts = 2; \
|
|
|
|
|
else if (sizeof(_type_) == 4) \
|
|
|
|
|
shifts = 3; \
|
|
|
|
|
else if (sizeof(_type_) == 8) \
|
|
|
|
|
shifts = 4; \
|
|
|
|
|
offBeatMask = (1 << (shifts - 1)) - 1; \
|
|
|
|
|
if ((ULONG_PTR)pDst & offBeatMask) \
|
|
|
|
|
{ \
|
|
|
|
|
/* Incrementing the pointer skips over 16-byte boundary. */ \
|
|
|
|
|
return _fallback_(pSrc1, pSrc2, pDst, len); \
|
|
|
|
|
} \
|
|
|
|
|
/* Get to the 16-byte boundary now. */ \
|
|
|
|
|
while ((ULONG_PTR)dptr & 0x0f) \
|
|
|
|
|
{ \
|
|
|
|
|
pstatus_t status; \
|
|
|
|
|
status = _slowWay_; \
|
|
|
|
|
if (status != PRIMITIVES_SUCCESS) \
|
|
|
|
|
return status; \
|
|
|
|
|
if (--len == 0) \
|
|
|
|
|
return PRIMITIVES_SUCCESS; \
|
|
|
|
|
} \
|
|
|
|
|
/* Use 4 128-bit SSE registers. */ \
|
|
|
|
|
count = len >> (7 - shifts); \
|
|
|
|
|
len -= count << (7 - shifts); \
|
2021-08-02 13:13:34 +03:00
|
|
|
if (((const ULONG_PTR)sptr1 & 0x0f) || ((const ULONG_PTR)sptr2 & 0x0f)) \
|
2019-11-20 13:30:14 +03:00
|
|
|
{ \
|
|
|
|
|
/* Unaligned loads */ \
|
|
|
|
|
while (count--) \
|
|
|
|
|
{ \
|
|
|
|
|
__m128i xmm0, xmm1, xmm2, xmm3, xmm4, xmm5, xmm6, xmm7; \
|
2021-08-02 13:13:34 +03:00
|
|
|
xmm0 = _mm_lddqu_si128((const __m128i*)sptr1); \
|
2019-11-20 13:30:14 +03:00
|
|
|
sptr1 += (16 / sizeof(_type_)); \
|
2021-08-02 13:13:34 +03:00
|
|
|
xmm1 = _mm_lddqu_si128((const __m128i*)sptr1); \
|
2019-11-20 13:30:14 +03:00
|
|
|
sptr1 += (16 / sizeof(_type_)); \
|
2021-08-02 13:13:34 +03:00
|
|
|
xmm2 = _mm_lddqu_si128((const __m128i*)sptr1); \
|
2019-11-20 13:30:14 +03:00
|
|
|
sptr1 += (16 / sizeof(_type_)); \
|
2021-08-02 13:13:34 +03:00
|
|
|
xmm3 = _mm_lddqu_si128((const __m128i*)sptr1); \
|
2019-11-20 13:30:14 +03:00
|
|
|
sptr1 += (16 / sizeof(_type_)); \
|
2021-08-02 13:13:34 +03:00
|
|
|
xmm4 = _mm_lddqu_si128((const __m128i*)sptr2); \
|
2019-11-20 13:30:14 +03:00
|
|
|
sptr2 += (16 / sizeof(_type_)); \
|
2021-08-02 13:13:34 +03:00
|
|
|
xmm5 = _mm_lddqu_si128((const __m128i*)sptr2); \
|
2019-11-20 13:30:14 +03:00
|
|
|
sptr2 += (16 / sizeof(_type_)); \
|
2021-08-02 13:13:34 +03:00
|
|
|
xmm6 = _mm_lddqu_si128((const __m128i*)sptr2); \
|
2019-11-20 13:30:14 +03:00
|
|
|
sptr2 += (16 / sizeof(_type_)); \
|
2021-08-02 13:13:34 +03:00
|
|
|
xmm7 = _mm_lddqu_si128((const __m128i*)sptr2); \
|
2019-11-20 13:30:14 +03:00
|
|
|
sptr2 += (16 / sizeof(_type_)); \
|
|
|
|
|
xmm0 = _op_(xmm0, xmm4); \
|
|
|
|
|
xmm1 = _op_(xmm1, xmm5); \
|
|
|
|
|
xmm2 = _op_(xmm2, xmm6); \
|
|
|
|
|
xmm3 = _op_(xmm3, xmm7); \
|
|
|
|
|
_mm_store_si128((__m128i*)dptr, xmm0); \
|
|
|
|
|
dptr += (16 / sizeof(_type_)); \
|
|
|
|
|
_mm_store_si128((__m128i*)dptr, xmm1); \
|
|
|
|
|
dptr += (16 / sizeof(_type_)); \
|
|
|
|
|
_mm_store_si128((__m128i*)dptr, xmm2); \
|
|
|
|
|
dptr += (16 / sizeof(_type_)); \
|
|
|
|
|
_mm_store_si128((__m128i*)dptr, xmm3); \
|
|
|
|
|
dptr += (16 / sizeof(_type_)); \
|
|
|
|
|
} \
|
|
|
|
|
} \
|
|
|
|
|
else \
|
|
|
|
|
{ \
|
|
|
|
|
/* Aligned loads */ \
|
|
|
|
|
while (count--) \
|
|
|
|
|
{ \
|
|
|
|
|
__m128i xmm0, xmm1, xmm2, xmm3, xmm4, xmm5, xmm6, xmm7; \
|
2021-08-02 13:13:34 +03:00
|
|
|
xmm0 = _mm_load_si128((const __m128i*)sptr1); \
|
2019-11-20 13:30:14 +03:00
|
|
|
sptr1 += (16 / sizeof(_type_)); \
|
2021-08-02 13:13:34 +03:00
|
|
|
xmm1 = _mm_load_si128((const __m128i*)sptr1); \
|
2019-11-20 13:30:14 +03:00
|
|
|
sptr1 += (16 / sizeof(_type_)); \
|
2021-08-02 13:13:34 +03:00
|
|
|
xmm2 = _mm_load_si128((const __m128i*)sptr1); \
|
2019-11-20 13:30:14 +03:00
|
|
|
sptr1 += (16 / sizeof(_type_)); \
|
2021-08-02 13:13:34 +03:00
|
|
|
xmm3 = _mm_load_si128((const __m128i*)sptr1); \
|
2019-11-20 13:30:14 +03:00
|
|
|
sptr1 += (16 / sizeof(_type_)); \
|
2021-08-02 13:13:34 +03:00
|
|
|
xmm4 = _mm_load_si128((const __m128i*)sptr2); \
|
2019-11-20 13:30:14 +03:00
|
|
|
sptr2 += (16 / sizeof(_type_)); \
|
2021-08-02 13:13:34 +03:00
|
|
|
xmm5 = _mm_load_si128((const __m128i*)sptr2); \
|
2019-11-20 13:30:14 +03:00
|
|
|
sptr2 += (16 / sizeof(_type_)); \
|
2021-08-02 13:13:34 +03:00
|
|
|
xmm6 = _mm_load_si128((const __m128i*)sptr2); \
|
2019-11-20 13:30:14 +03:00
|
|
|
sptr2 += (16 / sizeof(_type_)); \
|
2021-08-02 13:13:34 +03:00
|
|
|
xmm7 = _mm_load_si128((const __m128i*)sptr2); \
|
2019-11-20 13:30:14 +03:00
|
|
|
sptr2 += (16 / sizeof(_type_)); \
|
|
|
|
|
xmm0 = _op_(xmm0, xmm4); \
|
|
|
|
|
xmm1 = _op_(xmm1, xmm5); \
|
|
|
|
|
xmm2 = _op_(xmm2, xmm6); \
|
|
|
|
|
xmm3 = _op_(xmm3, xmm7); \
|
|
|
|
|
_mm_store_si128((__m128i*)dptr, xmm0); \
|
|
|
|
|
dptr += (16 / sizeof(_type_)); \
|
|
|
|
|
_mm_store_si128((__m128i*)dptr, xmm1); \
|
|
|
|
|
dptr += (16 / sizeof(_type_)); \
|
|
|
|
|
_mm_store_si128((__m128i*)dptr, xmm2); \
|
|
|
|
|
dptr += (16 / sizeof(_type_)); \
|
|
|
|
|
_mm_store_si128((__m128i*)dptr, xmm3); \
|
|
|
|
|
dptr += (16 / sizeof(_type_)); \
|
|
|
|
|
} \
|
|
|
|
|
} \
|
|
|
|
|
/* Use a single 128-bit SSE register. */ \
|
|
|
|
|
count = len >> (5 - shifts); \
|
|
|
|
|
len -= count << (5 - shifts); \
|
|
|
|
|
while (count--) \
|
|
|
|
|
{ \
|
|
|
|
|
__m128i xmm0, xmm1; \
|
|
|
|
|
xmm0 = LOAD_SI128(sptr1); \
|
|
|
|
|
sptr1 += (16 / sizeof(_type_)); \
|
|
|
|
|
xmm1 = LOAD_SI128(sptr2); \
|
|
|
|
|
sptr2 += (16 / sizeof(_type_)); \
|
|
|
|
|
xmm0 = _op_(xmm0, xmm1); \
|
|
|
|
|
_mm_store_si128((__m128i*)dptr, xmm0); \
|
|
|
|
|
dptr += (16 / sizeof(_type_)); \
|
|
|
|
|
} \
|
|
|
|
|
/* Finish off the remainder. */ \
|
|
|
|
|
while (len--) \
|
|
|
|
|
{ \
|
|
|
|
|
_slowWay_; \
|
|
|
|
|
} \
|
|
|
|
|
return PRIMITIVES_SUCCESS; \
|
2016-04-05 18:07:45 +03:00
|
|
|
}
|
2013-01-19 02:32:58 +04:00
|
|
|
|
2017-06-06 15:01:41 +03:00
|
|
|
#endif /* FREERDP_LIB_PRIM_TEMPLATES_H */
|
