d04a74c7a2
- tx_timer value for data sizes other than 8 fixed - MCR bit 3 (OUT2) controls the serial interrupt generation
178 lines
6.2 KiB
C++
178 lines
6.2 KiB
C++
/////////////////////////////////////////////////////////////////////////
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// $Id: serial.h,v 1.10 2003-09-14 20:16:25 vruppert Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2002 MandrakeSoft S.A.
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//
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// MandrakeSoft S.A.
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// 43, rue d'Aboukir
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// 75002 Paris - France
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// http://www.linux-mandrake.com/
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// http://www.mandrakesoft.com/
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//
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// This library is free software; you can redistribute it and/or
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// modify it under the terms of the GNU Lesser General Public
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// License as published by the Free Software Foundation; either
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// version 2 of the License, or (at your option) any later version.
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//
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// This library is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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// Lesser General Public License for more details.
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//
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// You should have received a copy of the GNU Lesser General Public
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// License along with this library; if not, write to the Free Software
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// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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// Peter Grehan (grehan@iprg.nokia.com) coded most of this
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// serial emulation.
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#if USE_RAW_SERIAL
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#include "serial_raw.h"
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#endif // USE_RAW_SERIAL
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#if BX_USE_SER_SMF
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# define BX_SER_SMF static
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# define BX_SER_THIS theSerialDevice->
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#else
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# define BX_SER_SMF
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# define BX_SER_THIS this->
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#endif
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#define BX_SERIAL_MAXDEV 4
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#define BX_SERIAL_CONFDEV 1 /* only 1 serial port currently */
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#define BX_PC_CLOCK_XTL 1843200.0
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#define BX_SER_RXIDLE 0
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#define BX_SER_RXPOLL 1
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#define BX_SER_RXWAIT 2
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typedef struct {
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/*
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* UART internal state
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*/
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bx_bool ls_interrupt;
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bx_bool ms_interrupt;
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bx_bool rx_interrupt;
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bx_bool tx_interrupt;
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bx_bool ls_ipending;
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bx_bool ms_ipending;
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bx_bool rx_ipending;
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bx_bool tx_ipending;
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int baudrate;
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int tx_timer_index;
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int rx_pollstate;
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int rx_timer_index;
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#define RX_CB_SIZE 80
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int rx_cb_start;
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int rx_cb_end;
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unsigned char rx_cbuf[RX_CB_SIZE];
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/*
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* Register definitions
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*/
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Bit8u rxbuffer; /* receiver buffer register (r/o) */
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Bit8u thrbuffer; /* transmit holding register (w/o) */
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/* Interrupt Enable Register */
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struct {
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bx_bool rxdata_enable; /* 1=enable receive data interrupts */
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bx_bool txhold_enable; /* 1=enable tx. holding reg. empty ints */
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bx_bool rxlstat_enable; /* 1=enable rx line status interrupts */
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bx_bool modstat_enable; /* 1=enable modem status interrupts */
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} int_enable;
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/* Interrupt Identification Register (r/o) */
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struct {
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bx_bool ipending; /* 0=interrupt pending */
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Bit8u int_ID; /* 3-bit interrupt ID */
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Bit8u fifo_enabled; /* 2-bit, set to b11 when FCR0 enabled */
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} int_ident;
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/* FIFO Control Register (w/o) */
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struct {
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bx_bool enable; /* 1=enable tx and rx FIFOs */
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bx_bool rxreset; /* 1=clear rx fifo. self-clearing */
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bx_bool txreset; /* 1=clear tx fifo. self-clearing */
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bx_bool dmamode; /* 1=DMA mode 1 (unused on PC ?) */
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Bit8u rxtrigger; /* 2-bit code for rx fifo trigger level */
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} fifo_cntl;
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/* Line Control Register (r/w) */
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struct {
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Bit8u wordlen_sel; /* 2-bit code for char length */
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bx_bool stopbits; /* select stop bit len */
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bx_bool parity_enable; /* ... */
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bx_bool evenparity_sel; /* ... */
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bx_bool stick_parity; /* ... */
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bx_bool break_cntl; /* 1=send break signal */
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bx_bool dlab; /* divisor latch access bit */
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} line_cntl;
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/* MODEM Control Register (r/w) */
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struct {
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bx_bool dtr; /* DTR output value */
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bx_bool rts; /* RTS output value */
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bx_bool out1; /* OUTPUT1 value */
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bx_bool out2; /* OUTPUT2 value */
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bx_bool local_loopback; /* 1=loopback mode */
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} modem_cntl;
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/* Line Status Register (r/w) */
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struct {
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bx_bool rxdata_ready; /* 1=receiver data ready */
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bx_bool overrun_error; /* 1=receive overrun detected */
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bx_bool parity_error; /* 1=rx char has a bad parity bit */
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bx_bool framing_error; /* 1=no stop bit detected for rx char */
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bx_bool break_int; /* 1=break signal detected */
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bx_bool thr_empty; /* 1=tx hold register (or fifo) is empty */
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bx_bool tsr_empty; /* 1=shift reg and hold reg empty */
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bx_bool fifo_error; /* 1=at least 1 err condition in fifo */
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} line_status;
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/* Modem Status Register (r/w) */
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struct {
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bx_bool delta_cts; /* 1=CTS changed since last read */
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bx_bool delta_dsr; /* 1=DSR changed since last read */
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bx_bool ri_trailedge; /* 1=RI moved from low->high */
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bx_bool delta_dcd; /* 1=CD changed since last read */
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bx_bool cts; /* CTS input value */
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bx_bool dsr; /* DSR input value */
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bx_bool ri; /* RI input value */
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bx_bool dcd; /* DCD input value */
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} modem_status;
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Bit8u scratch; /* Scratch Register (r/w) */
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Bit8u tsrbuffer; /* transmit shift register (internal) */
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Bit8u divisor_lsb; /* Divisor latch, least-sig. byte */
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Bit8u divisor_msb; /* Divisor latch, most-sig. byte */
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} bx_serial_t;
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class bx_serial_c : public bx_devmodel_c {
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public:
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bx_serial_c(void);
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~bx_serial_c(void);
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virtual void init(void);
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virtual void reset(unsigned type);
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#if USE_RAW_SERIAL
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serial_raw* raw;
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#endif // USE_RAW_SERIAL
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private:
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bx_serial_t s[BX_SERIAL_MAXDEV];
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static void tx_timer_handler(void *);
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BX_SER_SMF void tx_timer(void);
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static void rx_timer_handler(void *);
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BX_SER_SMF void rx_timer(void);
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static Bit32u read_handler(void *this_ptr, Bit32u address, unsigned io_len);
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static void write_handler(void *this_ptr, Bit32u address, Bit32u value, unsigned io_len);
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#if !BX_USE_SER_SMF
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Bit32u read(Bit32u address, unsigned io_len);
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void write(Bit32u address, Bit32u value, unsigned io_len);
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#endif
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};
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