378 lines
11 KiB
C++
378 lines
11 KiB
C++
/////////////////////////////////////////////////////////////////////////
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// $Id: acpi.cc,v 1.2 2006-09-26 18:43:42 vruppert Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2006 Volker Ruppert
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//
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// This library is free software; you can redistribute it and/or
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// modify it under the terms of the GNU Lesser General Public
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// License as published by the Free Software Foundation; either
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// version 2 of the License, or (at your option) any later version.
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//
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// This library is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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// Lesser General Public License for more details.
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//
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// You should have received a copy of the GNU Lesser General Public
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// License along with this library; if not, write to the Free Software
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// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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//
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// PIIX4 ACPI support
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//
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// Define BX_PLUGGABLE in files that can be compiled into plugins. For
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// platforms that require a special tag on exported symbols, BX_PLUGGABLE
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// is used to know when we are exporting symbols and when we are importing.
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#define BX_PLUGGABLE
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#include "iodev.h"
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#if BX_SUPPORT_PCI && BX_SUPPORT_ACPI
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#define LOG_THIS theACPIController->
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bx_acpi_ctrl_c* theACPIController = NULL;
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// FIXME
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const Bit8u acpi_pm_iomask[64] = {2, 0, 2, 0, 2, 0, 0, 0, 7, 7, 7, 7, 7, 7, 7, 7,
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7, 7, 7, 7, 1, 1, 0, 0, 7, 7, 0, 0, 7, 7, 7, 7,
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7, 7, 0, 0, 0, 0, 0, 0, 7, 7, 7, 7, 7, 7, 7, 7,
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1, 1, 1, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0};
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const Bit8u acpi_sm_iomask[16] = {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2, 0, 2, 0, 0, 0};
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int libacpi_LTX_plugin_init(plugin_t *plugin, plugintype_t type, int argc, char *argv[])
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{
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theACPIController = new bx_acpi_ctrl_c();
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bx_devices.pluginACPIController = theACPIController;
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BX_REGISTER_DEVICE_DEVMODEL(plugin, type, theACPIController, BX_PLUGIN_ACPI);
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return 0; // Success
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}
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void libacpi_LTX_plugin_fini(void)
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{
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delete theACPIController;
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}
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bx_acpi_ctrl_c::bx_acpi_ctrl_c()
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{
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put("ACPI");
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settype(ACPILOG);
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}
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bx_acpi_ctrl_c::~bx_acpi_ctrl_c()
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{
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BX_DEBUG(("Exit"));
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}
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void bx_acpi_ctrl_c::init(void)
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{
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// called once when bochs initializes
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unsigned i;
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BX_ACPI_THIS s.devfunc = BX_PCI_DEVICE(1, 3);
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DEV_register_pci_handlers(this, &BX_ACPI_THIS s.devfunc, BX_PLUGIN_ACPI,
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"ACPI Controller");
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for (i=0; i<256; i++) {
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BX_ACPI_THIS s.pci_conf[i] = 0x0;
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}
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BX_ACPI_THIS s.pm_base = 0x0;
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BX_ACPI_THIS s.sm_base = 0x0;
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// readonly registers
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static const struct init_vals_t {
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unsigned addr;
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unsigned char val;
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} init_vals[] = {
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{ 0x00, 0x86 }, { 0x01, 0x80 },
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{ 0x02, 0x13 }, { 0x03, 0x71 },
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{ 0x0a, 0x80 }, // other bridge device
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{ 0x0b, 0x06 }, // bridge device
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{ 0x0e, 0x00 }, // header type
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{ 0x3d, BX_PCI_INTA } // interrupt pin #1
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};
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for (i = 0; i < sizeof(init_vals) / sizeof(*init_vals); ++i) {
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BX_ACPI_THIS s.pci_conf[init_vals[i].addr] = init_vals[i].val;
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}
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}
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void bx_acpi_ctrl_c::reset(unsigned type)
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{
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static const struct reset_vals_t {
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unsigned addr;
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unsigned char val;
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} reset_vals[] = {
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{ 0x04, 0x00 }, { 0x05, 0x00 }, // command_io + command_mem
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{ 0x06, 0x80 }, { 0x07, 0x02 }, // status_devsel_medium
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{ 0x3c, 0x00 }, // IRQ
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// PM base 0x40 - 0x43
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{ 0x40, 0x01 }, { 0x41, 0x00 },
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{ 0x42, 0x00 }, { 0x43, 0x00 },
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// device resources
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{ 0x5f, 0x90 }, { 0x63, 0x60 },
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{ 0x67, 0x98 },
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// SM base 0x90 - 0x93
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{ 0x90, 0x01 }, { 0x91, 0x00 },
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{ 0x92, 0x00 }, { 0x93, 0x00 }
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};
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for (unsigned i = 0; i < sizeof(reset_vals) / sizeof(*reset_vals); ++i) {
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BX_ACPI_THIS s.pci_conf[reset_vals[i].addr] = reset_vals[i].val;
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}
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BX_ACPI_THIS s.pmsts = 0;
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BX_ACPI_THIS s.pmen = 0;
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BX_ACPI_THIS s.pmcntrl = 0;
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}
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#if BX_SUPPORT_SAVE_RESTORE
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void bx_acpi_ctrl_c::register_state(void)
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{
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unsigned i;
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char name[6];
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bx_list_c *list = new bx_list_c(SIM->get_sr_root(), "acpi", "ACPI Controller State");
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BXRS_HEX_PARAM_FIELD(list, pmsts, BX_ACPI_THIS s.pmsts);
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BXRS_HEX_PARAM_FIELD(list, pmen, BX_ACPI_THIS s.pmen);
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BXRS_HEX_PARAM_FIELD(list, pmcntrl, BX_ACPI_THIS s.pmcntrl);
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bx_list_c *pci_conf = new bx_list_c(list, "pci_conf", 256);
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for (i=0; i<256; i++) {
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sprintf(name, "0x%02x", i);
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new bx_shadow_num_c(pci_conf, name, &BX_ACPI_THIS s.pci_conf[i], BASE_HEX);
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}
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}
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void bx_acpi_ctrl_c::after_restore_state(void)
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{
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if (DEV_pci_set_base_io(BX_ACPI_THIS_PTR, read_handler, write_handler,
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&BX_ACPI_THIS s.pm_base,
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&BX_ACPI_THIS s.pci_conf[0x40],
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64, &acpi_pm_iomask[0], "ACPI PM base"))
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{
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BX_INFO(("new PM base address: 0x%04x", BX_ACPI_THIS s.pm_base));
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}
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if (DEV_pci_set_base_io(BX_ACPI_THIS_PTR, read_handler, write_handler,
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&BX_ACPI_THIS s.sm_base,
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&BX_ACPI_THIS s.pci_conf[0x90],
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16, &acpi_sm_iomask[0], "ACPI SM base"))
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{
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BX_INFO(("new SM base address: 0x%04x", BX_ACPI_THIS s.sm_base));
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}
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}
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#endif
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void bx_acpi_ctrl_c::set_irq_level(bx_bool level)
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{
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DEV_pci_set_irq(BX_ACPI_THIS s.devfunc, BX_ACPI_THIS s.pci_conf[0x3d], level);
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}
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// static IO port read callback handler
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// redirects to non-static class handler to avoid virtual functions
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Bit32u bx_acpi_ctrl_c::read_handler(void *this_ptr, Bit32u address, unsigned io_len)
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{
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#if !BX_USE_ACPI_SMF
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bx_acpi_ctrl_c *class_ptr = (bx_acpi_ctrl_c *) this_ptr;
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return class_ptr->read(address, io_len);
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}
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Bit32u bx_acpi_ctrl_c::read(Bit32u address, unsigned io_len)
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{
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#else
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UNUSED(this_ptr);
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#endif // !BX_USE_ACPI_SMF
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Bit8u reg = address & 0x3f;
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Bit32u value = 0xffffffff;
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if ((address & 0xffc0) == BX_ACPI_THIS s.pm_base) {
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switch (reg) {
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case 0x00:
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value = BX_ACPI_THIS s.pmsts;
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break;
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case 0x02:
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value = BX_ACPI_THIS s.pmen;
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break;
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case 0x04:
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value = BX_ACPI_THIS s.pmcntrl;
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break;
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default:
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BX_INFO(("ACPI read from PM register 0x%02x not implemented yet", reg));
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}
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} else {
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BX_INFO(("ACPI read from SM register 0x%02x not implemented yet", reg));
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}
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return value;
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}
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// static IO port write callback handler
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// redirects to non-static class handler to avoid virtual functions
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void bx_acpi_ctrl_c::write_handler(void *this_ptr, Bit32u address, Bit32u value, unsigned io_len)
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{
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#if !BX_USE_ACPI_SMF
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bx_acpi_ctrl_c *class_ptr = (bx_acpi_ctrl_c *) this_ptr;
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class_ptr->write(address, value, io_len);
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}
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void bx_acpi_ctrl_c::write(Bit32u address, Bit32u value, unsigned io_len)
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{
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#else
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UNUSED(this_ptr);
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#endif // !BX_USE_ACPI_SMF
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Bit8u reg = address & 0x3f;
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if ((address & 0xffc0) == BX_ACPI_THIS s.pm_base) {
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switch (reg) {
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case 0x00:
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BX_ACPI_THIS s.pmsts &= ~value;
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break;
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case 0x02:
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BX_ACPI_THIS s.pmen = value;
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break;
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case 0x04:
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BX_ACPI_THIS s.pmcntrl = value;
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break;
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default:
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BX_INFO(("ACPI write to PM register 0x%02x not implemented yet", reg));
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}
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} else {
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BX_INFO(("ACPI write to SM register 0x%02x not implemented yet", reg));
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}
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}
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// pci configuration space read callback handler
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Bit32u bx_acpi_ctrl_c::pci_read_handler(Bit8u address, unsigned io_len)
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{
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Bit32u value = 0;
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if (io_len > 4 || io_len == 0) {
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BX_DEBUG(("ACPI controller read register 0x%02x, len=%u !",
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(unsigned) address, (unsigned) io_len));
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return 0xffffffff;
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}
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const char* pszName = " ";
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switch (address) {
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case 0x00: if (io_len == 2) {
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pszName = "(vendor id) ";
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} else if (io_len == 4) {
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pszName = "(vendor + device) ";
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}
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break;
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case 0x04: if (io_len == 2) {
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pszName = "(command) ";
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} else if (io_len == 4) {
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pszName = "(command+status) ";
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}
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break;
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case 0x08: if (io_len == 1) {
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pszName = "(revision id) ";
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} else if (io_len == 4) {
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pszName = "(rev.+class code) ";
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}
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break;
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case 0x0c: pszName = "(cache line size) "; break;
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case 0x28: pszName = "(cardbus cis) "; break;
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case 0x2c: pszName = "(subsys. vendor+) "; break;
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case 0x30: pszName = "(rom base) "; break;
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case 0x3c: pszName = "(interrupt line+) "; break;
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case 0x3d: pszName = "(interrupt pin) "; break;
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}
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// This odd code is to display only what bytes actually were read.
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char szTmp[9];
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char szTmp2[3];
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szTmp[0] = '\0';
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szTmp2[0] = '\0';
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for (unsigned i=0; i<io_len; i++) {
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value |= (BX_ACPI_THIS s.pci_conf[address+i] << (i*8));
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sprintf(szTmp2, "%02x", (BX_ACPI_THIS s.pci_conf[address+i]));
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strrev(szTmp2);
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strcat(szTmp, szTmp2);
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}
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strrev(szTmp);
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BX_DEBUG(("ACPI controller read register 0x%02x %svalue 0x%s",
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address, pszName, szTmp));
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return value;
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}
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// static pci configuration space write callback handler
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void bx_acpi_ctrl_c::pci_write_handler(Bit8u address, Bit32u value, unsigned io_len)
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{
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Bit8u value8, oldval;
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bx_bool pm_base_change = 0, sm_base_change = 0;
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if ((address >= 0x10) && (address < 0x34))
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return;
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// This odd code is to display only what bytes actually were written.
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char szTmp[9];
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char szTmp2[3];
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szTmp[0] = '\0';
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szTmp2[0] = '\0';
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for (unsigned i=0; i<io_len; i++) {
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value8 = (value >> (i*8)) & 0xFF;
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oldval = BX_ACPI_THIS s.pci_conf[address+i];
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switch (address+i) {
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case 0x04:
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value8 = (value8 & 0xfe) | (value & 0x01);
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goto set_value;
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break;
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case 0x06: // disallowing write to status lo-byte (is that expected?)
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strcpy(szTmp2, "..");
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break;
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case 0x3c:
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if (value8 != oldval) {
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BX_INFO(("new irq line = %d", value8));
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}
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goto set_value;
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break;
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case 0x40:
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value8 = (value8 & 0xfc) | 0x01;
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case 0x41:
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case 0x42:
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case 0x43:
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pm_base_change |= (value8 != oldval);
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goto set_value;
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break;
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case 0x90:
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value8 = (value8 & 0xfc) | 0x01;
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case 0x91:
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case 0x92:
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case 0x93:
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sm_base_change |= (value8 != oldval);
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default:
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set_value:
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BX_ACPI_THIS s.pci_conf[address+i] = value8;
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sprintf(szTmp2, "%02x", value8);
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}
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strrev(szTmp2);
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strcat(szTmp, szTmp2);
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}
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if (pm_base_change) {
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if (DEV_pci_set_base_io(BX_ACPI_THIS_PTR, read_handler, write_handler,
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&BX_ACPI_THIS s.pm_base,
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&BX_ACPI_THIS s.pci_conf[0x40],
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64, &acpi_pm_iomask[0], "ACPI PM base"))
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{
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BX_INFO(("new PM base address: 0x%04x", BX_ACPI_THIS s.pm_base));
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}
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}
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if (sm_base_change) {
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if (DEV_pci_set_base_io(BX_ACPI_THIS_PTR, read_handler, write_handler,
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&BX_ACPI_THIS s.sm_base,
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&BX_ACPI_THIS s.pci_conf[0x90],
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16, &acpi_sm_iomask[0], "ACPI SM base"))
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{
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BX_INFO(("new SM base address: 0x%04x", BX_ACPI_THIS s.sm_base));
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}
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}
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strrev(szTmp);
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BX_DEBUG(("ACPI controller write register 0x%02x value 0x%s", address, szTmp));
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}
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#endif // BX_SUPPORT_PCI
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