231 lines
6.6 KiB
C++
231 lines
6.6 KiB
C++
/////////////////////////////////////////////////////////////////////////
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// $Id$
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (c) 2006-2009 Stanislav Shwartsman
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// Written by Stanislav Shwartsman [sshwarts at sourceforge net]
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//
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// This library is free software; you can redistribute it and/or
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// modify it under the terms of the GNU Lesser General Public
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// License as published by the Free Software Foundation; either
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// version 2 of the License, or (at your option) any later version.
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//
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// This library is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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// Lesser General Public License for more details.
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//
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// You should have received a copy of the GNU Lesser General Public
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// License along with this library; if not, write to the Free Software
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// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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#include <assert.h>
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#include "bochs.h"
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#include "cpu/cpu.h"
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#include "disasm/disasm.h"
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// maximum size of an instruction
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#define MAX_OPCODE_LENGTH 16
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// maximum physical addresses an instruction can generate
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#define MAX_DATA_ACCESSES 1024
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// Use this variable to turn on/off collection of instrumentation data
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// If you are not using the debugger to turn this on/off, then possibly
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// start this at 1 instead of 0.
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static bx_bool active = 1;
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static disassembler bx_disassembler;
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static struct instruction_t {
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bx_bool ready; // is current instruction ready to be printed
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unsigned opcode_length;
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Bit8u opcode[MAX_OPCODE_LENGTH];
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bx_bool is32, is64;
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unsigned num_data_accesses;
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struct {
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bx_address laddr; // linear address
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bx_phy_address paddr; // physical address
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unsigned op; // BX_READ, BX_WRITE or BX_RW
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unsigned size; // 1 .. 32
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} data_access[MAX_DATA_ACCESSES];
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bx_bool is_branch;
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bx_bool is_taken;
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bx_address target_linear;
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} *instruction;
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static logfunctions *instrument_log = new logfunctions ();
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#define LOG_THIS instrument_log->
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void bx_instr_init_env(void) {}
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void bx_instr_exit_env(void) {}
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void bx_instr_initialize(unsigned cpu)
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{
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assert(cpu < BX_SMP_PROCESSORS);
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if (instruction == NULL)
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instruction = new struct instruction_t[BX_SMP_PROCESSORS];
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fprintf(stderr, "Initialize cpu %d\n", cpu);
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}
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void bx_instr_reset(unsigned cpu, unsigned type)
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{
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instruction[cpu].ready = 0;
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instruction[cpu].num_data_accesses = 0;
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instruction[cpu].is_branch = 0;
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}
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void bx_print_instruction(unsigned cpu, const instruction_t *i)
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{
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char disasm_tbuf[512]; // buffer for instruction disassembly
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unsigned length = i->opcode_length, n;
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bx_disassembler.disasm(i->is32, i->is64, 0, 0, i->opcode, disasm_tbuf);
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if(length != 0)
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{
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fprintf(stderr, "----------------------------------------------------------\n");
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fprintf(stderr, "CPU: %d: %s\n", cpu, disasm_tbuf);
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fprintf(stderr, "LEN: %d\tBYTES: ", length);
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for(n=0;n < length;n++) fprintf(stderr, "%02x", i->opcode[n]);
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if(i->is_branch)
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{
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fprintf(stderr, "\tBRANCH ");
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if(i->is_taken)
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fprintf(stderr, "TARGET " FMT_ADDRX " (TAKEN)", i->target_linear);
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else
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fprintf(stderr, "(NOT TAKEN)");
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}
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fprintf(stderr, "\n");
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for(n=0;n < i->num_data_accesses;n++)
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{
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fprintf(stderr, "MEM ACCESS[%u]: 0x" FMT_ADDRX " (linear) 0x" FMT_PHY_ADDRX " (physical) %s SIZE: %d\n", n,
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i->data_access[n].laddr,
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i->data_access[n].paddr,
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i->data_access[n].op == BX_READ ? "RD":"WR",
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i->data_access[n].size);
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}
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fprintf(stderr, "\n");
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}
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}
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void bx_instr_before_execution(unsigned cpu, bxInstruction_c *bx_instr)
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{
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if (!active) return;
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instruction_t *i = &instruction[cpu];
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if (i->ready) bx_print_instruction(cpu, i);
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// prepare instruction_t structure for new instruction
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i->ready = 1;
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i->num_data_accesses = 0;
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i->is_branch = 0;
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i->is32 = BX_CPU(cpu)->sregs[BX_SEG_REG_CS].cache.u.segment.d_b;
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i->is64 = BX_CPU(cpu)->long64_mode();
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i->opcode_length = bx_instr->ilen();
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memcpy(i->opcode, bx_instr->get_opcode_bytes(), i->opcode_length);
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}
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void bx_instr_after_execution(unsigned cpu, bxInstruction_c *bx_instr)
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{
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if (!active) return;
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instruction_t *i = &instruction[cpu];
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if (i->ready) {
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bx_print_instruction(cpu, i);
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i->ready = 0;
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}
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}
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static void branch_taken(unsigned cpu, bx_address new_eip)
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{
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if (!active || !instruction[cpu].ready) return;
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// find linear address
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bx_address laddr = BX_CPU(cpu)->get_laddr(BX_SEG_REG_CS, new_eip);
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instruction[cpu].is_branch = 1;
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instruction[cpu].is_taken = 1;
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instruction[cpu].target_linear = laddr;
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}
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void bx_instr_cnear_branch_taken(unsigned cpu, bx_address new_eip)
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{
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branch_taken(cpu, new_eip);
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}
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void bx_instr_cnear_branch_not_taken(unsigned cpu)
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{
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if (!active || !instruction[cpu].ready) return;
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instruction[cpu].is_branch = 1;
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instruction[cpu].is_taken = 0;
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}
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void bx_instr_ucnear_branch(unsigned cpu, unsigned what, bx_address new_eip)
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{
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branch_taken(cpu, new_eip);
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}
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void bx_instr_far_branch(unsigned cpu, unsigned what, Bit16u new_cs, bx_address new_eip)
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{
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branch_taken(cpu, new_eip);
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}
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void bx_instr_interrupt(unsigned cpu, unsigned vector)
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{
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if(active)
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{
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fprintf(stderr, "CPU %u: interrupt %02xh\n", cpu, vector);
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}
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}
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void bx_instr_exception(unsigned cpu, unsigned vector, unsigned error_code)
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{
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if(active)
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{
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fprintf(stderr, "CPU %u: exception %02xh, error_code = %x\n", cpu, vector, error_code);
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}
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}
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void bx_instr_hwinterrupt(unsigned cpu, unsigned vector, Bit16u cs, bx_address eip)
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{
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if(active)
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{
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fprintf(stderr, "CPU %u: hardware interrupt %02xh\n", cpu, vector);
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}
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}
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void bx_instr_mem_data_access(unsigned cpu, unsigned seg, bx_address offset, unsigned len, unsigned rw)
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{
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unsigned index;
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bx_phy_address phy;
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if(!active || !instruction[cpu].ready) return;
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if (instruction[cpu].num_data_accesses >= MAX_DATA_ACCESSES)
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{
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return;
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}
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bx_address lin = BX_CPU(cpu)->get_laddr(seg, offset);
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bx_bool page_valid = BX_CPU(cpu)->dbg_xlate_linear2phy(lin, &phy);
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// If linear translation doesn't exist, a paging exception will occur.
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// Invalidate physical address data for now.
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if (!page_valid) phy = (bx_phy_address) (-1);
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index = instruction[cpu].num_data_accesses;
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instruction[cpu].data_access[index].laddr = lin;
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instruction[cpu].data_access[index].paddr = phy;
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instruction[cpu].data_access[index].op = rw;
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instruction[cpu].data_access[index].size = len;
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instruction[cpu].num_data_accesses++;
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}
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