996 lines
32 KiB
C++
996 lines
32 KiB
C++
/////////////////////////////////////////////////////////////////////////
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// $Id: paging.cc,v 1.9 2002-06-19 15:49:07 bdenney Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001 MandrakeSoft S.A.
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//
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// MandrakeSoft S.A.
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// 43, rue d'Aboukir
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// 75002 Paris - France
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// http://www.linux-mandrake.com/
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// http://www.mandrakesoft.com/
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//
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// This library is free software; you can redistribute it and/or
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// modify it under the terms of the GNU Lesser General Public
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// License as published by the Free Software Foundation; either
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// version 2 of the License, or (at your option) any later version.
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//
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// This library is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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// Lesser General Public License for more details.
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//
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// You should have received a copy of the GNU Lesser General Public
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// License along with this library; if not, write to the Free Software
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// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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#if 0
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// - what should the reserved bits in the error code be ?
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// - move CR0.wp bit in lookup table to cache. Then dump
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// cache whenever it is changed. This eliminates the
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// extra calculation and shifting.
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// - change BX_READ and BX_WRITE to 0,1 ???
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#endif
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#define NEED_CPU_REG_SHORTCUTS 1
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#include "bochs.h"
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#define LOG_THIS BX_CPU_THIS_PTR
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#if BX_USE_CPU_SMF
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#define this (BX_CPU(0))
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#endif
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#if 0
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// X86 Registers Which Affect Paging:
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// ==================================
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//
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// CR0:
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// bit 31: PG, Paging (386+)
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// bit 16: WP, Write Protect (486+)
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// 0: allow supervisor level writes into user level RO pages
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// 1: inhibit supervisor level writes into user level RO pages
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//
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// CR3:
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// bit 31..12: PDBR, Page Directory Base Register (386+)
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// bit 4: PCD, Page level Cache Disable (486+)
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// Controls caching of current page directory. Affects only the processor's
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// internal caches (L1 and L2).
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// This flag ignored if paging disabled (PG=0) or cache disabled (CD=1).
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// Values:
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// 0: Page Directory can be cached
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// 1: Page Directory not cached
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// bit 3: PWT, Page level Writes Transparent (486+)
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// Controls write-through or write-back caching policy of current page
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// directory. Affects only the processor's internal caches (L1 and L2).
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// This flag ignored if paging disabled (PG=0) or cache disabled (CD=1).
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// Values:
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// 0: write-back caching enabled
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// 1: write-through caching enabled
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//
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// CR4:
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// bit 4: PSE, Page Size Extension (Pentium+)
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// 0: 4KByte pages (typical)
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// 1: 4MByte or 2MByte pages
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// bit 5: PAE, Physical Address Extension (Pentium Pro+)
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// 0: 32bit physical addresses
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// 1: 36bit physical addresses
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// bit 7: PGE, Page Global Enable (Pentium Pro+)
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// The global page feature allows frequently used or shared pages
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// to be marked as global (PDE or PTE bit 8). Global pages are
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// not flushed from TLB on a task switch or write to CR3.
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// Values:
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// 0: disables global page feature
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// 1: enables global page feature
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//
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// Page size extention and physical address size extention matrix
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// ====================================================================
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// CR0.PG CR4.PAE CR4.PSE PDE.PS | page size physical address size
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// ====================================================================
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// 0 X X X | - paging disabled
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// 1 0 0 X | 4K 32bits
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// 1 0 1 0 | 4K 32bits
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// 1 0 1 1 | 4M 32bits
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// 1 1 X 0 | 4K 36bits
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// 1 1 X 1 | 2M 36bits
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// Page Directory/Table Entry format when P=0:
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// ===========================================
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//
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// 31.. 1: available
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// 0: P=0
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// Page Directory Entry format when P=1 (4-Kbyte Page Table):
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// ==========================================================
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//
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// 31..12: page table base address
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// 11.. 9: available
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// 8: G (Pentium Pro+), 0=reserved otherwise
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// 7: PS (Pentium+), 0=reserved otherwise
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// 6: 0=reserved
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// 5: A (386+)
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// 4: PCD (486+), 0=reserved otherwise
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// 3: PWT (486+), 0=reserved otherwise
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// 2: U/S (386+)
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// 1: R/W (386+)
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// 0: P=1 (386+)
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// Page Table Entry format when P=1 (4-Kbyte Page):
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// ================================================
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//
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// 31..12: page base address
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// 11.. 9: available
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// 8: G (Pentium Pro+), 0=reserved otherwise
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// 7: 0=reserved
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// 6: D (386+)
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// 5: A (386+)
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// 4: PCD (486+), 0=reserved otherwise
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// 3: PWT (486+), 0=reserved otherwise
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// 2: U/S (386+)
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// 1: R/W (386+)
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// 0: P=1 (386+)
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// Page Directory/Table Entry Fields Defined:
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// ==========================================
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// G: Global flag
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// Indiciates a global page when set. When a page is marked
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// global and the PGE flag in CR4 is set, the page table or
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// directory entry for the page is not invalidated in the TLB
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// when CR3 is loaded or a task switch occurs. Only software
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// clears and sets this flag. For page directory entries that
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// point to page tables, this flag is ignored and the global
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// characteristics of a page are set in the page table entries.
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//
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// PS: Page Size flag
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// Only used in page directory entries. When PS=0, the page
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// size is 4KBytes and the page directory entry points to a
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// page table. When PS=1, the page size is 4MBytes for
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// normal 32-bit addressing and 2MBytes if extended physical
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// addressing
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//
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// D: Dirty bit:
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// Processor sets the Dirty bit in the 2nd-level page table before a
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// write operation to an address mapped by that page table entry.
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// Dirty bit in directory entries is undefined.
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//
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// A: Accessed bit:
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// Processor sets the Accessed bits in both levels of page tables before
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// a read/write operation to a page.
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//
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// PCD: Page level Cache Disable
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// Controls caching of individual pages or page tables.
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// This allows a per-page based mechanism to disable caching, for
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// those pages which contained memory mapped IO, or otherwise
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// should not be cached. Processor ignores this flag if paging
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// is not used (CR0.PG=0) or the cache disable bit is set (CR0.CD=1).
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// Values:
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// 0: page or page table can be cached
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// 1: page or page table is not cached (prevented)
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//
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// PWT: Page level Write Through
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// Controls the write-through or write-back caching policy of individual
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// pages or page tables. Processor ignores this flag if paging
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// is not used (CR0.PG=0) or the cache disable bit is set (CR0.CD=1).
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// Values:
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// 0: write-back caching
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// 1: write-through caching
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//
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// U/S: User/Supervisor level
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// 0: Supervisor level - for the OS, drivers, etc.
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// 1: User level - application code and data
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//
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// R/W: Read/Write access
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// 0: read-only access
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// 1: read/write access
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//
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// P: Present
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// 0: Not present
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// 1: Present
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// ==========================================
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// Combined page directory/page table protection:
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// ==============================================
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// There is one column for the combined effect on a 386
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// and one column for the combined effect on a 486+ CPU.
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//
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// +----------------+-----------------+----------------+----------------+
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// | Page Directory| Page Table | Combined 386 | Combined 486+ |
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// |Privilege Type | Privilege Type | Privilege Type| Privilege Type|
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// |----------------+-----------------+----------------+----------------|
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// |User R | User R | User R | User R |
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// |User R | User RW | User R | User R |
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// |User RW | User R | User R | User R |
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// |User RW | User RW | User RW | User RW |
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// |User R | Supervisor R | User R | Supervisor RW |
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// |User R | Supervisor RW | User R | Supervisor RW |
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// |User RW | Supervisor R | User R | Supervisor RW |
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// |User RW | Supervisor RW | User RW | Supervisor RW |
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// |Supervisor R | User R | User R | Supervisor RW |
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// |Supervisor R | User RW | User R | Supervisor RW |
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// |Supervisor RW | User R | User R | Supervisor RW |
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// |Supervisor RW | User RW | User RW | Supervisor RW |
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// |Supervisor R | Supervisor R | Supervisor RW | Supervisor RW |
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// |Supervisor R | Supervisor RW | Supervisor RW | Supervisor RW |
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// |Supervisor RW | Supervisor R | Supervisor RW | Supervisor RW |
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// |Supervisor RW | Supervisor RW | Supervisor RW | Supervisor RW |
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// +----------------+-----------------+----------------+----------------+
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// Page Fault Error Code Format:
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// =============================
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//
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// bits 31..4: Reserved
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// bit 3: RSVD (Pentium Pro+)
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// 0: fault caused by reserved bits set to 1 in a page directory
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// when the PSE or PAE flags in CR4 are set to 1
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// 1: fault was not caused by reserved bit violation
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// bit 2: U/S (386+)
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// 0: fault originated when in supervior mode
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// 1: fault originated when in user mode
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// bit 1: R/W (386+)
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// 0: access causing the fault was a read
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// 1: access causing the fault was a write
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// bit 0: P (386+)
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// 0: fault caused by a nonpresent page
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// 1: fault caused by a page level protection violation
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// Some paging related notes:
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// ==========================
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//
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// - When the processor is running in supervisor level, all pages are both
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// readable and writable (write-protect ignored). When running at user
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// level, only pages which belong to the user level are accessible;
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// read/write & read-only are readable, read/write are writable.
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//
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// - If the Present bit is 0 in either level of page table, an
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// access which uses these entries will generate a page fault.
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//
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// - (A)ccess bit is used to report read or write access to a page
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// or 2nd level page table.
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//
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// - (D)irty bit is used to report write access to a page.
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//
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// - Processor running at CPL=0,1,2 maps to U/S=0
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// Processor running at CPL=3 maps to U/S=1
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//
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// - Pentium+ processors have separate TLB's for data and instruction caches
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// - Pentium Pro+ processors maintain separate 4K and 4M TLBs.
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#endif
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#if BX_SUPPORT_PAGING
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#define BX_INVALID_TLB_ENTRY 0xffffffff
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#if BX_CPU_LEVEL >= 4
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# define BX_PRIV_CHECK_SIZE 32
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#else
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# define BX_PRIV_CHECK_SIZE 16
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#endif
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// The 'priv_check' array is used to decide if the current access
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// has the proper paging permissions. An index is formed, based
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// on parameters such as the access type and level, the write protect
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// flag and values cached in the TLB. The format of the index into this
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// array is:
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//
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// |4 |3 |2 |1 |0 |
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// |wp|us|us|rw|rw|
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// | | | | |
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// | | | | +---> r/w of current access
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// | | +--+------> u/s,r/w combined of page dir & table (cached)
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// | +------------> u/s of current access
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// +---------------> Current CR0.wp value
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//
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// The TLB cache holds the following info, from which the above
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// fields can efficiently be extracted to facilitate a privilege check:
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//
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// |4 |3 |2 |1 |0 |
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// | | |us|rw|D |
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// | | |
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// | | +---> Dirty bit from PTE (not used for privilege check)
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// +--+------> u/s,r/w combined of page dir & table
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//
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//
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// The rest of the fields are taken from current access parameters
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// and the write-protect field:
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//
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// |4 |3 |2 |1 |0 |
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// |wp|us| | |rw|
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// | | |
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// | | +---> r/w of current access
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// | |
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// | +------------> u/s of current access
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// +---------------> Current CR0.wp value
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static unsigned priv_check[BX_PRIV_CHECK_SIZE];
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void
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BX_CPU_C::enable_paging(void)
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{
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TLB_flush();
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if (bx_dbg.paging) BX_INFO(("enable_paging():"));
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//BX_DEBUG(( "enable_paging():-------------------------" ));
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}
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void
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BX_CPU_C::disable_paging(void)
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{
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TLB_flush();
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if (bx_dbg.paging) BX_INFO(("disable_paging():"));
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}
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void
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BX_CPU_C::CR3_change(Bit32u value32)
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{
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if (bx_dbg.paging) {
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BX_INFO(("CR3_change(): flush TLB cache"));
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BX_INFO(("Page Directory Base %08x", (unsigned) value32));
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}
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// flush TLB even if value does not change
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TLB_flush();
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BX_CPU_THIS_PTR cr3 = value32;
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}
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void
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BX_CPU_C::TLB_init(void)
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{
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// Called to initialize the TLB upon startup.
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// Unconditional initialization of all TLB entries.
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#if BX_USE_TLB
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unsigned i;
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unsigned wp, us_combined, rw_combined, us_current, rw_current;
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for (i=0; i<BX_TLB_SIZE; i++) {
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BX_CPU_THIS_PTR TLB.entry[i].lpf = BX_INVALID_TLB_ENTRY;
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}
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//
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// Setup privilege check matrix.
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//
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for (i=0; i<BX_PRIV_CHECK_SIZE; i++) {
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wp = (i & 0x10) >> 4;
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us_current = (i & 0x08) >> 3;
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us_combined = (i & 0x04) >> 2;
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rw_combined = (i & 0x02) >> 1;
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rw_current = (i & 0x01) >> 0;
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if (wp) { // when write protect on
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if (us_current > us_combined) // user access, supervisor page
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priv_check[i] = 0;
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else if (rw_current > rw_combined) // RW access, RO page
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priv_check[i] = 0;
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else
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priv_check[i] = 1;
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}
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else { // when write protect off
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if (us_current == 0) // Supervisor mode access, anything goes
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priv_check[i] = 1;
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else {
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// user mode access
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if (us_combined == 0) // user access, supervisor Page
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priv_check[i] = 0;
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else if (rw_current > rw_combined) // RW access, RO page
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priv_check[i] = 0;
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else
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priv_check[i] = 1;
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}
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}
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}
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#endif // #if BX_USE_TLB
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}
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void
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BX_CPU_C::TLB_flush(void)
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{
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#if BX_USE_TLB
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for (unsigned i=0; i<BX_TLB_SIZE; i++) {
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BX_CPU_THIS_PTR TLB.entry[i].lpf = BX_INVALID_TLB_ENTRY;
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}
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#endif // #if BX_USE_TLB
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invalidate_prefetch_q();
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}
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void
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BX_CPU_C::TLB_clear(void)
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{
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#if BX_USE_TLB
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for (unsigned i=0; i<BX_TLB_SIZE; i++) {
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BX_CPU_THIS_PTR TLB.entry[i].lpf = BX_INVALID_TLB_ENTRY;
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}
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#endif // #if BX_USE_TLB
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}
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void
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BX_CPU_C::INVLPG(BxInstruction_t* i)
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{
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#if BX_CPU_LEVEL >= 4
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invalidate_prefetch_q();
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// Operand must not be a register
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if (i->mod == 0xc0) {
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BX_INFO(("INVLPG: op is a register"));
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UndefinedOpcode(i);
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}
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// Can not be executed in v8086 mode
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if (v8086_mode())
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exception(BX_GP_EXCEPTION, 0, 0);
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// Protected instruction: CPL0 only
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if (BX_CPU_THIS_PTR cr0.pe) {
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if (CPL!=0) {
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BX_INFO(("INVLPG: CPL!=0"));
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exception(BX_GP_EXCEPTION, 0, 0);
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}
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}
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#if BX_USE_TLB
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// Just clear the entire TLB, ugh!
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TLB_clear();
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#endif // BX_USE_TLB
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BX_INSTR_TLB_CNTRL(BX_INSTR_INVLPG, 0);
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#else
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// not supported on < 486
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UndefinedOpcode(i);
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#endif
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}
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// Translate a linear address to a physical address, for
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// a data access (D)
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Bit32u
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BX_CPU_C::dtranslate_linear(Bit32u laddress, unsigned pl, unsigned rw)
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{
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Bit32u lpf, ppf, poffset, TLB_index, error_code, paddress;
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Bit32u pde, pde_addr;
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Bit32u pte, pte_addr;
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unsigned priv_index;
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Boolean is_rw;
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Bit32u combined_access, new_combined_access;
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lpf = laddress & 0xfffff000; // linear page frame
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poffset = laddress & 0x00000fff; // physical offset
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TLB_index = BX_TLB_INDEX_OF(lpf);
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is_rw = (rw>=BX_WRITE); // write or r-m-w
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if (BX_CPU_THIS_PTR TLB.entry[TLB_index].lpf == lpf) {
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paddress = BX_CPU_THIS_PTR TLB.entry[TLB_index].ppf | poffset;
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combined_access = BX_CPU_THIS_PTR TLB.entry[TLB_index].combined_access;
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priv_check:
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priv_index =
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#if BX_CPU_LEVEL >= 4
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(BX_CPU_THIS_PTR cr0.wp<<4) | // bit 4
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#endif
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(pl<<3) | // bit 3
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(combined_access & 0x06) | // bit 2,1
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is_rw; // bit 0
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if (priv_check[priv_index]) {
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// Operation has proper privilege.
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// See if A/D bits need updating.
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//BW !! a read access does not do any updates, patched load
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new_combined_access = combined_access | is_rw;
|
||
if (new_combined_access == combined_access) {
|
||
// A/D bits already up-to-date
|
||
return(paddress);
|
||
}
|
||
|
||
// A/D bits need updating first
|
||
BX_CPU_THIS_PTR TLB.entry[TLB_index].combined_access = new_combined_access;
|
||
pte_addr = BX_CPU_THIS_PTR TLB.entry[TLB_index].pte_addr;
|
||
BX_CPU_THIS_PTR mem->read_physical(this, pte_addr, 4, &pte); // get old 4kPTE/4mPDE
|
||
pte |= 0x20 | (is_rw << 6);
|
||
BX_CPU_THIS_PTR mem->write_physical(this, pte_addr, 4, &pte); // write updated 4kPTE/4mPDE
|
||
return(paddress);
|
||
}
|
||
|
||
// Protection violation
|
||
error_code = 0xfffffff9; // RSVD=1, P=1
|
||
goto page_fault_check;
|
||
}
|
||
|
||
// Get page dir entry
|
||
pde_addr = (BX_CPU_THIS_PTR cr3 & 0xfffff000) |
|
||
((laddress & 0xffc00000) >> 20);
|
||
BX_CPU_THIS_PTR mem->read_physical(this, pde_addr, 4, &pde);
|
||
if ( !(pde & 0x01) ) {
|
||
// Page Directory Entry NOT present
|
||
error_code = 0xfffffff8; // RSVD=1, P=0
|
||
goto page_fault_not_present;
|
||
}
|
||
|
||
// check for 4Mbyte page
|
||
|
||
if ((pde & 0x80) && (BX_CPU_THIS_PTR cr4 & 0x10)) { // check for 4M page and make sure it's enabled
|
||
combined_access = pde & 0x06; // combined access is just access from the pde
|
||
ppf = (pde & 0xFFC00000) | (laddress & 0x003FF000); // make up the physical frame number
|
||
pte_addr = pde_addr; // A/D bits in same place as a real pte
|
||
}
|
||
|
||
// normal 4Kbyte page
|
||
|
||
else {
|
||
|
||
// Get page table entry
|
||
pte_addr = (pde & 0xfffff000) |
|
||
((laddress & 0x003ff000) >> 10);
|
||
BX_CPU_THIS_PTR mem->read_physical(this, pte_addr, 4, &pte);
|
||
|
||
// update PDE if A bit was not set before
|
||
if ( !(pde & 0x20) ) {
|
||
pde |= 0x20;
|
||
BX_CPU_THIS_PTR mem->write_physical(this, pde_addr, 4, &pde);
|
||
}
|
||
|
||
if ( !(pte & 0x01) ) {
|
||
// Page Table Entry NOT present
|
||
error_code = 0xfffffff8; // RSVD=1, P=0
|
||
goto page_fault_not_present;
|
||
}
|
||
|
||
//BW added: update PTE if A bit was not set before
|
||
if ( !(pte & 0x20) ) {
|
||
pte |= 0x20;
|
||
BX_CPU_THIS_PTR mem->write_physical(this, pte_addr, 4, &pte);
|
||
}
|
||
|
||
// 386 and 486+ have different bahaviour for combining
|
||
// privilege from PDE and PTE.
|
||
#if BX_CPU_LEVEL == 3
|
||
combined_access = (pde | pte) & 0x04; // U/S
|
||
combined_access |= (pde & pte) & 0x02; // R/W
|
||
#else // 486+
|
||
combined_access = (pde & pte) & 0x06; // U/S and R/W
|
||
#endif
|
||
|
||
ppf = pte & 0xfffff000;
|
||
}
|
||
|
||
// Calculate physical memory address and fill in TLB cache entry
|
||
|
||
paddress = ppf | poffset;
|
||
|
||
BX_CPU_THIS_PTR TLB.entry[TLB_index].lpf = lpf;
|
||
BX_CPU_THIS_PTR TLB.entry[TLB_index].ppf = ppf;
|
||
BX_CPU_THIS_PTR TLB.entry[TLB_index].pte_addr = pte_addr;
|
||
BX_CPU_THIS_PTR TLB.entry[TLB_index].combined_access = combined_access;
|
||
|
||
goto priv_check;
|
||
|
||
|
||
page_fault_check:
|
||
// (mch) Define RMW_WRITES for old behavior
|
||
#if !defined(RMW_WRITES)
|
||
/* (mch) Ok, so we know it's a page fault. It the access is a
|
||
read-modify-write access we check if the read faults, if it
|
||
does then we (optionally) do not set the write bit */
|
||
if (rw == BX_RW) {
|
||
priv_index =
|
||
#if BX_CPU_LEVEL >= 4
|
||
(BX_CPU_THIS_PTR cr0.wp<<4) | // bit 4
|
||
#endif
|
||
(pl<<3) | // bit 3
|
||
(combined_access & 0x06) | // bit 2,1
|
||
0; // bit 0 (read)
|
||
if (!priv_check[priv_index]) {
|
||
// Fault on read
|
||
is_rw = 0;
|
||
}
|
||
}
|
||
#endif /* RMW_WRITES */
|
||
goto page_fault_proper;
|
||
|
||
page_fault_not_present:
|
||
#if !defined(RMW_WRITES)
|
||
if (rw == BX_RW)
|
||
is_rw = 0;
|
||
#endif /* RMW_WRITES */
|
||
goto page_fault_proper;
|
||
|
||
page_fault_proper:
|
||
error_code |= (pl << 2) | (is_rw << 1);
|
||
BX_CPU_THIS_PTR cr2 = laddress;
|
||
// invalidate entry - we can get away without maintaining A bit in PTE
|
||
// if we don't maintain TLB entries without it set.
|
||
BX_CPU_THIS_PTR TLB.entry[TLB_index].lpf = BX_INVALID_TLB_ENTRY;
|
||
exception(BX_PF_EXCEPTION, error_code, 0);
|
||
return(0); // keep compiler happy
|
||
}
|
||
|
||
|
||
// Translate a linear address to a physical address, for
|
||
// an instruction fetch access (I)
|
||
|
||
Bit32u
|
||
BX_CPU_C::itranslate_linear(Bit32u laddress, unsigned pl)
|
||
{
|
||
Bit32u lpf, ppf, poffset, TLB_index, error_code, paddress;
|
||
Bit32u pde, pde_addr;
|
||
Bit32u pte, pte_addr;
|
||
unsigned priv_index;
|
||
Bit32u combined_access;
|
||
|
||
lpf = laddress & 0xfffff000; // linear page frame
|
||
poffset = laddress & 0x00000fff; // physical offset
|
||
TLB_index = BX_TLB_INDEX_OF(lpf);
|
||
|
||
|
||
if (BX_CPU_THIS_PTR TLB.entry[TLB_index].lpf == lpf) {
|
||
paddress = BX_CPU_THIS_PTR TLB.entry[TLB_index].ppf | poffset;
|
||
combined_access = BX_CPU_THIS_PTR TLB.entry[TLB_index].combined_access;
|
||
priv_check:
|
||
priv_index =
|
||
#if BX_CPU_LEVEL >= 4
|
||
(BX_CPU_THIS_PTR cr0.wp<<4) | // bit 4
|
||
#endif
|
||
(pl<<3) | // bit 3
|
||
(combined_access & 0x06); // bit 2,1
|
||
// bit 0 == 0
|
||
|
||
if (priv_check[priv_index]) {
|
||
// Operation has proper privilege.
|
||
return(paddress);
|
||
}
|
||
|
||
// Protection violation
|
||
error_code = 0xfffffff9; // RSVD=1, P=1
|
||
goto page_fault;
|
||
}
|
||
|
||
// Get page dir entry
|
||
pde_addr = (BX_CPU_THIS_PTR cr3 & 0xfffff000) |
|
||
((laddress & 0xffc00000) >> 20);
|
||
BX_CPU_THIS_PTR mem->read_physical(this, pde_addr, 4, &pde);
|
||
if ( !(pde & 0x01) ) {
|
||
// Page Directory Entry NOT present
|
||
error_code = 0xfffffff8; // RSVD=1, P=0
|
||
goto page_fault;
|
||
}
|
||
|
||
// check for 4Mbyte page
|
||
|
||
if ((pde & 0x80) && (BX_CPU_THIS_PTR cr4 & 0x10)) { // check for 4M page and make sure it's enabled
|
||
combined_access = pde & 0x06; // combined access is just access from the pde
|
||
ppf = (pde & 0xFFC00000) | (laddress & 0x003FF000); // make up the physical frame number
|
||
pte_addr = pde_addr; // A/D bits in same place as a real pte
|
||
}
|
||
|
||
|
||
else {
|
||
// normal 4Kbyte page
|
||
|
||
// Get page table entry
|
||
pte_addr = (pde & 0xfffff000) |
|
||
((laddress & 0x003ff000) >> 10);
|
||
BX_CPU_THIS_PTR mem->read_physical(this, pte_addr, 4, &pte);
|
||
|
||
// update PDE if A bit was not set before
|
||
if ( !(pde & 0x20) ) {
|
||
pde |= 0x20;
|
||
BX_CPU_THIS_PTR mem->write_physical(this, pde_addr, 4, &pde);
|
||
}
|
||
|
||
if ( !(pte & 0x01) ) {
|
||
// Page Table Entry NOT present
|
||
error_code = 0xfffffff8; // RSVD=1, P=0
|
||
goto page_fault;
|
||
}
|
||
|
||
//BW added: update PTE if A bit was not set before
|
||
if ( !(pte & 0x20) ) {
|
||
pte |= 0x20;
|
||
BX_CPU_THIS_PTR mem->write_physical(this, pte_addr, 4, &pte);
|
||
}
|
||
|
||
// 386 and 486+ have different bahaviour for combining
|
||
// privilege from PDE and PTE.
|
||
#if BX_CPU_LEVEL == 3
|
||
combined_access = (pde | pte) & 0x04; // U/S
|
||
combined_access |= (pde & pte) & 0x02; // R/W
|
||
#else // 486+
|
||
combined_access = (pde & pte) & 0x06; // U/S and R/W
|
||
#endif
|
||
|
||
ppf = pte & 0xfffff000;
|
||
}
|
||
|
||
paddress = ppf | poffset;
|
||
|
||
BX_CPU_THIS_PTR TLB.entry[TLB_index].lpf = lpf;
|
||
BX_CPU_THIS_PTR TLB.entry[TLB_index].ppf = ppf;
|
||
BX_CPU_THIS_PTR TLB.entry[TLB_index].pte_addr = pte_addr;
|
||
BX_CPU_THIS_PTR TLB.entry[TLB_index].combined_access = combined_access;
|
||
goto priv_check;
|
||
|
||
|
||
page_fault:
|
||
error_code |= (pl << 2);
|
||
BX_CPU_THIS_PTR cr2 = laddress;
|
||
// invalidate entry - we can get away without maintaining A bit in PTE
|
||
// if we don't maintain TLB entries without it set.
|
||
BX_CPU_THIS_PTR TLB.entry[TLB_index].lpf = BX_INVALID_TLB_ENTRY;
|
||
exception(BX_PF_EXCEPTION, error_code, 0);
|
||
return(0); // keep compiler happy
|
||
}
|
||
|
||
|
||
#if BX_DEBUGGER || BX_DISASM || BX_INSTRUMENTATION
|
||
|
||
void
|
||
BX_CPU_C::dbg_xlate_linear2phy(Bit32u laddress, Bit32u *phy, Boolean *valid)
|
||
{
|
||
Bit32u lpf, ppf, poffset, TLB_index, paddress;
|
||
Bit32u pde, pde_addr;
|
||
Bit32u pte, pte_addr;
|
||
|
||
if (BX_CPU_THIS_PTR cr0.pg == 0) {
|
||
*phy = laddress;
|
||
*valid = 1;
|
||
return;
|
||
}
|
||
|
||
lpf = laddress & 0xfffff000; // linear page frame
|
||
poffset = laddress & 0x00000fff; // physical offset
|
||
TLB_index = BX_TLB_INDEX_OF(lpf);
|
||
|
||
// see if page is in the TLB first
|
||
if (BX_CPU_THIS_PTR TLB.entry[TLB_index].lpf == lpf) {
|
||
paddress = BX_CPU_THIS_PTR TLB.entry[TLB_index].ppf | poffset;
|
||
*phy = paddress;
|
||
*valid = 1;
|
||
return;
|
||
}
|
||
|
||
// Get page dir entry
|
||
pde_addr = (BX_CPU_THIS_PTR cr3 & 0xfffff000) |
|
||
((laddress & 0xffc00000) >> 20);
|
||
BX_CPU_THIS_PTR mem->read_physical(this, pde_addr, 4, &pde);
|
||
if ( !(pde & 0x01) ) {
|
||
// Page Directory Entry NOT present
|
||
goto page_fault;
|
||
}
|
||
|
||
// Get page table entry
|
||
pte_addr = (pde & 0xfffff000) |
|
||
((laddress & 0x003ff000) >> 10);
|
||
BX_CPU_THIS_PTR mem->read_physical(this, pte_addr, 4, &pte);
|
||
if ( !(pte & 0x01) ) {
|
||
// Page Table Entry NOT present
|
||
goto page_fault;
|
||
}
|
||
|
||
ppf = pte & 0xfffff000;
|
||
paddress = ppf | poffset;
|
||
|
||
*phy = paddress;
|
||
*valid = 1;
|
||
return;
|
||
|
||
page_fault:
|
||
*phy = 0;
|
||
*valid = 0;
|
||
return;
|
||
}
|
||
#endif
|
||
|
||
|
||
|
||
void
|
||
BX_CPU_C::access_linear(Bit32u laddress, unsigned length, unsigned pl,
|
||
unsigned rw, void *data)
|
||
{
|
||
Bit32u mod4096;
|
||
unsigned xlate_rw;
|
||
|
||
|
||
#if BX_X86_DEBUGGER
|
||
if ( BX_CPU_THIS_PTR dr7 & 0x000000ff ) {
|
||
// Only compare debug registers if any breakpoints are enabled
|
||
Bit32u dr6_bits;
|
||
unsigned opa, opb;
|
||
opa = BX_HWDebugMemRW; // Read or Write always compares vs 11b
|
||
if (rw==BX_READ) // only compares vs 11b
|
||
opb = opa;
|
||
else // BX_WRITE or BX_RW; also compare vs 01b
|
||
opb = BX_HWDebugMemW;
|
||
dr6_bits = hwdebug_compare(laddress, length, opa, opb);
|
||
if (dr6_bits) {
|
||
BX_CPU_THIS_PTR debug_trap |= dr6_bits;
|
||
BX_CPU_THIS_PTR async_event = 1;
|
||
}
|
||
}
|
||
#endif
|
||
|
||
if (rw==BX_RW) {
|
||
xlate_rw = BX_RW;
|
||
rw = BX_READ;
|
||
}
|
||
else {
|
||
xlate_rw = rw;
|
||
}
|
||
|
||
|
||
// perhaps put this check before all code which calls this function,
|
||
// so we don't have to here
|
||
|
||
if (BX_CPU_THIS_PTR cr0.pg) {
|
||
/* check for reference across multiple pages */
|
||
mod4096 = laddress & 0x00000fff;
|
||
if ( (mod4096 + length) <= 4096 ) {
|
||
// Bit32u paddress1;
|
||
|
||
/* access within single page */
|
||
BX_CPU_THIS_PTR address_xlation.paddress1 = dtranslate_linear(laddress, pl, xlate_rw);
|
||
BX_CPU_THIS_PTR address_xlation.pages = 1;
|
||
|
||
if (rw == BX_READ) {
|
||
BX_INSTR_LIN_READ(laddress, BX_CPU_THIS_PTR address_xlation.paddress1, length);
|
||
BX_CPU_THIS_PTR mem->read_physical(this, BX_CPU_THIS_PTR address_xlation.paddress1, length, data);
|
||
}
|
||
else {
|
||
BX_INSTR_LIN_WRITE(laddress, BX_CPU_THIS_PTR address_xlation.paddress1, length);
|
||
BX_CPU_THIS_PTR mem->write_physical(this, BX_CPU_THIS_PTR address_xlation.paddress1, length, data);
|
||
}
|
||
return;
|
||
}
|
||
else {
|
||
// access across 2 pages
|
||
BX_CPU_THIS_PTR address_xlation.paddress1 = dtranslate_linear(laddress, pl, xlate_rw);
|
||
BX_CPU_THIS_PTR address_xlation.len1 = 4096 - mod4096;
|
||
BX_CPU_THIS_PTR address_xlation.len2 = length - BX_CPU_THIS_PTR address_xlation.len1;
|
||
BX_CPU_THIS_PTR address_xlation.pages = 2;
|
||
|
||
BX_CPU_THIS_PTR address_xlation.paddress2 = dtranslate_linear(laddress + BX_CPU_THIS_PTR address_xlation.len1, pl, xlate_rw);
|
||
|
||
#ifdef BX_LITTLE_ENDIAN
|
||
if (rw == BX_READ) {
|
||
BX_INSTR_LIN_READ(laddress,
|
||
BX_CPU_THIS_PTR address_xlation.paddress1,
|
||
BX_CPU_THIS_PTR address_xlation.len1);
|
||
BX_CPU_THIS_PTR mem->read_physical(this, BX_CPU_THIS_PTR address_xlation.paddress1,
|
||
BX_CPU_THIS_PTR address_xlation.len1, data);
|
||
BX_INSTR_LIN_READ(laddress + BX_CPU_THIS_PTR address_xlation.len1,
|
||
BX_CPU_THIS_PTR address_xlation.paddress2,
|
||
BX_CPU_THIS_PTR address_xlation.len2);
|
||
BX_CPU_THIS_PTR mem->read_physical(this, BX_CPU_THIS_PTR address_xlation.paddress2,
|
||
BX_CPU_THIS_PTR address_xlation.len2,
|
||
((Bit8u*)data) + BX_CPU_THIS_PTR address_xlation.len1);
|
||
}
|
||
else {
|
||
BX_INSTR_LIN_WRITE(laddress,
|
||
BX_CPU_THIS_PTR address_xlation.paddress1,
|
||
BX_CPU_THIS_PTR address_xlation.len1);
|
||
BX_CPU_THIS_PTR mem->write_physical(this, BX_CPU_THIS_PTR address_xlation.paddress1,
|
||
BX_CPU_THIS_PTR address_xlation.len1, data);
|
||
BX_INSTR_LIN_WRITE(laddress + BX_CPU_THIS_PTR address_xlation.len1,
|
||
BX_CPU_THIS_PTR address_xlation.paddress2,
|
||
BX_CPU_THIS_PTR address_xlation.len2);
|
||
BX_CPU_THIS_PTR mem->write_physical(this, BX_CPU_THIS_PTR address_xlation.paddress2,
|
||
BX_CPU_THIS_PTR address_xlation.len2,
|
||
((Bit8u*)data) + BX_CPU_THIS_PTR address_xlation.len1);
|
||
}
|
||
|
||
#else // BX_BIG_ENDIAN
|
||
if (rw == BX_READ) {
|
||
BX_INSTR_LIN_READ(laddress,
|
||
BX_CPU_THIS_PTR address_xlation.paddress1,
|
||
BX_CPU_THIS_PTR address_xlation.len1);
|
||
BX_CPU_THIS_PTR mem->read_physical(this, BX_CPU_THIS_PTR address_xlation.paddress1,
|
||
BX_CPU_THIS_PTR address_xlation.len1,
|
||
((Bit8u*)data) + (length - BX_CPU_THIS_PTR address_xlation.len1));
|
||
BX_INSTR_LIN_READ(laddress + BX_CPU_THIS_PTR address_xlation.len1,
|
||
BX_CPU_THIS_PTR address_xlation.paddress2,
|
||
BX_CPU_THIS_PTR address_xlation.len2);
|
||
BX_CPU_THIS_PTR mem->read_physical(this, BX_CPU_THIS_PTR address_xlation.paddress2,
|
||
BX_CPU_THIS_PTR address_xlation.len2, data);
|
||
}
|
||
else {
|
||
BX_INSTR_LIN_WRITE(laddress,
|
||
BX_CPU_THIS_PTR address_xlation.paddress1,
|
||
BX_CPU_THIS_PTR address_xlation.len1);
|
||
BX_CPU_THIS_PTR mem->write_physical(this, BX_CPU_THIS_PTR address_xlation.paddress1,
|
||
BX_CPU_THIS_PTR address_xlation.len1,
|
||
((Bit8u*)data) + (length - BX_CPU_THIS_PTR address_xlation.len1));
|
||
BX_INSTR_LIN_WRITE(laddress + BX_CPU_THIS_PTR address_xlation.len1,
|
||
BX_CPU_THIS_PTR address_xlation.paddress2,
|
||
BX_CPU_THIS_PTR address_xlation.len2);
|
||
BX_CPU_THIS_PTR mem->write_physical(this, BX_CPU_THIS_PTR address_xlation.paddress2,
|
||
BX_CPU_THIS_PTR address_xlation.len2, data);
|
||
}
|
||
#endif
|
||
|
||
return;
|
||
}
|
||
}
|
||
else {
|
||
// paging off, pass linear address thru to physical
|
||
if (rw == BX_READ) {
|
||
BX_INSTR_LIN_READ(laddress, laddress, length);
|
||
BX_CPU_THIS_PTR mem->read_physical(this, laddress, length, data);
|
||
}
|
||
else {
|
||
BX_INSTR_LIN_WRITE(laddress, laddress, length);
|
||
BX_CPU_THIS_PTR mem->write_physical(this, laddress, length, data);
|
||
}
|
||
return;
|
||
}
|
||
}
|
||
|
||
|
||
|
||
|
||
|
||
|
||
|
||
|
||
#else // BX_SUPPORT_PAGING
|
||
|
||
// stub functions for non-support of paging
|
||
void
|
||
BX_CPU_C::enable_paging(void)
|
||
{
|
||
BX_PANIC(("enable_paging(): not implemented"));
|
||
}
|
||
|
||
void
|
||
BX_CPU_C::disable_paging(void)
|
||
{
|
||
BX_PANIC(("disable_paging() called"));
|
||
}
|
||
|
||
void
|
||
BX_CPU_C::CR3_change(Bit32u value32)
|
||
{
|
||
BX_INFO(("CR3_change(): flush TLB cache"));
|
||
BX_INFO(("Page Directory Base %08x", (unsigned) value32));
|
||
}
|
||
|
||
|
||
void
|
||
BX_CPU_C::access_linear(Bit32u laddress, unsigned length, unsigned pl,
|
||
unsigned rw, void *data)
|
||
{
|
||
/* perhaps put this check before all code which calls this function,
|
||
* so we don't have to here
|
||
*/
|
||
if (BX_CPU_THIS_PTR cr0.pg == 0) {
|
||
if (rw == BX_READ)
|
||
BX_CPU_THIS_PTR mem->read_physical(this, laddress, length, data);
|
||
else
|
||
BX_CPU_THIS_PTR mem->write_physical(this, laddress, length, data);
|
||
return;
|
||
}
|
||
|
||
BX_PANIC(("access_linear: paging not supported"));
|
||
}
|
||
|
||
void
|
||
BX_CPU_C::INVLPG(BxInstruction_t* i)
|
||
{}
|
||
|
||
#endif // BX_SUPPORT_PAGING
|