367 lines
18 KiB
C++
367 lines
18 KiB
C++
/////////////////////////////////////////////////////////////////////////
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// $Id$
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (c) 2013 Stanislav Shwartsman
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// Written by Stanislav Shwartsman [sshwarts at sourceforge net]
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//
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// This library is free software; you can redistribute it and/or
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// modify it under the terms of the GNU Lesser General Public
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// License as published by the Free Software Foundation; either
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// version 2 of the License, or (at your option) any later version.
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//
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// This library is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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// Lesser General Public License for more details.
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//
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// You should have received a copy of the GNU Lesser General Public
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// License along with this library; if not, write to the Free Software
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// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA B 02110-1301 USA
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//
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/////////////////////////////////////////////////////////////////////////
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#define NEED_CPU_REG_SHORTCUTS 1
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#include "bochs.h"
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#include "cpu.h"
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#define LOG_THIS BX_CPU_THIS_PTR
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#if BX_SUPPORT_EVEX
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extern void mxcsr_to_softfloat_status_word(float_status_t &status, bx_mxcsr_t mxcsr);
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#include "fpu/softfloat-compare.h"
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#include "simd_int.h"
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#include "simd_pfp.h"
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#define EVEX_OP_PACKED_SINGLE(HANDLER, func) \
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C:: HANDLER (bxInstruction_c *i) \
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{ \
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BxPackedAvxRegister op1 = BX_READ_AVX_REG(i->src1()), op2 = BX_READ_AVX_REG(i->src2()); \
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unsigned mask = BX_READ_16BIT_OPMASK(i->opmask()); \
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unsigned len = i->getVL(); \
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\
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float_status_t status; \
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mxcsr_to_softfloat_status_word(status, MXCSR); \
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softfloat_status_word_rc_override(status, i); \
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\
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for (unsigned n=0, tmp_mask = mask; n < len; n++, tmp_mask >>= 4) \
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(func)(&op1.vmm128(n), &op2.vmm128(n), status, tmp_mask); \
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\
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check_exceptionsSSE(status.float_exception_flags); \
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\
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if (! i->isZeroMasking()) { \
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for (unsigned n=0; n < len; n++, mask >>= 4) \
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xmm_blendps(&BX_READ_AVX_REG_LANE(i->dst(), n), &op1.vmm128(n), mask); \
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\
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BX_CLEAR_AVX_REGZ(i->dst(), len); \
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} \
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else { \
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BX_WRITE_AVX_REGZ(i->dst(), op1, len); \
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} \
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\
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BX_NEXT_INSTR(i); \
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}
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EVEX_OP_PACKED_SINGLE(VADDPS_MASK_VpsHpsWpsR, xmm_addps_mask)
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EVEX_OP_PACKED_SINGLE(VSUBPS_MASK_VpsHpsWpsR, xmm_subps_mask)
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EVEX_OP_PACKED_SINGLE(VMULPS_MASK_VpsHpsWpsR, xmm_mulps_mask)
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EVEX_OP_PACKED_SINGLE(VDIVPS_MASK_VpsHpsWpsR, xmm_divps_mask)
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EVEX_OP_PACKED_SINGLE(VMAXPS_MASK_VpsHpsWpsR, xmm_maxps_mask)
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EVEX_OP_PACKED_SINGLE(VMINPS_MASK_VpsHpsWpsR, xmm_minps_mask)
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#define EVEX_OP_PACKED_DOUBLE(HANDLER, func) \
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C:: HANDLER (bxInstruction_c *i) \
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{ \
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BxPackedAvxRegister op1 = BX_READ_AVX_REG(i->src1()), op2 = BX_READ_AVX_REG(i->src2()); \
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unsigned mask = BX_READ_8BIT_OPMASK(i->opmask()); \
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unsigned len = i->getVL(); \
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\
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float_status_t status; \
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mxcsr_to_softfloat_status_word(status, MXCSR); \
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softfloat_status_word_rc_override(status, i); \
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\
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for (unsigned n=0, tmp_mask = mask; n < len; n++, tmp_mask >>= 2) \
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(func)(&op1.vmm128(n), &op2.vmm128(n), status, tmp_mask); \
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\
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check_exceptionsSSE(status.float_exception_flags); \
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\
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if (! i->isZeroMasking()) { \
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for (unsigned n=0; n < len; n++, mask >>= 2) \
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xmm_blendpd(&BX_READ_AVX_REG_LANE(i->dst(), n), &op1.vmm128(n), mask); \
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\
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BX_CLEAR_AVX_REGZ(i->dst(), len); \
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} \
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else { \
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BX_WRITE_AVX_REGZ(i->dst(), op1, len); \
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} \
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\
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BX_NEXT_INSTR(i); \
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}
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EVEX_OP_PACKED_DOUBLE(VADDPD_MASK_VpdHpdWpdR, xmm_addpd_mask)
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EVEX_OP_PACKED_DOUBLE(VSUBPD_MASK_VpdHpdWpdR, xmm_subpd_mask)
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EVEX_OP_PACKED_DOUBLE(VMULPD_MASK_VpdHpdWpdR, xmm_mulpd_mask)
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EVEX_OP_PACKED_DOUBLE(VDIVPD_MASK_VpdHpdWpdR, xmm_divpd_mask)
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EVEX_OP_PACKED_DOUBLE(VMAXPD_MASK_VpdHpdWpdR, xmm_maxpd_mask)
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EVEX_OP_PACKED_DOUBLE(VMINPD_MASK_VpdHpdWpdR, xmm_minpd_mask)
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#define EVEX_OP_SCALAR_SINGLE(HANDLER, func) \
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C:: HANDLER (bxInstruction_c *i) \
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{ \
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BxPackedXmmRegister op1 = BX_READ_XMM_REG(i->src1()); \
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\
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if (BX_SCALAR_ELEMENT_MASK(i->opmask())) { \
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float32 op2 = BX_READ_XMM_REG_LO_DWORD(i->src2()); \
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\
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float_status_t status; \
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mxcsr_to_softfloat_status_word(status, MXCSR); \
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softfloat_status_word_rc_override(status, i); \
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op1.xmm32u(0) = (func)(op1.xmm32u(0), op2, status); \
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check_exceptionsSSE(status.float_exception_flags); \
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} \
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else { \
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if (i->isZeroMasking()) \
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op1.xmm32u(0) = 0; \
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else \
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op1.xmm32u(0) = BX_READ_XMM_REG_LO_DWORD(i->dst()); \
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} \
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\
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BX_WRITE_XMM_REG_CLEAR_HIGH(i->dst(), op1); \
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BX_NEXT_INSTR(i); \
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}
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EVEX_OP_SCALAR_SINGLE(VADDSS_MASK_VssHpsWssR, float32_add)
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EVEX_OP_SCALAR_SINGLE(VSUBSS_MASK_VssHpsWssR, float32_sub)
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EVEX_OP_SCALAR_SINGLE(VMULSS_MASK_VssHpsWssR, float32_mul)
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EVEX_OP_SCALAR_SINGLE(VDIVSS_MASK_VssHpsWssR, float32_div)
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EVEX_OP_SCALAR_SINGLE(VMINSS_MASK_VssHpsWssR, float32_min)
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EVEX_OP_SCALAR_SINGLE(VMAXSS_MASK_VssHpsWssR, float32_max)
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#define EVEX_OP_SCALAR_DOUBLE(HANDLER, func) \
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C:: HANDLER (bxInstruction_c *i) \
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{ \
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BxPackedXmmRegister op1 = BX_READ_XMM_REG(i->src1()); \
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\
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if (BX_SCALAR_ELEMENT_MASK(i->opmask())) { \
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float64 op2 = BX_READ_XMM_REG_LO_QWORD(i->src2()); \
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\
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float_status_t status; \
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mxcsr_to_softfloat_status_word(status, MXCSR); \
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softfloat_status_word_rc_override(status, i); \
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op1.xmm64u(0) = (func)(op1.xmm64u(0), op2, status); \
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check_exceptionsSSE(status.float_exception_flags); \
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} \
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else { \
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if (i->isZeroMasking()) \
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op1.xmm64u(0) = 0; \
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else \
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op1.xmm64u(0) = BX_READ_XMM_REG_LO_QWORD(i->dst()); \
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} \
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\
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BX_WRITE_XMM_REG_CLEAR_HIGH(i->dst(), op1); \
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BX_NEXT_INSTR(i); \
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}
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EVEX_OP_SCALAR_DOUBLE(VADDSD_MASK_VsdHpdWsdR, float64_add)
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EVEX_OP_SCALAR_DOUBLE(VSUBSD_MASK_VsdHpdWsdR, float64_sub)
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EVEX_OP_SCALAR_DOUBLE(VMULSD_MASK_VsdHpdWsdR, float64_mul)
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EVEX_OP_SCALAR_DOUBLE(VDIVSD_MASK_VsdHpdWsdR, float64_div)
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EVEX_OP_SCALAR_DOUBLE(VMINSD_MASK_VsdHpdWsdR, float64_min)
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EVEX_OP_SCALAR_DOUBLE(VMAXSD_MASK_VsdHpdWsdR, float64_max)
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VSQRTPS_MASK_VpsWpsR(bxInstruction_c *i)
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{
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BxPackedAvxRegister op = BX_READ_AVX_REG(i->src());
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unsigned mask = BX_READ_16BIT_OPMASK(i->opmask());
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unsigned len = i->getVL();
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float_status_t status;
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mxcsr_to_softfloat_status_word(status, MXCSR);
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softfloat_status_word_rc_override(status, i);
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for (unsigned n=0, tmp_mask = mask; n < len; n++, tmp_mask >>= 4)
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xmm_sqrtps_mask(&op.vmm128(n), status, tmp_mask);
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check_exceptionsSSE(status.float_exception_flags);
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if (! i->isZeroMasking()) {
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for (unsigned n=0; n < len; n++, mask >>= 4)
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xmm_blendps(&BX_READ_AVX_REG_LANE(i->dst(), n), &op.vmm128(n), mask);
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BX_CLEAR_AVX_REGZ(i->dst(), len);
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}
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else {
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BX_WRITE_AVX_REGZ(i->dst(), op, len);
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}
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BX_NEXT_INSTR(i);
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}
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VSQRTPD_MASK_VpdWpdR(bxInstruction_c *i)
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{
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BxPackedAvxRegister op = BX_READ_AVX_REG(i->src());
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unsigned mask = BX_READ_8BIT_OPMASK(i->opmask());
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unsigned len = i->getVL();
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float_status_t status;
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mxcsr_to_softfloat_status_word(status, MXCSR);
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softfloat_status_word_rc_override(status, i);
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for (unsigned n=0, tmp_mask = mask; n < len; n++, tmp_mask >>= 2)
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xmm_sqrtpd_mask(&op.vmm128(n), status, tmp_mask);
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check_exceptionsSSE(status.float_exception_flags);
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if (! i->isZeroMasking()) {
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for (unsigned n=0; n < len; n++, mask >>= 2)
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xmm_blendpd(&BX_READ_AVX_REG_LANE(i->dst(), n), &op.vmm128(n), mask);
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BX_CLEAR_AVX_REGZ(i->dst(), len);
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}
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else {
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BX_WRITE_AVX_REGZ(i->dst(), op, len);
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}
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BX_NEXT_INSTR(i);
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}
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VSQRTSS_MASK_VssHpsWssR(bxInstruction_c *i)
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{
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BxPackedXmmRegister op1 = BX_READ_XMM_REG(i->src1());
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if (BX_SCALAR_ELEMENT_MASK(i->opmask())) {
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float32 op2 = BX_READ_XMM_REG_LO_DWORD(i->src2());
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float_status_t status;
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mxcsr_to_softfloat_status_word(status, MXCSR);
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softfloat_status_word_rc_override(status, i);
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op1.xmm32u(0) = float32_sqrt(op2, status);
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check_exceptionsSSE(status.float_exception_flags);
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}
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else {
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if (i->isZeroMasking())
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op1.xmm32u(0) = 0;
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else
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op1.xmm32u(0) = BX_READ_XMM_REG_LO_DWORD(i->dst());
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}
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BX_WRITE_XMM_REG_CLEAR_HIGH(i->dst(), op1);
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BX_NEXT_INSTR(i);
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}
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VSQRTSD_MASK_VsdHpdWsdR(bxInstruction_c *i)
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{
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BxPackedXmmRegister op1 = BX_READ_XMM_REG(i->src1());
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if (BX_SCALAR_ELEMENT_MASK(i->opmask())) {
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float64 op2 = BX_READ_XMM_REG_LO_QWORD(i->src2());
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float_status_t status;
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mxcsr_to_softfloat_status_word(status, MXCSR);
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softfloat_status_word_rc_override(status, i);
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op1.xmm64u(0) = float64_sqrt(op2, status);
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check_exceptionsSSE(status.float_exception_flags);
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}
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else {
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if (i->isZeroMasking())
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op1.xmm64u(0) = 0;
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else
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op1.xmm64u(0) = BX_READ_XMM_REG_LO_QWORD(i->dst());
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}
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BX_WRITE_XMM_REG_CLEAR_HIGH(i->dst(), op1);
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BX_NEXT_INSTR(i);
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}
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extern float32_compare_method avx_compare32[32];
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extern float64_compare_method avx_compare64[32];
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VCMPPS_MASK_KGwHpsWpsIbR(bxInstruction_c *i)
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{
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BxPackedAvxRegister op1 = BX_READ_AVX_REG(i->src1()), op2 = BX_READ_AVX_REG(i->src2());
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unsigned num_elements = 4 * i->getVL();
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Bit32u opmask = i->opmask() ? BX_READ_8BIT_OPMASK(i->opmask()) : (Bit32u) -1;
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Bit32u result = 0;
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float_status_t status;
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mxcsr_to_softfloat_status_word(status, MXCSR);
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softfloat_status_word_rc_override(status, i);
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int ib = i->Ib() & 0x1F;
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for (unsigned n=0, mask = 0x1; n < num_elements; n++, mask <<= 1) {
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if (opmask & mask) {
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if (avx_compare32[ib](op1.vmm32u(n), op2.vmm32u(n), status)) result |= mask;
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}
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}
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check_exceptionsSSE(status.float_exception_flags);
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BX_WRITE_OPMASK(i->dst(), result);
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BX_NEXT_INSTR(i);
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}
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VCMPPD_MASK_KGbHpdWpdIbR(bxInstruction_c *i)
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{
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BxPackedAvxRegister op1 = BX_READ_AVX_REG(i->src1()), op2 = BX_READ_AVX_REG(i->src2());
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unsigned num_elements = 2 * i->getVL();
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Bit32u opmask = i->opmask() ? BX_READ_8BIT_OPMASK(i->opmask()) : (Bit32u) -1;
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Bit32u result = 0;
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float_status_t status;
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mxcsr_to_softfloat_status_word(status, MXCSR);
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softfloat_status_word_rc_override(status, i);
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int ib = i->Ib() & 0x1F;
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for (unsigned n=0, mask = 0x1; n < num_elements; n++, mask <<= 1) {
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if (opmask & mask) {
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if (avx_compare64[ib](op1.vmm64u(n), op2.vmm64u(n), status)) result |= mask;
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}
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}
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check_exceptionsSSE(status.float_exception_flags);
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BX_WRITE_OPMASK(i->dst(), result);
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BX_NEXT_INSTR(i);
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}
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VCMPSD_MASK_KGbHsdWsdIbR(bxInstruction_c *i)
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{
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Bit32u result = 0;
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if (! i->opmask() || BX_SCALAR_ELEMENT_MASK(i->opmask())) {
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float64 op1 = BX_READ_XMM_REG_LO_QWORD(i->src1());
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float64 op2 = BX_READ_XMM_REG_LO_QWORD(i->src2());
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float_status_t status;
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mxcsr_to_softfloat_status_word(status, MXCSR);
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softfloat_status_word_rc_override(status, i);
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if (avx_compare64[i->Ib() & 0x1F](op1, op2, status)) result = 1;
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check_exceptionsSSE(status.float_exception_flags);
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}
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BX_WRITE_OPMASK(i->dst(), result);
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BX_NEXT_INSTR(i);
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}
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VCMPSS_MASK_KGbHssWssIbR(bxInstruction_c *i)
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{
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Bit32u result = 0;
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if (! i->opmask() || BX_SCALAR_ELEMENT_MASK(i->opmask())) {
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float32 op1 = BX_READ_XMM_REG_LO_DWORD(i->src1());
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float32 op2 = BX_READ_XMM_REG_LO_DWORD(i->src2());
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float_status_t status;
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mxcsr_to_softfloat_status_word(status, MXCSR);
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softfloat_status_word_rc_override(status, i);
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if (avx_compare32[i->Ib() & 0x1F](op1, op2, status)) result = 1;
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check_exceptionsSSE(status.float_exception_flags);
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}
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BX_WRITE_OPMASK(i->dst(), result);
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BX_NEXT_INSTR(i);
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}
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#endif
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