374 lines
13 KiB
C++
374 lines
13 KiB
C++
/////////////////////////////////////////////////////////////////////////
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// $Id$
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (c) 2012-2015 Stanislav Shwartsman
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// Written by Stanislav Shwartsman [sshwarts at sourceforge net]
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//
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// This library is free software; you can redistribute it and/or
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// modify it under the terms of the GNU Lesser General Public
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// License as published by the Free Software Foundation; either
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// version 2 of the License, or (at your option) any later version.
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//
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// This library is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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// Lesser General Public License for more details.
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//
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// You should have received a copy of the GNU Lesser General Public
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// License along with this library; if not, write to the Free Software
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// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA B 02110-1301 USA
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//
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/////////////////////////////////////////////////////////////////////////
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#define NEED_CPU_REG_SHORTCUTS 1
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#include "bochs.h"
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#include "cpu.h"
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#define LOG_THIS BX_CPU_THIS_PTR
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#include "cpustats.h"
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void BX_CPP_AttrRegparmN(2) BX_CPU_C::stackPrefetch(bx_address offset, unsigned len)
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{
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bx_address laddr;
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unsigned pageOffset;
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INC_STACK_PREFETCH_STAT(stackPrefetch);
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BX_CPU_THIS_PTR espHostPtr = 0; // initialize with NULL pointer
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BX_CPU_THIS_PTR espPageWindowSize = 0;
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len--;
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#if BX_SUPPORT_X86_64
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if (long64_mode() || (BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.valid & SegAccessWOK4G)) {
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laddr = offset;
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pageOffset = PAGE_OFFSET(offset);
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// canonical violations will miss the TLB below
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if (pageOffset + len >= 4096) // don't care for page split accesses
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return;
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BX_CPU_THIS_PTR espPageWindowSize = 4096;
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}
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else
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#endif
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{
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laddr = get_laddr32(BX_SEG_REG_SS, (Bit32u) offset);
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pageOffset = PAGE_OFFSET(laddr);
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if (pageOffset + len >= 4096) // don't care for page split accesses
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return;
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Bit32u limit = BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.limit_scaled;
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Bit32u pageStart = (Bit32u) offset - pageOffset;
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if (! BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.valid) {
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BX_ERROR(("stackPrefetch: SS not valid"));
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exception(BX_SS_EXCEPTION, 0);
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}
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BX_ASSERT(BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.p);
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BX_ASSERT(IS_DATA_SEGMENT_WRITEABLE(BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.type));
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// check that the begining of the page is within stack segment limits
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// problem can happen with EXPAND DOWN segments
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if (IS_DATA_SEGMENT_EXPAND_DOWN(BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.type)) {
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Bit32u upper_limit;
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if (BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.d_b)
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upper_limit = 0xffffffff;
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else
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upper_limit = 0x0000ffff;
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if (offset <= limit || offset > upper_limit || (upper_limit - offset) < len) {
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BX_ERROR(("stackPrefetch(%d): access [0x%08x] > SS.limit [0x%08x] ED", len+1, (Bit32u) offset, limit));
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exception(BX_SS_EXCEPTION, 0);
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}
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// check that the begining of the page is within stack segment limits
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// handle correctly the wrap corner case for EXPAND DOWN
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Bit32u pageEnd = pageStart + 0xfff;
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if (pageStart > limit && pageStart < pageEnd) {
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BX_CPU_THIS_PTR espPageWindowSize = 4096;
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if ((upper_limit - offset) < (4096 - pageOffset))
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BX_CPU_THIS_PTR espPageWindowSize = (Bit32u)(upper_limit - offset + 1);
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}
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}
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else {
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if (offset > (limit - len) || len > limit) {
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BX_ERROR(("stackPrefetch(%d): access [0x%08x] > SS.limit [0x%08x]", len+1, (Bit32u) offset, limit));
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exception(BX_SS_EXCEPTION, 0);
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}
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if (pageStart <= limit) {
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BX_CPU_THIS_PTR espPageWindowSize = 4096;
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if ((limit - offset) < (4096 - pageOffset))
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BX_CPU_THIS_PTR espPageWindowSize = (Bit32u)(limit - offset + 1);
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}
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}
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}
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Bit64u lpf = LPFOf(laddr);
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bx_TLB_entry *tlbEntry = BX_TLB_ENTRY_OF(laddr, 0);
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if (tlbEntry->lpf == lpf) {
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// See if the TLB entry privilege level allows us write access from this CPL
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// Assuming that we always can read if write access is OK
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if (isWriteOK(tlbEntry, USER_PL)) {
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BX_CPU_THIS_PTR espPageBias = (bx_address) pageOffset - offset;
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BX_CPU_THIS_PTR pAddrStackPage = tlbEntry->ppf;
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BX_CPU_THIS_PTR espHostPtr = (Bit8u*) tlbEntry->hostPageAddr;
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#if BX_SUPPORT_MEMTYPE
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BX_CPU_THIS_PTR espPageMemtype = tlbEntry->get_memtype();
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#endif
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#if BX_SUPPORT_SMP == 0
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BX_CPU_THIS_PTR espPageFineGranularityMapping = pageWriteStampTable.getFineGranularityMapping(tlbEntry->ppf);
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#endif
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}
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}
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if (! BX_CPU_THIS_PTR espHostPtr || BX_CPU_THIS_PTR espPageWindowSize < 7)
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BX_CPU_THIS_PTR espPageWindowSize = 0;
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else
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BX_CPU_THIS_PTR espPageWindowSize -= 7;
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}
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void BX_CPP_AttrRegparmN(2) BX_CPU_C::stack_write_byte(bx_address offset, Bit8u data)
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{
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bx_address espBiased = offset + BX_CPU_THIS_PTR espPageBias;
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if (espBiased >= BX_CPU_THIS_PTR espPageWindowSize) {
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stackPrefetch(offset, 1);
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espBiased = offset + BX_CPU_THIS_PTR espPageBias;
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}
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if (BX_CPU_THIS_PTR espHostPtr) {
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Bit8u *hostPageAddr = (Bit8u*)(BX_CPU_THIS_PTR espHostPtr + espBiased);
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bx_phy_address pAddr = BX_CPU_THIS_PTR pAddrStackPage + espBiased;
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BX_NOTIFY_LIN_MEMORY_ACCESS(get_laddr(BX_SEG_REG_SS, offset), pAddr, 1,
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MEMTYPE(BX_CPU_THIS_PTR espPageMemtype), BX_WRITE, (Bit8u*) &data);
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#if BX_SUPPORT_SMP == 0
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if (BX_CPU_THIS_PTR espPageFineGranularityMapping)
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#endif
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pageWriteStampTable.decWriteStamp(pAddr, 1);
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*hostPageAddr = data;
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}
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else {
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write_virtual_byte(BX_SEG_REG_SS, offset, data);
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}
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}
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void BX_CPP_AttrRegparmN(2) BX_CPU_C::stack_write_word(bx_address offset, Bit16u data)
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{
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bx_address espBiased = offset + BX_CPU_THIS_PTR espPageBias;
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if (espBiased >= BX_CPU_THIS_PTR espPageWindowSize) {
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stackPrefetch(offset, 2);
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espBiased = offset + BX_CPU_THIS_PTR espPageBias;
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}
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if (BX_CPU_THIS_PTR espHostPtr) {
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Bit16u *hostPageAddr = (Bit16u*)(BX_CPU_THIS_PTR espHostPtr + espBiased);
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bx_phy_address pAddr = BX_CPU_THIS_PTR pAddrStackPage + espBiased;
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#if BX_CPU_LEVEL >= 4 && BX_SUPPORT_ALIGNMENT_CHECK
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if (BX_CPU_THIS_PTR alignment_check() && (pAddr & 1) != 0) {
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BX_ERROR(("stack_write_word(): #AC misaligned access"));
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exception(BX_AC_EXCEPTION, 0);
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}
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#endif
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BX_NOTIFY_LIN_MEMORY_ACCESS(get_laddr(BX_SEG_REG_SS, offset), pAddr, 2,
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MEMTYPE(BX_CPU_THIS_PTR espPageMemtype), BX_WRITE, (Bit8u*) &data);
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#if BX_SUPPORT_SMP == 0
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if (BX_CPU_THIS_PTR espPageFineGranularityMapping)
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#endif
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pageWriteStampTable.decWriteStamp(pAddr, 2);
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WriteHostWordToLittleEndian(hostPageAddr, data);
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}
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else {
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write_virtual_word(BX_SEG_REG_SS, offset, data);
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}
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}
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void BX_CPP_AttrRegparmN(2) BX_CPU_C::stack_write_dword(bx_address offset, Bit32u data)
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{
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bx_address espBiased = offset + BX_CPU_THIS_PTR espPageBias;
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if (espBiased >= BX_CPU_THIS_PTR espPageWindowSize) {
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stackPrefetch(offset, 4);
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espBiased = offset + BX_CPU_THIS_PTR espPageBias;
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}
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if (BX_CPU_THIS_PTR espHostPtr) {
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Bit32u *hostPageAddr = (Bit32u*)(BX_CPU_THIS_PTR espHostPtr + espBiased);
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bx_phy_address pAddr = BX_CPU_THIS_PTR pAddrStackPage + espBiased;
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#if BX_CPU_LEVEL >= 4 && BX_SUPPORT_ALIGNMENT_CHECK
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if (BX_CPU_THIS_PTR alignment_check() && (pAddr & 3) != 0) {
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BX_ERROR(("stack_write_dword(): #AC misaligned access"));
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exception(BX_AC_EXCEPTION, 0);
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}
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#endif
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BX_NOTIFY_LIN_MEMORY_ACCESS(get_laddr(BX_SEG_REG_SS, offset), pAddr, 4,
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MEMTYPE(BX_CPU_THIS_PTR espPageMemtype), BX_WRITE, (Bit8u*) &data);
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#if BX_SUPPORT_SMP == 0
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if (BX_CPU_THIS_PTR espPageFineGranularityMapping)
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#endif
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pageWriteStampTable.decWriteStamp(pAddr, 4);
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WriteHostDWordToLittleEndian(hostPageAddr, data);
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}
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else {
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write_virtual_dword(BX_SEG_REG_SS, offset, data);
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}
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}
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void BX_CPP_AttrRegparmN(2) BX_CPU_C::stack_write_qword(bx_address offset, Bit64u data)
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{
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bx_address espBiased = offset + BX_CPU_THIS_PTR espPageBias;
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if (espBiased >= BX_CPU_THIS_PTR espPageWindowSize) {
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stackPrefetch(offset, 8);
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espBiased = offset + BX_CPU_THIS_PTR espPageBias;
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}
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if (BX_CPU_THIS_PTR espHostPtr) {
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Bit64u *hostPageAddr = (Bit64u*)(BX_CPU_THIS_PTR espHostPtr + espBiased);
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bx_phy_address pAddr = BX_CPU_THIS_PTR pAddrStackPage + espBiased;
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#if BX_CPU_LEVEL >= 4 && BX_SUPPORT_ALIGNMENT_CHECK
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if (BX_CPU_THIS_PTR alignment_check() && (pAddr & 7) != 0) {
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BX_ERROR(("stack_write_qword(): #AC misaligned access"));
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exception(BX_AC_EXCEPTION, 0);
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}
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#endif
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BX_NOTIFY_LIN_MEMORY_ACCESS(get_laddr(BX_SEG_REG_SS, offset), pAddr, 8,
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MEMTYPE(BX_CPU_THIS_PTR espPageMemtype), BX_WRITE, (Bit8u*) &data);
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#if BX_SUPPORT_SMP == 0
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if (BX_CPU_THIS_PTR espPageFineGranularityMapping)
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#endif
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pageWriteStampTable.decWriteStamp(pAddr, 8);
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WriteHostQWordToLittleEndian(hostPageAddr, data);
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}
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else {
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write_virtual_qword(BX_SEG_REG_SS, offset, data);
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}
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}
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Bit8u BX_CPP_AttrRegparmN(1) BX_CPU_C::stack_read_byte(bx_address offset)
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{
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bx_address espBiased = offset + BX_CPU_THIS_PTR espPageBias;
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if (espBiased >= BX_CPU_THIS_PTR espPageWindowSize) {
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stackPrefetch(offset, 1);
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espBiased = offset + BX_CPU_THIS_PTR espPageBias;
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}
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if (BX_CPU_THIS_PTR espHostPtr) {
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Bit8u *hostPageAddr = (Bit8u*)(BX_CPU_THIS_PTR espHostPtr + espBiased), data;
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data = *hostPageAddr;
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BX_NOTIFY_LIN_MEMORY_ACCESS(get_laddr(BX_SEG_REG_SS, offset),
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(BX_CPU_THIS_PTR pAddrStackPage + espBiased), 1,
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MEMTYPE(BX_CPU_THIS_PTR espPageMemtype), BX_READ, (Bit8u*) &data);
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return data;
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}
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else {
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return read_virtual_byte(BX_SEG_REG_SS, offset);
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}
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}
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Bit16u BX_CPP_AttrRegparmN(1) BX_CPU_C::stack_read_word(bx_address offset)
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{
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bx_address espBiased = offset + BX_CPU_THIS_PTR espPageBias;
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if (espBiased >= BX_CPU_THIS_PTR espPageWindowSize) {
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stackPrefetch(offset, 2);
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espBiased = offset + BX_CPU_THIS_PTR espPageBias;
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}
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if (BX_CPU_THIS_PTR espHostPtr) {
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Bit16u *hostPageAddr = (Bit16u*)(BX_CPU_THIS_PTR espHostPtr + espBiased), data;
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#if BX_CPU_LEVEL >= 4 && BX_SUPPORT_ALIGNMENT_CHECK
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if (BX_CPU_THIS_PTR alignment_check()) {
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bx_phy_address pAddr = BX_CPU_THIS_PTR pAddrStackPage + espBiased;
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if (pAddr & 1) {
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BX_ERROR(("stack_read_word(): #AC misaligned access"));
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exception(BX_AC_EXCEPTION, 0);
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}
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}
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#endif
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ReadHostWordFromLittleEndian(hostPageAddr, data);
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BX_NOTIFY_LIN_MEMORY_ACCESS(get_laddr(BX_SEG_REG_SS, offset),
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(BX_CPU_THIS_PTR pAddrStackPage + espBiased), 2,
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MEMTYPE(BX_CPU_THIS_PTR espPageMemtype), BX_READ, (Bit8u*) &data);
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return data;
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}
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else {
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return read_virtual_word(BX_SEG_REG_SS, offset);
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}
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}
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Bit32u BX_CPP_AttrRegparmN(1) BX_CPU_C::stack_read_dword(bx_address offset)
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{
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bx_address espBiased = offset + BX_CPU_THIS_PTR espPageBias;
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if (espBiased >= BX_CPU_THIS_PTR espPageWindowSize) {
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stackPrefetch(offset, 4);
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espBiased = offset + BX_CPU_THIS_PTR espPageBias;
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}
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if (BX_CPU_THIS_PTR espHostPtr) {
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Bit32u *hostPageAddr = (Bit32u*)(BX_CPU_THIS_PTR espHostPtr + espBiased), data;
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#if BX_CPU_LEVEL >= 4 && BX_SUPPORT_ALIGNMENT_CHECK
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if (BX_CPU_THIS_PTR alignment_check()) {
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bx_phy_address pAddr = BX_CPU_THIS_PTR pAddrStackPage + espBiased;
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if (pAddr & 3) {
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BX_ERROR(("stack_read_dword(): #AC misaligned access"));
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exception(BX_AC_EXCEPTION, 0);
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}
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}
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#endif
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ReadHostDWordFromLittleEndian(hostPageAddr, data);
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BX_NOTIFY_LIN_MEMORY_ACCESS(get_laddr(BX_SEG_REG_SS, offset),
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(BX_CPU_THIS_PTR pAddrStackPage + espBiased), 4,
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MEMTYPE(BX_CPU_THIS_PTR espPageMemtype), BX_READ, (Bit8u*) &data);
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return data;
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}
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else {
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return read_virtual_dword(BX_SEG_REG_SS, offset);
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}
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}
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Bit64u BX_CPP_AttrRegparmN(1) BX_CPU_C::stack_read_qword(bx_address offset)
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{
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bx_address espBiased = offset + BX_CPU_THIS_PTR espPageBias;
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if (espBiased >= BX_CPU_THIS_PTR espPageWindowSize) {
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stackPrefetch(offset, 8);
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espBiased = offset + BX_CPU_THIS_PTR espPageBias;
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}
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if (BX_CPU_THIS_PTR espHostPtr) {
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Bit64u *hostPageAddr = (Bit64u*)(BX_CPU_THIS_PTR espHostPtr + espBiased), data;
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#if BX_CPU_LEVEL >= 4 && BX_SUPPORT_ALIGNMENT_CHECK
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if (BX_CPU_THIS_PTR alignment_check()) {
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bx_phy_address pAddr = BX_CPU_THIS_PTR pAddrStackPage + espBiased;
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if (pAddr & 7) {
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BX_ERROR(("stack_read_qword(): #AC misaligned access"));
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exception(BX_AC_EXCEPTION, 0);
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}
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}
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#endif
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ReadHostQWordFromLittleEndian(hostPageAddr, data);
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BX_NOTIFY_LIN_MEMORY_ACCESS(get_laddr(BX_SEG_REG_SS, offset),
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(BX_CPU_THIS_PTR pAddrStackPage + espBiased), 8,
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MEMTYPE(BX_CPU_THIS_PTR espPageMemtype), BX_READ, (Bit8u*) &data);
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return data;
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}
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else {
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return read_virtual_qword(BX_SEG_REG_SS, offset);
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}
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}
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