463 lines
14 KiB
C++
463 lines
14 KiB
C++
/////////////////////////////////////////////////////////////////////////
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// $Id$
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (c) 2011-2012 Stanislav Shwartsman
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// Written by Stanislav Shwartsman [sshwarts at sourceforge net]
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//
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// This library is free software; you can redistribute it and/or
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// modify it under the terms of the GNU Lesser General Public
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// License as published by the Free Software Foundation; either
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// version 2 of the License, or (at your option) any later version.
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//
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// This library is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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// Lesser General Public License for more details.
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//
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// You should have received a copy of the GNU Lesser General Public
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// License along with this library; if not, write to the Free Software
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// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA B 02110-1301 USA
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/////////////////////////////////////////////////////////////////////////
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#define NEED_CPU_REG_SHORTCUTS 1
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#include "bochs.h"
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#include "cpu.h"
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#define LOG_THIS BX_CPU_THIS_PTR
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#include "iodev/iodev.h"
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bx_bool BX_CPU_C::handleWaitForEvent(void)
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{
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// For one processor, pass the time as quickly as possible until
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// an interrupt wakes up the CPU.
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while (1)
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{
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if ((BX_CPU_INTR && (BX_CPU_THIS_PTR get_IF() || BX_CPU_THIS_PTR activity_state == BX_ACTIVITY_STATE_MWAIT_IF)) ||
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#if BX_SUPPORT_VMX >= 2
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BX_CPU_THIS_PTR pending_vmx_timer_expired ||
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#endif
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BX_CPU_THIS_PTR pending_NMI || BX_CPU_THIS_PTR pending_SMI || BX_CPU_THIS_PTR pending_INIT)
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{
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// interrupt ends the HALT condition
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#if BX_SUPPORT_MONITOR_MWAIT
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if (BX_CPU_THIS_PTR activity_state >= BX_ACTIVITY_STATE_MWAIT)
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BX_CPU_THIS_PTR monitor.reset_monitor();
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#endif
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BX_CPU_THIS_PTR activity_state = BX_ACTIVITY_STATE_ACTIVE;
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BX_CPU_THIS_PTR inhibit_mask = 0; // clear inhibits for after resume
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break;
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}
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if (BX_CPU_THIS_PTR activity_state == BX_ACTIVITY_STATE_ACTIVE) {
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// happens also when MWAIT monitor was hit
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// BX_INFO(("handleWaitForEvent: reset detected in HLT state"));
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break;
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}
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if (BX_HRQ && BX_DBG_ASYNC_DMA) {
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// handle DMA also when CPU is halted
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DEV_dma_raise_hlda();
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}
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// for multiprocessor simulation, even if this CPU is halted we still
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// must give the others a chance to simulate. If an interrupt has
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// arrived, then clear the HALT condition; otherwise just return from
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// the CPU loop with stop_reason STOP_CPU_HALTED.
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#if BX_SUPPORT_SMP
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if (BX_SMP_PROCESSORS > 1) {
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// HALT condition remains, return so other CPUs have a chance
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#if BX_DEBUGGER
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BX_CPU_THIS_PTR stop_reason = STOP_CPU_HALTED;
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#endif
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return 1; // Return to caller of cpu_loop.
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}
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#endif
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#if BX_DEBUGGER
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if (bx_guard.interrupt_requested)
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return 1; // Return to caller of cpu_loop.
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#endif
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if (bx_pc_system.kill_bochs_request) {
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// setting kill_bochs_request causes the cpu loop to return ASAP.
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return 1; // Return to caller of cpu_loop.
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}
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BX_TICKN(10); // when in HLT run time faster for single CPU
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}
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return 0;
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}
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BX_CPP_INLINE bx_bool BX_CPU_C::interrupts_enabled(void)
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{
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#if BX_SUPPORT_SVM
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if (BX_CPU_THIS_PTR in_svm_guest && SVM_V_INTR_MASKING) return SVM_HOST_IF;
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#endif
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return BX_CPU_THIS_PTR get_IF();
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}
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void BX_CPU_C::InterruptAcknowledge(void)
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{
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Bit8u vector;
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#if BX_SUPPORT_SVM
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if (BX_CPU_THIS_PTR in_svm_guest) {
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if (SVM_INTERCEPT(SVM_INTERCEPT0_INTR)) Svm_Vmexit(SVM_VMEXIT_INTR);
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}
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#endif
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#if BX_SUPPORT_VMX
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VMexit_ExtInterrupt();
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#endif
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// NOTE: similar code in ::take_irq()
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#if BX_SUPPORT_APIC
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if (BX_CPU_THIS_PTR lapic.INTR)
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vector = BX_CPU_THIS_PTR lapic.acknowledge_int();
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else
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#endif
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// if no local APIC, always acknowledge the PIC.
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vector = DEV_pic_iac(); // may set INTR with next interrupt
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BX_CPU_THIS_PTR EXT = 1; /* external event */
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#if BX_SUPPORT_VMX
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VMexit_Event(0, BX_EXTERNAL_INTERRUPT, vector, 0, 0);
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#endif
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BX_INSTR_HWINTERRUPT(BX_CPU_ID, vector,
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BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value, RIP);
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interrupt(vector, BX_EXTERNAL_INTERRUPT, 0, 0);
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BX_CPU_THIS_PTR prev_rip = RIP; // commit new RIP
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BX_CPU_THIS_PTR EXT = 0;
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}
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#if BX_SUPPORT_SVM
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void BX_CPU_C::VirtualInterruptAcknowledge(void)
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{
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Bit8u vector = SVM_V_INTR_VECTOR;
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if (SVM_INTERCEPT(SVM_INTERCEPT0_VINTR)) Svm_Vmexit(SVM_VMEXIT_VINTR);
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SVM_V_IRQ = 0;
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BX_CPU_THIS_PTR EXT = 1; /* external event */
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BX_INSTR_HWINTERRUPT(BX_CPU_ID, vector,
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BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value, RIP);
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interrupt(vector, BX_EXTERNAL_INTERRUPT, 0, 0);
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BX_CPU_THIS_PTR prev_rip = RIP; // commit new RIP
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BX_CPU_THIS_PTR EXT = 0;
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}
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#endif
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bx_bool BX_CPU_C::handleAsyncEvent(void)
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{
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//
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// This area is where we process special conditions and events.
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//
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if (BX_CPU_THIS_PTR activity_state != BX_ACTIVITY_STATE_ACTIVE) {
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// For one processor, pass the time as quickly as possible until
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// an interrupt wakes up the CPU.
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if (handleWaitForEvent()) return 1;
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}
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if (bx_pc_system.kill_bochs_request) {
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// setting kill_bochs_request causes the cpu loop to return ASAP.
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return 1; // Return to caller of cpu_loop.
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}
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// Priority 1: Hardware Reset and Machine Checks
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// RESET
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// Machine Check
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// (bochs doesn't support these)
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#if BX_SUPPORT_SVM
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// debug exceptions or trap due to breakpoint register match
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// ignored and discarded if GIF == 0
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// debug traps due to EFLAGS.TF remain untouched
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if (! BX_CPU_THIS_PTR svm_gif)
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BX_CPU_THIS_PTR debug_trap &= ~BX_DEBUG_SINGLE_STEP_BIT;
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#endif
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// Priority 2: Trap on Task Switch
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// T flag in TSS is set
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if (BX_CPU_THIS_PTR debug_trap & BX_DEBUG_TRAP_TASK_SWITCH_BIT) {
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exception(BX_DB_EXCEPTION, 0); // no error, not interrupt
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}
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// Priority 3: External Hardware Interventions
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// FLUSH
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// STOPCLK
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// SMI
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// INIT
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if (BX_CPU_THIS_PTR pending_SMI && ! BX_CPU_THIS_PTR smm_mode() && SVM_GIF)
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{
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// clear SMI pending flag and disable NMI when SMM was accepted
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BX_CPU_THIS_PTR pending_SMI = 0;
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enter_system_management_mode();
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}
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if (BX_CPU_THIS_PTR pending_INIT && ! BX_CPU_THIS_PTR disable_INIT && SVM_GIF) {
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#if BX_SUPPORT_SVM
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if (BX_CPU_THIS_PTR in_svm_guest) {
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if (SVM_INTERCEPT(SVM_INTERCEPT0_INIT)) Svm_Vmexit(SVM_VMEXIT_INIT);
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}
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#endif
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#if BX_SUPPORT_VMX
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if (BX_CPU_THIS_PTR in_vmx_guest) {
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BX_ERROR(("VMEXIT: INIT pin asserted"));
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VMexit(0, VMX_VMEXIT_INIT, 0);
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}
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#endif
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// reset will clear pending INIT
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reset(BX_RESET_SOFTWARE);
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#if BX_SUPPORT_SMP
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if (BX_SMP_PROCESSORS > 1) {
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// if HALT condition remains, return so other CPUs have a chance
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if (BX_CPU_THIS_PTR activity_state != BX_ACTIVITY_STATE_ACTIVE) {
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#if BX_DEBUGGER
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BX_CPU_THIS_PTR stop_reason = STOP_CPU_HALTED;
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#endif
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return 1; // Return to caller of cpu_loop.
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}
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}
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#endif
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}
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// Priority 4: Traps on Previous Instruction
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// Breakpoints
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// Debug Trap Exceptions (TF flag set or data/IO breakpoint)
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if (! interrupts_inhibited(BX_INHIBIT_DEBUG)) {
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// A trap may be inhibited on this boundary due to an instruction which loaded SS.
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#if BX_X86_DEBUGGER
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code_breakpoint_match(get_laddr(BX_SEG_REG_CS, BX_CPU_THIS_PTR prev_rip));
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#endif
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if (BX_CPU_THIS_PTR debug_trap)
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exception(BX_DB_EXCEPTION, 0); // no error, not interrupt
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}
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// Priority 5: External Interrupts
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// VMX Preemption Timer Expired.
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// NMI Interrupts
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// Maskable Hardware Interrupts
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if (interrupts_inhibited(BX_INHIBIT_INTERRUPTS) || ! SVM_GIF) {
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// Processing external interrupts is inhibited on this
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// boundary because of certain instructions like STI.
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}
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#if BX_SUPPORT_VMX >= 2
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else if (BX_CPU_THIS_PTR in_vmx_guest && BX_CPU_THIS_PTR pending_vmx_timer_expired) {
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BX_CPU_THIS_PTR pending_vmx_timer_expired = 0;
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VMexit_PreemptionTimerExpired();
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}
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#endif
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#if BX_SUPPORT_VMX
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else if (! BX_CPU_THIS_PTR disable_NMI && BX_CPU_THIS_PTR in_vmx_guest &&
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VMEXIT(VMX_VM_EXEC_CTRL2_NMI_WINDOW_VMEXIT))
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{
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// NMI-window exiting
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BX_ERROR(("VMEXIT: NMI window exiting"));
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VMexit(0, VMX_VMEXIT_NMI_WINDOW, 0);
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}
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#endif
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else if (BX_CPU_THIS_PTR pending_NMI && ! BX_CPU_THIS_PTR disable_NMI) {
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#if BX_SUPPORT_SVM
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if (BX_CPU_THIS_PTR in_svm_guest) {
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if (SVM_INTERCEPT(SVM_INTERCEPT0_NMI)) Svm_Vmexit(SVM_VMEXIT_NMI);
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}
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#endif
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BX_CPU_THIS_PTR pending_NMI = 0;
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BX_CPU_THIS_PTR disable_NMI = 1;
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BX_CPU_THIS_PTR EXT = 1; /* external event */
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#if BX_SUPPORT_VMX
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VMexit_Event(0, BX_NMI, 2, 0, 0);
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#endif
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BX_INSTR_HWINTERRUPT(BX_CPU_ID, 2, BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value, RIP);
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interrupt(2, BX_NMI, 0, 0);
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}
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#if BX_SUPPORT_VMX
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else if (BX_CPU_THIS_PTR vmx_interrupt_window && BX_CPU_THIS_PTR get_IF()) {
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// interrupt-window exiting
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BX_DEBUG(("VMEXIT: interrupt window exiting"));
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VMexit(0, VMX_VMEXIT_INTERRUPT_WINDOW, 0);
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}
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#endif
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else if (BX_CPU_INTR && BX_DBG_ASYNC_INTR &&
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(interrupts_enabled()
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#if BX_SUPPORT_VMX
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|| (BX_CPU_THIS_PTR in_vmx_guest && PIN_VMEXIT(VMX_VM_EXEC_CTRL1_EXTERNAL_INTERRUPT_VMEXIT))
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#endif
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))
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{
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InterruptAcknowledge();
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}
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#if BX_SUPPORT_SVM
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else if (BX_CPU_THIS_PTR in_svm_guest && SVM_V_IRQ && BX_CPU_THIS_PTR get_IF() &&
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((SVM_V_INTR_PRIO > SVM_V_TPR) || SVM_V_IGNORE_TPR))
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{
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// virtual interrupt acknowledge
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VirtualInterruptAcknowledge();
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}
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#endif
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else if (BX_HRQ && BX_DBG_ASYNC_DMA) {
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// NOTE: similar code in ::take_dma()
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// assert Hold Acknowledge (HLDA) and go into a bus hold state
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DEV_dma_raise_hlda();
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}
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if (BX_CPU_THIS_PTR get_TF())
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{
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// TF is set before execution of next instruction. Schedule
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// a debug trap (#DB) after execution. After completion of
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// next instruction, the code above will invoke the trap.
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BX_CPU_THIS_PTR debug_trap |= BX_DEBUG_SINGLE_STEP_BIT;
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}
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// Priority 6: Faults from fetching next instruction
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// Code breakpoint fault
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// Code segment limit violation (priority 7 on 486/Pentium)
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// Code page fault (priority 7 on 486/Pentium)
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// (handled in main decode loop)
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// Priority 7: Faults from decoding next instruction
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// Instruction length > 15 bytes
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// Illegal opcode
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// Coprocessor not available
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// (handled in main decode loop etc)
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// Priority 8: Faults on executing an instruction
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// Floating point execution
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// Overflow
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// Bound error
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// Invalid TSS
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// Segment not present
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// Stack fault
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// General protection
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// Data page fault
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// Alignment check
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// (handled by rest of the code)
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if (!((BX_CPU_INTR && interrupts_enabled() && SVM_GIF) ||
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BX_CPU_THIS_PTR debug_trap ||
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// BX_CPU_THIS_PTR get_TF() // implies debug_trap is set
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BX_HRQ
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#if BX_SUPPORT_VMX
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|| BX_CPU_THIS_PTR vmx_interrupt_window
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|| (BX_CPU_THIS_PTR in_vmx_guest && ! BX_CPU_THIS_PTR disable_NMI &&
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VMEXIT(VMX_VM_EXEC_CTRL2_NMI_WINDOW_VMEXIT))
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#endif
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#if BX_SUPPORT_VMX >= 2
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|| BX_CPU_THIS_PTR pending_vmx_timer_expired
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#endif
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#if BX_SUPPORT_SVM
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|| (BX_CPU_THIS_PTR in_svm_guest && SVM_V_IRQ && BX_CPU_THIS_PTR get_IF() &&
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((SVM_V_INTR_PRIO > SVM_V_TPR) || SVM_V_IGNORE_TPR))
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#endif
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#if BX_X86_DEBUGGER
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// a debug code breakpoint is set in current page
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|| BX_CPU_THIS_PTR codebp
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#endif
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))
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BX_CPU_THIS_PTR async_event = 0;
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return 0; // Continue executing cpu_loop.
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}
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// Certain instructions inhibit interrupts, some debug exceptions and single-step traps.
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void BX_CPU_C::inhibit_interrupts(unsigned mask)
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{
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BX_DEBUG(("inhibit interrupts mask = %d", mask));
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BX_CPU_THIS_PTR inhibit_mask = mask;
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BX_CPU_THIS_PTR inhibit_icount = get_icount() + 1; // inhibit for next instruction
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}
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bx_bool BX_CPU_C::interrupts_inhibited(unsigned mask)
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{
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return (get_icount() <= BX_CPU_THIS_PTR inhibit_icount) && (BX_CPU_THIS_PTR inhibit_mask & mask) == mask;
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}
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void BX_CPU_C::deliver_SIPI(unsigned vector)
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{
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if (BX_CPU_THIS_PTR activity_state == BX_ACTIVITY_STATE_WAIT_FOR_SIPI) {
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BX_CPU_THIS_PTR activity_state = BX_ACTIVITY_STATE_ACTIVE;
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RIP = 0;
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load_seg_reg(&BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS], vector*0x100);
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BX_CPU_THIS_PTR disable_INIT = 0; // enable INIT pin back
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BX_INFO(("CPU %d started up at %04X:%08X by APIC",
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BX_CPU_THIS_PTR bx_cpuid, vector*0x100, EIP));
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} else {
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BX_INFO(("CPU %d started up by APIC, but was not halted at the time", BX_CPU_THIS_PTR bx_cpuid));
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}
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}
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void BX_CPU_C::deliver_INIT(void)
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{
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if (! BX_CPU_THIS_PTR disable_INIT) {
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BX_CPU_THIS_PTR pending_INIT = 1;
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BX_CPU_THIS_PTR async_event = 1;
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}
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}
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void BX_CPU_C::deliver_NMI(void)
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{
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BX_CPU_THIS_PTR pending_NMI = 1;
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BX_CPU_THIS_PTR async_event = 1;
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}
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void BX_CPU_C::deliver_SMI(void)
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{
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BX_CPU_THIS_PTR pending_SMI = 1;
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BX_CPU_THIS_PTR async_event = 1;
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}
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void BX_CPU_C::set_INTR(bx_bool value)
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{
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BX_CPU_THIS_PTR INTR = value;
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BX_CPU_THIS_PTR async_event = 1;
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}
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#if BX_DEBUGGER
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void BX_CPU_C::dbg_take_irq(void)
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{
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// NOTE: similar code in ::cpu_loop()
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if (BX_CPU_INTR && BX_CPU_THIS_PTR get_IF()) {
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if (setjmp(BX_CPU_THIS_PTR jmp_buf_env) == 0) {
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// normal return from setjmp setup
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unsigned vector = DEV_pic_iac(); // may set INTR with next interrupt
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BX_CPU_THIS_PTR EXT = 1; // external event
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BX_CPU_THIS_PTR async_event = 1; // set in case INTR is triggered
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interrupt(vector, BX_EXTERNAL_INTERRUPT, 0, 0);
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}
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}
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}
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void BX_CPU_C::dbg_force_interrupt(unsigned vector)
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{
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// Used to force simulator to take an interrupt, without
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// regard to IF
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if (setjmp(BX_CPU_THIS_PTR jmp_buf_env) == 0) {
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// normal return from setjmp setup
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BX_CPU_THIS_PTR EXT = 1; // external event
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BX_CPU_THIS_PTR async_event = 1; // probably don't need this
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interrupt(vector, BX_EXTERNAL_INTERRUPT, 0, 0);
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}
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}
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void BX_CPU_C::dbg_take_dma(void)
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{
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// NOTE: similar code in ::cpu_loop()
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if (BX_HRQ) {
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BX_CPU_THIS_PTR async_event = 1; // set in case INTR is triggered
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DEV_dma_raise_hlda();
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}
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}
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#endif // #if BX_DEBUGGER
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