133 lines
3.7 KiB
C++
133 lines
3.7 KiB
C++
/////////////////////////////////////////////////////////////////////////
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// $Id$
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (c) 2023 Stanislav Shwartsman
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// Written by Stanislav Shwartsman [sshwarts at sourceforge net]
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//
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// This library is free software; you can redistribute it and/or
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// modify it under the terms of the GNU Lesser General Public
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// License as published by the Free Software Foundation; either
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// version 2 of the License, or (at your option) any later version.
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//
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// This library is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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// Lesser General Public License for more details.
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//
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// You should have received a copy of the GNU Lesser General Public
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// License along with this library; if not, write to the Free Software
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// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA B 02110-1301 USA
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//
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/////////////////////////////////////////////////////////////////////////
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#define NEED_CPU_REG_SHORTCUTS 1
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#include "bochs.h"
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#include "cpu.h"
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#define LOG_THIS BX_CPU_THIS_PTR
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#if BX_SUPPORT_AVX
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#include "scalar_arith.h"
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BX_CPP_INLINE Bit64u s0(Bit64u val64)
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{
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return ror64(val64, 1) ^ ror64(val64, 8) ^ (val64 >> 7);
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}
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BX_CPP_INLINE Bit64u s1(Bit64u val64)
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{
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return ror64(val64, 19) ^ ror64(val64, 61) ^ (val64 >> 6);
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}
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BX_CPP_INLINE Bit64u cap_sigma0(Bit64u val64)
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{
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return ror64(val64, 28) ^ ror64(val64, 34) ^ ror64(val64, 39);
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}
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BX_CPP_INLINE Bit64u cap_sigma1(Bit64u val64)
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{
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return ror64(val64, 14) ^ ror64(val64, 18) ^ ror64(val64, 41);
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}
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BX_CPP_INLINE Bit64u sha_maj(Bit64u a, Bit64u b, Bit64u c)
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{
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return (a & b) ^ (a & c) ^ (b & c);
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}
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BX_CPP_INLINE Bit64u sha_ch(Bit64u e, Bit64u f, Bit64u g)
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{
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return (e & f) ^ (g & ~e);
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}
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// See https://nvlpubs.nist.gov/nistpubs/FIPS/NIST.FIPS.180-4.pdf for more information on the SHA512 standard
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void BX_CPP_AttrRegparmN(1) BX_CPU_C::VSHA512MSG1_VdqWdqR(bxInstruction_c *i)
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{
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BxPackedYmmRegister dst = BX_READ_YMM_REG(i->dst());
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Bit64u src = BX_READ_XMM_REG_LO_QWORD(i->src());
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dst.ymm64u(0) += s0(dst.ymm64u(1));
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dst.ymm64u(1) += s0(dst.ymm64u(2));
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dst.ymm64u(2) += s0(dst.ymm64u(3));
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dst.ymm64u(3) += s0(src);
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BX_WRITE_YMM_REGZ(i->dst(), dst);
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BX_NEXT_INSTR(i);
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}
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void BX_CPP_AttrRegparmN(1) BX_CPU_C::VSHA512MSG2_VdqWdqR(bxInstruction_c *i)
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{
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BxPackedYmmRegister dst = BX_READ_YMM_REG(i->dst()), src = BX_READ_YMM_REG(i->src());
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dst.ymm64u(0) += s1(src.ymm64u(2));
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dst.ymm64u(1) += s1(src.ymm64u(3));
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dst.ymm64u(2) += s1(dst.ymm64u(0));
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dst.ymm64u(3) += s1(dst.ymm64u(1));
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BX_WRITE_YMM_REGZ(i->dst(), dst);
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BX_NEXT_INSTR(i);
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}
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void BX_CPP_AttrRegparmN(1) BX_CPU_C::VSHA512RNDS2_VdqHdqWdqR(bxInstruction_c *i)
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{
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BxPackedYmmRegister dst = BX_READ_YMM_REG(i->dst()), op1 = BX_READ_YMM_REG(i->src1());
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BxPackedXmmRegister op2 = BX_READ_XMM_REG(i->src2());
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Bit64u A[3], B[3], C[3], D[3], E[3], F[3], G[3], H[3];
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A[0] = op1.ymm64u(3);
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B[0] = op1.ymm64u(2);
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C[0] = dst.ymm64u(3);
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D[0] = dst.ymm64u(2);
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E[0] = op1.ymm64u(1);
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F[0] = op1.ymm64u(0);
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G[0] = dst.ymm64u(1);
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H[0] = dst.ymm64u(0);
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for (unsigned n=0; n < 2; n++) {
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A[n+1] = sha_ch(E[n], F[n], G[n]) + cap_sigma1(E[n]) + op2.xmm64u(n) /* WK[n] */ + H[n] + sha_maj(A[n], B[n], C[n]) + cap_sigma0(A[n]);
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B[n+1] = A[n];
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C[n+1] = B[n];
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D[n+1] = C[n];
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E[n+1] = sha_ch(E[n], F[n], G[n]) + cap_sigma1(E[n]) + op2.xmm64u(n) /* WK[n] */ + H[n] + D[n];
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F[n+1] = E[n];
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G[n+1] = F[n];
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H[n+1] = G[n];
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}
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dst.ymm64u(3) = A[2];
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dst.ymm64u(2) = B[2];
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dst.ymm64u(1) = E[2];
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dst.ymm64u(0) = F[2];
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BX_WRITE_YMM_REGZ(i->dst(), dst);
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BX_NEXT_INSTR(i);
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}
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#endif
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