b200ff2058
PACKSSWB_VdqWq PCMPGTB_VdqWq PCMPGTW_VdqWq PCMPGTD_VdqWdq PACKUSWB_VdqWdq PCMPEQB_VdqWdq PCMPEQW_VdqWdq PCMPEQD_VdqWdq PADDQ_VdqWdq PSUBUSB_VdqWdq PSUBUSW_VdqWdq PAND_VdqWdq PANDN_VdqWdq PAVGB_VdqWdq PAVGW_VdqWdq POR_VdqWdq PXOR_VdqWdq PSUBB_VdqWdq PSUBW_VdqWdq PSUBD_VdqWdq PSUBQ_VdqWdq PADDB_VdqWdq PADDW_VdqWdq PADDD_VdqWdq PADDQ_VdqWdq
128 lines
4.1 KiB
C
128 lines
4.1 KiB
C
#ifndef BX_SSE_EXTENSIONS_H
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#define BX_SSE_EXTENSIONS_H
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/* XMM REGISTER */
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typedef Bit32u Float32;
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typedef Bit64u Float64;
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typedef union bx_xmm_reg_t {
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Bit8s _sbyte[16];
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Bit16s _s16[8];
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Bit32s _s32[4];
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Bit64s _s64[2];
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Bit8u _ubyte[16];
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Bit16u _u16[8];
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Bit32u _u32[4];
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Bit64u _u64[2];
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} BxPackedXmmRegister;
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#ifdef BX_SUPPORT_X86_64
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# define BX_XMM_REGISTERS 16
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#else
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# define BX_XMM_REGISTERS 8
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#endif
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#ifdef BX_BIG_ENDIAN
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#define xmm64s(i) _s64[1 - (i)]
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#define xmm32s(i) _s32[3 - (i)]
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#define xmm16s(i) _s16[7 - (i)]
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#define xmmsbyte(i) _sbyte[15 - (i)]
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#define xmmubyte(i) _ubyte[15 - (i)]
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#define xmm16u(i) _u16[7 - (i)]
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#define xmm32u(i) _u32[3 - (i)]
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#define xmm64u(i) _u64[1 - (i)]
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#else
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#define xmm64s(i) _s64[(i)]
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#define xmm32s(i) _s32[(i)]
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#define xmm16s(i) _s16[(i)]
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#define xmmsbyte(i) _sbyte[(i)]
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#define xmmubyte(i) _ubyte[(i)]
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#define xmm16u(i) _u16[(i)]
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#define xmm32u(i) _u32[(i)]
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#define xmm64u(i) _u64[(i)]
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#endif
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/* floating point representation: single and double precission */
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#define xmm32f(i) xmm32u(i)
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#define xmm64f(i) xmm64u(i)
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#define BX_READ_XMM_REG(index) (BX_CPU_THIS_PTR xmm[index])
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#define BX_WRITE_XMM_REG(index, reg) { BX_CPU_THIS_PTR xmm[index] = reg; }
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/* MXCSR REGISTER */
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/* 31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16
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* ==|==|=====|==|==|==|==|==|==|==|==|==|==|==|== (reserved)
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* 0| 0| 0| 0| 0| 0| 0| 0| 0| 0| 0| 0| 0| 0| 0| 0
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*
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* 15|14|13|12|11|10| 9| 8| 7| 6| 5| 4| 3| 2| 1| 0
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* ==|==|=====|==|==|==|==|==|==|==|==|==|==|==|==
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* FZ| R C |PM|UM|OM|ZM|DM|IM|DZ|PE|UE|OE|ZE|DE|IE
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*/
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/* MXCSR REGISTER FIELDS DESCRIPTION */
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/*
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* IE 0 Invalid-Operation Exception 0
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* DE 1 Denormalized-Operand Exception 0
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* ZE 2 Zero-Divide Exception 0
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* OE 3 Overflow Exception 0
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* UE 4 Underflow Exception 0
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* PE 5 Precision Exception 0
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* DZ 6 Denormals are Zeros 0
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* IM 7 Invalid-Operation Exception Mask 1
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* DM 8 Denormalized-Operand Exception Mask 1
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* ZM 9 Zero-Divide Exception Mask 1
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* OM 10 Overflow Exception Mask 1
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* UM 11 Underflow Exception Mask 1
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* PM 12 Precision Exception Mask 1
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* RC 13-14 Floating-Point Rounding Control 00
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* FZ 15 Flush-to-Zero for Masked Underflow 0
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*/
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struct bx_mxcsr_t {
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Bit32u mxcsr; /* define bitfields accessors later */
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};
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#define MXCSR_MASK 0x00ff /* reset reserved bits */
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#define MXCSR_RESET 0x1f80 /* reset value of the MXCSR register */
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/* INTEGER SATURATION */
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/*
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SaturateWordSToByteS converts a signed 16-bit value to a
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signed 8-bit value. If the signed 16-bit value is less than -128, it
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is represented by the saturated value -128 (0x80). If it is greater
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than 127, it is represented by the saturated value 127 (0x7F).
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*/
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Bit8s SaturateWordSToByteS(Bit16s value);
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/*
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SaturateDwordSToWordS converts a signed 32-bit value to a
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signed 16-bit value. If the signed 32-bit value is less than -32768,
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it is represented by the saturated value -32768 (0x8000). If it is
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greater than 32767, it is represented by the saturated value 32767
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(0x7FFF).
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*/
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Bit16s SaturateDwordSToWordS(Bit32s value);
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/*
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SaturateWordSToByteU converts a signed 16-bit value to an
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unsigned 8-bit value. If the signed 16-bit value is less than zero it
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is represented by the saturated value zero (0x00).If it is greater
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than 255 it is represented by the saturated value 255 (0xFF).
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*/
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Bit8u SaturateWordSToByteU(Bit16s value);
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/*
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SaturateDwordSToWordU converts a signed 32-bit value
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to an unsigned 16-bit value. If the signed 32-bit value is less
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than zero, it is represented by the saturated value 65535
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(0x0000). If it is greater than 65535, it is represented by
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the saturated value 65535 (0xFFFF).
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*/
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Bit16u SaturateDwordSToWordU(Bit32s value);
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#endif
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