412 lines
11 KiB
C++
412 lines
11 KiB
C++
// Copyright (C) 2001 MandrakeSoft S.A.
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//
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// MandrakeSoft S.A.
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// 43, rue d'Aboukir
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// 75002 Paris - France
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// http://www.linux-mandrake.com/
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// http://www.mandrakesoft.com/
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//
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// This library is free software; you can redistribute it and/or
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// modify it under the terms of the GNU Lesser General Public
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// License as published by the Free Software Foundation; either
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// version 2 of the License, or (at your option) any later version.
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//
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// This library is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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// Lesser General Public License for more details.
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//
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// You should have received a copy of the GNU Lesser General Public
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// License along with this library; if not, write to the Free Software
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// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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#include "bochs.h"
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#define LOG_THIS bx_pci.
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//
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// i440FX Support
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//
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bx_pci_c bx_pci;
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#if BX_USE_PCI_SMF
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#define this (&bx_pci)
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#endif
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bx_pci_c::bx_pci_c(void)
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{
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setprefix("[PCI ]");
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settype(PCILOG);
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}
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bx_pci_c::~bx_pci_c(void)
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{
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BX_INFO(("Exit.\n"));
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}
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void
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bx_pci_c::init(bx_devices_c *d)
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{
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// called once when bochs initializes
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BX_PCI_THIS devices = d;
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for (unsigned i=0x0CFC; i<=0x0CFF; i++) {
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d->register_io_read_handler(this, read_handler, i, "i440FX");
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}
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d->register_io_write_handler(this, write_handler, 0x0CF8, "i440FX");
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for (unsigned i=0x0CFC; i<=0x0CFF; i++) {
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d->register_io_write_handler(this, write_handler, i, "i440FX");
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}
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// should this go into ::reset() ???
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if (bx_options.i440FXSupport) {
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for (unsigned i=0; i<256; i++)
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BX_PCI_THIS s.i440fx.array[i] = 0x0;
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}
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}
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void
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bx_pci_c::reset(void)
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{
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// upon RESET
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}
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// static IO port read callback handler
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// redirects to non-static class handler to avoid virtual functions
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Bit32u
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bx_pci_c::read_handler(void *this_ptr, Bit32u address, unsigned io_len)
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{
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#if !BX_USE_PCI_SMF
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bx_pci_c *class_ptr = (bx_pci_c *) this_ptr;
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return( class_ptr->read(address, io_len) );
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}
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Bit32u
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bx_pci_c::read(Bit32u address, unsigned io_len)
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{
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#else
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UNUSED(this_ptr);
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#endif // !BX_USE_PCI_SMF
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switch (address) {
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case 0x0CFC:
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case 0x0CFD:
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case 0x0CFE:
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case 0x0CFF:
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{
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Bit32u idx440fx, val440fx, retMask;
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idx440fx = BX_PCI_THIS s.i440fx.confAddr & 0x00FC;
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val440fx = (BX_PCI_THIS s.i440fx.array[idx440fx] >> ((address & 0x3)*8) );
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switch (io_len) {
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case 1:
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retMask = 0xFF; break;
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case 2:
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retMask = 0xFFFF; break;
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case 4:
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retMask = 0xFFFFFFFF; break;
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default:
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retMask = 0xFFFFFFFF; break;
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}
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BX_INFO(("440FX IO read from port: %04x, len: %02x, data: %04x\n",
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address, io_len, (val440fx & retMask)));
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return (val440fx & retMask);
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}
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}
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BX_PANIC(("pci: unsupported IO read to port 0x%x\n",
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(unsigned) address));
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return(0xffffffff);
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}
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// static IO port write callback handler
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// redirects to non-static class handler to avoid virtual functions
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void
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bx_pci_c::write_handler(void *this_ptr, Bit32u address, Bit32u value, unsigned io_len)
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{
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#if !BX_USE_PCI_SMF
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bx_pci_c *class_ptr = (bx_pci_c *) this_ptr;
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class_ptr->write(address, value, io_len);
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}
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void
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bx_pci_c::write(Bit32u address, Bit32u value, unsigned io_len)
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{
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#else
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UNUSED(this_ptr);
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#endif // !BX_USE_PCI_SMF
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switch (address) {
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case 0xCF8:
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BX_PCI_THIS s.i440fx.confAddr = value;
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BX_INFO(("440FX IO write to port %04x of %04x, len %02x \n",
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address, value, io_len));
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break;
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case 0xCFC:
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{
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Bit32u dMask, idx;
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switch (io_len) {
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case 1:
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dMask = 0xFF; break;
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case 2:
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dMask = 0xFFFF; break;
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case 4:
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dMask = 0xFFFFFFFF; break;
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default:
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dMask = 0x0; break;
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}
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if (BX_PCI_THIS s.i440fx.confAddr & 0x80000000) {
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idx = (BX_PCI_THIS s.i440fx.confAddr & 0xFC);
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BX_PCI_THIS s.i440fx.array[idx] = (BX_PCI_THIS s.i440fx.array[idx] & ~dMask) | (value & dMask);
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BX_INFO(("440FX IO write to port %04x of %04x, len %02x \n",
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address, value, io_len));
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}
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}
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break;
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case 0xCFD:
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{
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Bit32u dMask, idx;
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switch (io_len) {
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case 1:
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dMask = 0xFF00; break;
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case 2:
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dMask = 0xFFFF00; break;
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default:
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dMask = 0x0; break;
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}
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if (BX_PCI_THIS s.i440fx.confAddr & 0x80000000) {
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idx = (BX_PCI_THIS s.i440fx.confAddr & 0xFC);
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BX_PCI_THIS s.i440fx.array[idx] = (BX_PCI_THIS s.i440fx.array[idx] & ~dMask) | ((value << 8) & dMask);
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BX_INFO(("440FX IO write to port %04x of %04x, len %02x \n",
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address, value, io_len));
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}
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}
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break;
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case 0xCFE:
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{
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Bit32u dMask, idx;
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switch (io_len) {
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case 1:
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dMask = 0xFF0000; break;
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case 2:
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dMask = 0xFFFF0000; break;
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default:
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dMask = 0x0; break;
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}
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if (BX_PCI_THIS s.i440fx.confAddr & 0x80000000) {
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idx = (BX_PCI_THIS s.i440fx.confAddr & 0xFC);
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BX_PCI_THIS s.i440fx.array[idx] = (BX_PCI_THIS s.i440fx.array[idx] & ~dMask) | ((value << 16) & dMask);
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BX_INFO(("440FX IO write to port %04x of %04x, len %02x \n",
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address, value, io_len));
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}
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}
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break;
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case 0xCFF:
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{
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Bit32u dMask, idx;
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switch (io_len) {
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case 1:
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dMask = 0xFF000000; break;
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default:
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dMask = 0x0; break;
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}
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if (BX_PCI_THIS s.i440fx.confAddr & 0x80000000) {
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idx = (BX_PCI_THIS s.i440fx.confAddr & 0xFC);
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BX_PCI_THIS s.i440fx.array[idx] = (BX_PCI_THIS s.i440fx.array[idx] & ~dMask) | ((value << 24) & dMask);
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BX_INFO(("440FX IO write to port %04x of %04x, len %02x \n",
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address, value, io_len));
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}
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}
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break;
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default:
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BX_PANIC(("pci: IO write to port 0x%x\n", (unsigned) address));
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}
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}
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Bit32u
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bx_pci_c::mapRead (Bit32u val)
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{
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switch (val) {
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case 0x0:
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case 0x2:
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return (1); // (0) Goto ROM
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case 0x1:
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case 0x3:
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return (0); // (1) Goto Shadow
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}
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return (2);
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}
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Bit32u
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bx_pci_c::mapWrite (Bit32u val)
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{
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switch (val) {
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case 0x0:
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case 0x1:
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return (1); // (0) Goto ROM
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case 0x2:
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case 0x3:
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return (0); // (1) Goto Shadow
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}
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return (2);
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}
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Bit32u
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bx_pci_c::rd_memType (Bit32u addr)
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{
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switch ((addr & 0xFC000) >> 12) {
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case 0xC0:
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return (mapRead ( (BX_PCI_THIS s.i440fx.array[0x58] >> 16) & 0x3));
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case 0xC4:
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return (mapRead ( (BX_PCI_THIS s.i440fx.array[0x58] >> 20) & 0x3));
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case 0xC8:
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return (mapRead ( (BX_PCI_THIS s.i440fx.array[0x58] >> 24) & 0x3));
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case 0xCC:
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return (mapRead ( (BX_PCI_THIS s.i440fx.array[0x58] >> 28) & 0x3));
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case 0xD0:
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return (mapRead (BX_PCI_THIS s.i440fx.array[0x5C] & 0x3));
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case 0xD4:
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return (mapRead ( (BX_PCI_THIS s.i440fx.array[0x5C] >> 4) & 0x3));
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case 0xD8:
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return (mapRead ( (BX_PCI_THIS s.i440fx.array[0x5C] >> 8) & 0x3));
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case 0xDC:
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return (mapRead ( (BX_PCI_THIS s.i440fx.array[0x5C] >> 12) & 0x3));
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case 0xE0:
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return (mapRead ( (BX_PCI_THIS s.i440fx.array[0x5C] >> 16) & 0x3));
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case 0xE4:
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return (mapRead ( (BX_PCI_THIS s.i440fx.array[0x5C] >> 20) & 0x3));
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case 0xE8:
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return (mapRead ( (BX_PCI_THIS s.i440fx.array[0x5C] >> 24) & 0x3));
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case 0xEC:
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return (mapRead ( (BX_PCI_THIS s.i440fx.array[0x5C] >> 28) & 0x3));
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case 0xF0:
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case 0xF4:
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case 0xF8:
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case 0xFC:
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return (mapRead ( (BX_PCI_THIS s.i440fx.array[0x58] >> 12) & 0x3));
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default:
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BX_PANIC(("wr_memType () Error: Memory Type not known !\n"));
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return(0); // keep compiler happy
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break;
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}
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}
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Bit32u
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bx_pci_c::wr_memType (Bit32u addr)
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{
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switch ((addr & 0xFC000) >> 12) {
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case 0xC0:
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return (mapWrite ( (BX_PCI_THIS s.i440fx.array[0x58] >> 16) & 0x3));
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case 0xC4:
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return (mapWrite ( (BX_PCI_THIS s.i440fx.array[0x58] >> 20) & 0x3));
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case 0xC8:
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return (mapWrite ( (BX_PCI_THIS s.i440fx.array[0x58] >> 24) & 0x3));
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case 0xCC:
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return (mapWrite ( (BX_PCI_THIS s.i440fx.array[0x58] >> 28) & 0x3));
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case 0xD0:
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return (mapWrite (BX_PCI_THIS s.i440fx.array[0x5C] & 0x3));
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case 0xD4:
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return (mapWrite ( (BX_PCI_THIS s.i440fx.array[0x5C] >> 4) & 0x3));
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case 0xD8:
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return (mapWrite ( (BX_PCI_THIS s.i440fx.array[0x5C] >> 8) & 0x3));
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case 0xDC:
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return (mapWrite ( (BX_PCI_THIS s.i440fx.array[0x5C] >> 12) & 0x3));
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case 0xE0:
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return (mapWrite ( (BX_PCI_THIS s.i440fx.array[0x5C] >> 16) & 0x3));
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case 0xE4:
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return (mapWrite ( (BX_PCI_THIS s.i440fx.array[0x5C] >> 20) & 0x3));
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case 0xE8:
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return (mapWrite ( (BX_PCI_THIS s.i440fx.array[0x5C] >> 24) & 0x3));
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case 0xEC:
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return (mapWrite ( (BX_PCI_THIS s.i440fx.array[0x5C] >> 28) & 0x3));
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case 0xF0:
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case 0xF4:
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case 0xF8:
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case 0xFC:
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return (mapWrite ( (BX_PCI_THIS s.i440fx.array[0x58] >> 12) & 0x3));
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default:
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BX_PANIC(("rd_memType () Error: Memory Type not known !\n"));
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return(0); // keep compiler happy
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break;
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}
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}
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void
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bx_pci_c::print_i440fx_state()
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{
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#ifdef DUMP_FULL_I440FX
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int i;
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#endif /* DUMP_FULL_I440FX */
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BX_INFO(( "i440fxConfAddr:0x%x\n", BX_PCI_THIS s.i440fx.confAddr ));
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BX_INFO(( "i440fxConfData:0x%x\n", BX_PCI_THIS s.i440fx.confData ));
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#ifdef DUMP_FULL_I440FX
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for (i=0; i<256; i++) {
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BX_INFO(( "i440fxArray%02x:0x%x\n", i, BX_PCI_THIS s.i440fx.array[i] ));
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}
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#else /* DUMP_FULL_I440FX */
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BX_INFO(( "i440fxArray58:0x%x\n", BX_PCI_THIS s.i440fx.array[0x58] ));
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BX_INFO(( "i440fxArray5c:0x%x\n", BX_PCI_THIS s.i440fx.array[0x5c] ));
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#endif /* DUMP_FULL_I440FX */
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}
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Bit8u*
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bx_pci_c::i440fx_fetch_ptr(Bit32u addr)
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{
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if (bx_options.i440FXSupport) {
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switch (rd_memType (addr)) {
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case 0x0: // Read from ShadowRAM
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return (&devices->mem->vector[addr]);
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case 0x1: // Read from ROM
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return (&s.i440fx.shadow[(addr - 0xc0000)]);
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default:
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BX_PANIC(("i440fx_fetch_ptr(): default case\n"));
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return(0);
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}
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}
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else
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return (&devices->mem->vector[addr]);
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}
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