Bochs/bochs/instrument/example0/instrument.cc
Bryce Denney cec9135e9f - Apply patch.replace-Boolean rev 1.3. Every "Boolean" is now changed to a
"bx_bool" which is always defined as Bit32u on all platforms.  In Carbon
  specific code, Boolean is still used because the Carbon header files
  define it to unsigned char.
- this fixes bug [ 623152 ] MacOSX: Triple Exception Booting win95.
  The bug was that some code in Bochs depends on Boolean to be a
  32 bit value.  (This should be fixed, but I don't know all the places
  where it needs to be fixed yet.)  Because Carbon defined Boolean as
  an unsigned char, Bochs just followed along and used the unsigned char
  definition to avoid compile problems.  This exposed the dependency
  on 32 bit Boolean on MacOS X only and led to major simulation problems,
  that could only be reproduced and debugged on that platform.
- On the mailing list we debated whether to make all Booleans into "bool" or
  our own type.  I chose bx_bool for several reasons.
  1. Unlike C++'s bool, we can guarantee that bx_bool is the same size on all
     platforms, which makes it much less likely to have more platform-specific
     simulation differences in the future.  (I spent hours on a borrowed
     MacOSX machine chasing bug 618388 before discovering that different sized
     Booleans were the problem, and I don't want to repeat that.)
  2. We still have at least one dependency on 32 bit Booleans which must be
     fixed some time, but I don't want to risk introducing new bugs into the
     simulation just before the 2.0 release.

Modified Files:
    bochs.h config.h.in gdbstub.cc logio.cc main.cc pc_system.cc
    pc_system.h plugin.cc plugin.h bios/rombios.c cpu/apic.cc
    cpu/arith16.cc cpu/arith32.cc cpu/arith64.cc cpu/arith8.cc
    cpu/cpu.cc cpu/cpu.h cpu/ctrl_xfer16.cc cpu/ctrl_xfer32.cc
    cpu/ctrl_xfer64.cc cpu/data_xfer16.cc cpu/data_xfer32.cc
    cpu/data_xfer64.cc cpu/debugstuff.cc cpu/exception.cc
    cpu/fetchdecode.cc cpu/flag_ctrl_pro.cc cpu/init.cc
    cpu/io_pro.cc cpu/lazy_flags.cc cpu/lazy_flags.h cpu/mult16.cc
    cpu/mult32.cc cpu/mult64.cc cpu/mult8.cc cpu/paging.cc
    cpu/proc_ctrl.cc cpu/segment_ctrl_pro.cc cpu/stack_pro.cc
    cpu/tasking.cc debug/dbg_main.cc debug/debug.h debug/sim2.cc
    disasm/dis_decode.cc disasm/disasm.h doc/docbook/Makefile
    docs-html/cosimulation.html fpu/wmFPUemu_glue.cc
    gui/amigaos.cc gui/beos.cc gui/carbon.cc gui/gui.cc gui/gui.h
    gui/keymap.cc gui/keymap.h gui/macintosh.cc gui/nogui.cc
    gui/rfb.cc gui/sdl.cc gui/siminterface.cc gui/siminterface.h
    gui/term.cc gui/win32.cc gui/wx.cc gui/wxmain.cc gui/wxmain.h
    gui/x.cc instrument/example0/instrument.cc
    instrument/example0/instrument.h
    instrument/example1/instrument.cc
    instrument/example1/instrument.h
    instrument/stubs/instrument.cc instrument/stubs/instrument.h
    iodev/cdrom.cc iodev/cdrom.h iodev/cdrom_osx.cc iodev/cmos.cc
    iodev/devices.cc iodev/dma.cc iodev/dma.h iodev/eth_arpback.cc
    iodev/eth_packetmaker.cc iodev/eth_packetmaker.h
    iodev/floppy.cc iodev/floppy.h iodev/guest2host.h
    iodev/harddrv.cc iodev/harddrv.h iodev/ioapic.cc
    iodev/ioapic.h iodev/iodebug.cc iodev/iodev.h
    iodev/keyboard.cc iodev/keyboard.h iodev/ne2k.h
    iodev/parallel.h iodev/pci.cc iodev/pci.h iodev/pic.h
    iodev/pit.cc iodev/pit.h iodev/pit_wrap.cc iodev/pit_wrap.h
    iodev/sb16.cc iodev/sb16.h iodev/serial.cc iodev/serial.h
    iodev/vga.cc iodev/vga.h memory/memory.h memory/misc_mem.cc
2002-10-25 11:44:41 +00:00

277 lines
6.7 KiB
C++

/////////////////////////////////////////////////////////////////////////
// $Id: instrument.cc,v 1.7 2002-10-25 11:44:37 bdenney Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
//
// MandrakeSoft S.A.
// 43, rue d'Aboukir
// 75002 Paris - France
// http://www.linux-mandrake.com/
// http://www.mandrakesoft.com/
//
// This library is free software; you can redistribute it and/or
// modify it under the terms of the GNU Lesser General Public
// License as published by the Free Software Foundation; either
// version 2 of the License, or (at your option) any later version.
//
// This library is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// Lesser General Public License for more details.
//
// You should have received a copy of the GNU Lesser General Public
// License along with this library; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
#include "bochs.h"
#include "cpu/cpu.h"
// maximum size of an instruction
#define MAX_OPCODE_SIZE 16
// maximum physical addresses an instruction can generate
#define MAX_DATA_ACCESSES 1024
// Use this variable to turn on/off collection of instrumentation data
// If you are not using the debugger to turn this on/off, then possibly
// start this at 1 instead of 0.
static bx_bool active = 1;
static struct instruction_t {
bx_bool valid; // is current instruction valid
unsigned opcode_size;
unsigned nprefixes;
Bit8u opcode[MAX_OPCODE_SIZE];
bx_bool is32;
unsigned num_data_accesses;
struct {
bx_address laddr; // linear address
bx_address paddr; // physical address
unsigned op; // BX_READ or BX_WRITE
unsigned size; // 1 .. 8
} data_access[MAX_DATA_ACCESSES];
bx_bool is_branch;
bx_bool is_taken;
bx_address target_linear;
} instruction[BX_SMP_PROCESSORS];
static logfunctions *instrument_log = new logfunctions ();
#define LOG_THIS instrument_log->
void bx_instr_reset(unsigned cpu)
{
instruction[cpu].valid = 0;
instruction[cpu].nprefixes = 0;
instruction[cpu].num_data_accesses = 0;
instruction[cpu].is_branch = 0;
}
void bx_instr_new_instruction(unsigned cpu)
{
if (!active)
{
return;
}
instruction_t *i = &instruction[cpu];
if (i->valid)
{
char disasm_tbuf[512]; // buffer for instruction disassembly
unsigned length = i->opcode_size, n;
bx_disassemble.disasm(i->is32, 0, i->opcode, disasm_tbuf);
if(length != 0)
{
fprintf(stderr, "----------------------------------------------------------\n");
fprintf(stderr, "CPU: %d: %s\n", cpu, disasm_tbuf);
fprintf(stderr, "LEN: %d\tPREFIX: %d\tBYTES: ", length, i->nprefixes);
for(n=0;n<length;n++) fprintf(stderr, "%02x", i->opcode[n]);
if(i->is_branch)
{
fprintf(stderr, "\tBRANCH ");
if(i->is_taken)
fprintf(stderr, "TARGET %08x (TAKEN)", i->target_linear);
else
fprintf(stderr, "(NOT TAKEN)");
}
fprintf(stderr, "\n");
for(n=0;n<i->num_data_accesses;n++)
{
fprintf(stderr, "MEM ACCESS: %08x (linear) %08x (physical) %s SIZE: %d\n",
i->data_access[n].laddr,
i->data_access[n].paddr,
i->data_access[n].op == BX_READ ? "RD":"WR",
i->data_access[n].size);
}
fprintf(stderr, "\n");
}
}
instruction[cpu].valid = 0;
instruction[cpu].nprefixes = 0;
instruction[cpu].num_data_accesses = 0;
instruction[cpu].is_branch = 0;
}
static void branch_taken(unsigned cpu, bx_address new_eip)
{
Bit32u laddr;
if (!active)
{
return;
}
if (!instruction[cpu].valid)
{
return;
}
// find linear address
laddr = BX_CPU(cpu)->get_segment_base(BX_SREG_CS) + new_eip;
instruction[cpu].is_branch = 1;
instruction[cpu].is_taken = 1;
instruction[cpu].target_linear = laddr;
}
void bx_instr_cnear_branch_taken(unsigned cpu, bx_address new_eip)
{
branch_taken(cpu, new_eip);
}
void bx_instr_cnear_branch_not_taken(unsigned cpu)
{
if (!active)
{
return;
}
if (!instruction[cpu].valid)
{
return;
}
instruction[cpu].is_branch = 1;
instruction[cpu].is_taken = 0;
}
void bx_instr_ucnear_branch(unsigned cpu, unsigned what, bx_address new_eip) {
branch_taken(cpu, new_eip);
}
void bx_instr_far_branch(unsigned cpu, unsigned what, Bit16u new_cs, bx_address new_eip) {
branch_taken(cpu, new_eip);
}
void bx_instr_opcode(unsigned cpu, Bit8u *opcode, unsigned len, bx_bool is32)
{
if (!active)
{
return;
}
for(int i=0;i<len;i++)
{
instruction[cpu].opcode[i] = opcode[i];
}
instruction[cpu].is32 = is32;
instruction[cpu].opcode_size = len;
}
void bx_instr_fetch_decode_completed(unsigned cpu, const bxInstruction_c *i)
{
if(active)
{
instruction[cpu].valid = 1;
}
}
#define PROCESS_PREFIX(name) \
void bx_instr_prefix_##name(unsigned cpu) \
{ \
if(active) instruction[cpu].nprefixes++; \
}
PROCESS_PREFIX(as);
PROCESS_PREFIX(os);
PROCESS_PREFIX(rep);
PROCESS_PREFIX(repne);
PROCESS_PREFIX(lock);
PROCESS_PREFIX(cs);
PROCESS_PREFIX(ss);
PROCESS_PREFIX(ds);
PROCESS_PREFIX(es);
PROCESS_PREFIX(fs);
PROCESS_PREFIX(gs);
PROCESS_PREFIX(extend8b);
void bx_instr_interrupt(unsigned cpu, unsigned vector)
{
if(active)
{
fprintf(stderr, "CPU %u: interrupt %02xh\n", cpu, vector);
}
}
void bx_instr_exception(unsigned cpu, unsigned vector)
{
if(active)
{
fprintf(stderr, "CPU %u: exception %02xh\n", cpu, vector);
}
}
void bx_instr_hwinterrupt(unsigned cpu, unsigned vector, Bit16u cs, bx_address eip)
{
if(active)
{
fprintf(stderr, "CPU %u: hardware interrupt %02xh\n", cpu, vector);
}
}
void bx_instr_mem_data(unsigned cpu, bx_address lin, unsigned size, unsigned rw)
{
unsigned index;
bx_address phy;
bx_bool page_valid;
if(!active)
{
return;
}
if (!instruction[cpu].valid)
{
return;
}
if (instruction[cpu].num_data_accesses >= MAX_DATA_ACCESSES)
{
return;
}
BX_CPU(cpu)->dbg_xlate_linear2phy(lin, &phy, &page_valid);
phy = A20ADDR(phy);
// If linear translation doesn't exist, a paging exception will occur.
// Invalidate physical address data for now.
if (!page_valid)
{
phy = 0;
}
index = instruction[cpu].num_data_accesses;
instruction[cpu].data_access[index].laddr = lin;
instruction[cpu].data_access[index].paddr = phy;
instruction[cpu].data_access[index].op = rw;
instruction[cpu].data_access[index].size = size;
instruction[cpu].num_data_accesses++;
}