370 lines
11 KiB
C++
370 lines
11 KiB
C++
/////////////////////////////////////////////////////////////////////////
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// $Id$
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2002-2017 The Bochs Project
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//
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// This library is free software; you can redistribute it and/or
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// modify it under the terms of the GNU Lesser General Public
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// License as published by the Free Software Foundation; either
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// version 2 of the License, or (at your option) any later version.
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//
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// This library is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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// Lesser General Public License for more details.
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//
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// You should have received a copy of the GNU Lesser General Public
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// License along with this library; if not, write to the Free Software
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// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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/////////////////////////////////////////////////////////////////////////
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// Define BX_PLUGGABLE in files that can be compiled into plugins. For
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// platforms that require a special tag on exported symbols, BX_PLUGGABLE
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// is used to know when we are exporting symbols and when we are importing.
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#define BX_PLUGGABLE
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#include "iodev.h"
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#if BX_SUPPORT_APIC
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#include "ioapic.h"
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#define LOG_THIS theIOAPIC->
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bx_ioapic_c *theIOAPIC = NULL;
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int CDECL libioapic_LTX_plugin_init(plugin_t *plugin, plugintype_t type)
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{
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theIOAPIC = new bx_ioapic_c();
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bx_devices.pluginIOAPIC = theIOAPIC;
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BX_REGISTER_DEVICE_DEVMODEL(plugin, type, theIOAPIC, BX_PLUGIN_IOAPIC);
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return(0); // Success
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}
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void CDECL libioapic_LTX_plugin_fini(void)
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{
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bx_devices.pluginIOAPIC = &bx_devices.stubIOAPIC;
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delete theIOAPIC;
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}
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static bx_bool ioapic_read(bx_phy_address a20addr, unsigned len, void *data, void *param)
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{
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if((a20addr & ~0x3) != ((a20addr+len-1) & ~0x3)) {
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BX_PANIC(("I/O APIC read at address 0x" FMT_PHY_ADDRX " spans 32-bit boundary !", a20addr));
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return 1;
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}
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Bit32u value = theIOAPIC->read_aligned(a20addr & ~0x3);
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if(len == 4) { // must be 32-bit aligned
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*((Bit32u *)data) = value;
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return 1;
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}
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// handle partial read, independent of endian-ness
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value >>= (a20addr&3)*8;
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if (len == 1)
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*((Bit8u *) data) = value & 0xff;
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else if (len == 2)
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*((Bit16u *)data) = value & 0xffff;
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else
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BX_PANIC(("Unsupported I/O APIC read at address 0x" FMT_PHY_ADDRX ", len=%d", a20addr, len));
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return 1;
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}
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static bx_bool ioapic_write(bx_phy_address a20addr, unsigned len, void *data, void *param)
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{
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if(a20addr & 0xf) {
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BX_PANIC(("I/O apic write at unaligned address 0x" FMT_PHY_ADDRX, a20addr));
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return 1;
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}
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if (len == 4) {
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theIOAPIC->write_aligned(a20addr, *((Bit32u*) data));
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}
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else {
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if ((a20addr & 0xff) != 0)
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BX_PANIC(("I/O apic write with len=%d (should be 4) at address 0x" FMT_PHY_ADDRX, len, a20addr));
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if (len == 2)
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theIOAPIC->write_aligned(a20addr, (Bit32u) *((Bit16u*) data));
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else if (len == 1)
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theIOAPIC->write_aligned(a20addr, (Bit32u) *((Bit8u*) data));
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else
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BX_PANIC(("Unsupported I/O APIC write at address 0x" FMT_PHY_ADDRX ", len=%d", a20addr, len));
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}
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return 1;
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}
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void bx_io_redirect_entry_t::sprintf_self(char *buf)
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{
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sprintf(buf, "dest=%02x, masked=%d, trig_mode=%d, remote_irr=%d, polarity=%d, delivery_status=%d, dest_mode=%d, delivery_mode=%d, vector=%02x",
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(unsigned) destination(),
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(unsigned) is_masked(),
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(unsigned) trigger_mode(),
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(unsigned) remote_irr(),
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(unsigned) pin_polarity(),
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(unsigned) delivery_status(),
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(unsigned) destination_mode(),
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(unsigned) delivery_mode(),
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(unsigned) vector());
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}
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void bx_io_redirect_entry_t::register_state(bx_param_c *parent)
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{
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BXRS_HEX_PARAM_SIMPLE(parent, lo);
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BXRS_HEX_PARAM_SIMPLE(parent, hi);
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}
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#define BX_IOAPIC_BASE_ADDR (0xfec00000)
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#define BX_IOAPIC_DEFAULT_ID (BX_SMP_PROCESSORS)
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bx_ioapic_c::bx_ioapic_c(): enabled(0), base_addr(BX_IOAPIC_BASE_ADDR)
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{
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set_id(BX_IOAPIC_DEFAULT_ID);
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put("IOAPIC");
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}
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bx_ioapic_c::~bx_ioapic_c()
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{
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SIM->get_bochs_root()->remove("ioapic");
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BX_DEBUG(("Exit"));
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}
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void bx_ioapic_c::init(void)
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{
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BX_INFO(("initializing I/O APIC"));
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set_enabled(1, 0x0000);
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#if BX_DEBUGGER
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// register device for the 'info device' command (calls debug_dump())
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bx_dbg_register_debug_info("ioapic", this);
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#endif
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}
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void bx_ioapic_c::reset(unsigned type)
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{
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// all interrupts masked
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for (int i=0; i<BX_IOAPIC_NUM_PINS; i++) {
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ioredtbl[i].set_lo_part(0x00010000);
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ioredtbl[i].set_hi_part(0x00000000);
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}
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intin = 0;
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irr = 0;
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ioregsel = 0;
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}
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Bit32u bx_ioapic_c::read_aligned(bx_phy_address address)
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{
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BX_DEBUG(("IOAPIC: read aligned addr=0x" FMT_PHY_ADDRX, address));
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address &= 0xff;
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if (address == 0x00) {
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// select register
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return ioregsel;
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} else {
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if (address != 0x10)
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BX_PANIC(("IOAPIC: read from unsupported address"));
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}
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Bit32u data = 0;
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// only reached when reading data register
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switch (ioregsel) {
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case 0x00: // APIC ID, note this is 4bits, the upper 4 are reserved
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data = ((id & apic_id_mask) << 24);
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break;
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case 0x01: // version
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data = BX_IOAPIC_VERSION_ID;
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break;
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case 0x02:
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BX_INFO(("IOAPIC: arbitration ID unsupported, returned 0"));
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break;
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default:
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int index = (ioregsel - 0x10) >> 1;
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if (index >= 0 && index < BX_IOAPIC_NUM_PINS) {
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bx_io_redirect_entry_t *entry = ioredtbl + index;
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data = (ioregsel&1) ? entry->get_hi_part() : entry->get_lo_part();
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break;
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}
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BX_PANIC(("IOAPIC: IOREGSEL points to undefined register %02x", ioregsel));
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}
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return data;
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}
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void bx_ioapic_c::write_aligned(bx_phy_address address, Bit32u value)
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{
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BX_DEBUG(("IOAPIC: write aligned addr=%08x, data=%08x", (unsigned) address, value));
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address &= 0xff;
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if (address == 0x00) {
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ioregsel = value;
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return;
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} else {
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if (address != 0x10)
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BX_PANIC(("IOAPIC: write to unsupported address"));
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}
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// only reached when writing data register
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switch (ioregsel) {
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case 0x00: // set APIC ID
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{
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Bit8u newid = (value >> 24) & apic_id_mask;
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BX_INFO(("IOAPIC: setting id to 0x%x", newid));
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set_id (newid);
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return;
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}
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case 0x01: // version
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case 0x02: // arbitration id
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BX_INFO(("IOAPIC: could not write, IOREGSEL=0x%02x", ioregsel));
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return;
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default:
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int index = (ioregsel - 0x10) >> 1;
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if (index >= 0 && index < BX_IOAPIC_NUM_PINS) {
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bx_io_redirect_entry_t *entry = ioredtbl + index;
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if (ioregsel&1)
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entry->set_hi_part(value);
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else
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entry->set_lo_part(value);
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char buf[1024];
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entry->sprintf_self(buf);
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BX_DEBUG(("IOAPIC: now entry[%d] is %s", index, buf));
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service_ioapic();
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return;
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}
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BX_PANIC(("IOAPIC: IOREGSEL points to undefined register %02x", ioregsel));
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}
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}
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void bx_ioapic_c::set_enabled(bx_bool _enabled, Bit16u base_offset)
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{
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if (_enabled != enabled) {
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if (_enabled) {
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base_addr = BX_IOAPIC_BASE_ADDR | base_offset;
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DEV_register_memory_handlers(theIOAPIC,
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ioapic_read, ioapic_write, base_addr, base_addr + 0xfff);
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} else {
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DEV_unregister_memory_handlers(theIOAPIC, base_addr, base_addr + 0xfff);
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}
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enabled = _enabled;
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} else if (enabled && (base_offset != (base_addr & 0xffff))) {
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DEV_unregister_memory_handlers(theIOAPIC, base_addr, base_addr + 0xfff);
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base_addr = BX_IOAPIC_BASE_ADDR | base_offset;
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DEV_register_memory_handlers(theIOAPIC,
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ioapic_read, ioapic_write, base_addr, base_addr + 0xfff);
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}
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BX_INFO(("IOAPIC %sabled (base address = 0x%08x)", enabled?"en":"dis", (Bit32u)base_addr));
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}
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void bx_ioapic_c::set_irq_level(Bit8u int_in, bx_bool level)
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{
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if (int_in == 0) { // timer connected to pin #2
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int_in = 2;
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}
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if (int_in < BX_IOAPIC_NUM_PINS) {
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Bit32u bit = 1<<int_in;
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if ((level<<int_in) != (intin & bit)) {
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BX_DEBUG(("set_irq_level(): INTIN%d: level=%d", int_in, level));
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bx_io_redirect_entry_t *entry = ioredtbl + int_in;
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if (entry->trigger_mode()) {
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// level triggered
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if (level) {
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intin |= bit;
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irr |= bit;
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service_ioapic();
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} else {
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intin &= ~bit;
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irr &= ~bit;
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}
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} else {
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// edge triggered
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if (level) {
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intin |= bit;
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if (!entry->is_masked()) {
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irr |= bit;
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service_ioapic();
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}
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} else {
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intin &= ~bit;
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}
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}
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}
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}
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}
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void bx_ioapic_c::receive_eoi(Bit8u vector)
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{
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BX_DEBUG(("IOAPIC: received EOI for vector %d", vector));
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}
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void bx_ioapic_c::service_ioapic()
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{
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static unsigned int stuck = 0;
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Bit8u vector = 0;
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// look in IRR and deliver any interrupts that are not masked.
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BX_DEBUG(("IOAPIC: servicing"));
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for (unsigned bit=0; bit < BX_IOAPIC_NUM_PINS; bit++) {
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Bit32u mask = 1<<bit;
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if (irr & mask) {
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bx_io_redirect_entry_t *entry = ioredtbl + bit;
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if (! entry->is_masked()) {
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// clear irr bit and deliver
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if (entry->delivery_mode() == 7) {
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vector = DEV_pic_iac();
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} else {
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vector = entry->vector();
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}
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bx_bool done = apic_bus_deliver_interrupt(vector, entry->destination(), entry->delivery_mode(), entry->destination_mode(), entry->pin_polarity(), entry->trigger_mode());
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if (done) {
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if (! entry->trigger_mode())
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irr &= ~mask;
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entry->clear_delivery_status();
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stuck = 0;
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} else {
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entry->set_delivery_status();
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stuck++;
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if (stuck > 5)
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BX_INFO(("vector %#x stuck?", vector));
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}
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}
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else {
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BX_DEBUG(("service_ioapic(): INTIN%d is masked", bit));
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}
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}
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}
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}
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void bx_ioapic_c::register_state(void)
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{
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bx_list_c *list = new bx_list_c(SIM->get_bochs_root(), "ioapic", "IOAPIC State");
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BXRS_HEX_PARAM_SIMPLE(list, ioregsel);
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BXRS_HEX_PARAM_SIMPLE(list, intin);
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BXRS_HEX_PARAM_SIMPLE(list, irr);
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bx_list_c *table = new bx_list_c(list, "ioredtbl");
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for (unsigned i=0; i<BX_IOAPIC_NUM_PINS; i++) {
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char name[6];
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sprintf(name, "0x%02x", i);
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bx_list_c *entry = new bx_list_c(table, name);
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ioredtbl[i].register_state(entry);
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}
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}
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#if BX_DEBUGGER
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void bx_ioapic_c::debug_dump(int argc, char **argv)
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{
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int i;
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char buf[1024];
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dbg_printf("82093AA I/O APIC\n\n");
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for (i = 0; i < BX_IOAPIC_NUM_PINS; i++) {
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bx_io_redirect_entry_t *entry = ioredtbl + i;
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entry->sprintf_self(buf);
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dbg_printf("entry[%d]: %s\n", i, buf);
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}
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if (argc > 0) {
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dbg_printf("\nAdditional options not supported\n");
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}
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}
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#endif
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#endif /* if BX_SUPPORT_APIC */
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