e7093e74d8
- Added new PCI chipset choice for the i440BX AGPset. Some basic work is done, but AGP support is not present yet. - Added new class for the "virtual" PCI-to-PCI bridge that should manage the secondary bus (AGP). Since this device must appear with device number #1 at the primary bus, it was required to change the PCI device numbers for the i440BX case. Moved the PIIX4 module to device number #7. The presence of the PCI base address regions now depends on the header type as expected. - Since the Bochs BIOS cannot handle the modified PCI device layout, all tests continued with an external BIOS designed for this chipset (GA-6BA_F1.bin). This BIOS requires additional changes in some devices. - ACPI: Return value 0 for some status registers and the GPI registers. - CMOS: Since the PIIX4 supports a 256 byte CMOS RAM, prepared support for it and enable it in case a 256 byte CMOS image is used. - PCI: The device numbers for 4 slots starting at #8. The 5th slot could be used for AGP when available.
102 lines
2.9 KiB
C++
102 lines
2.9 KiB
C++
/////////////////////////////////////////////////////////////////////////
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// $Id$
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2002-2018 The Bochs Project
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//
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// This library is free software; you can redistribute it and/or
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// modify it under the terms of the GNU Lesser General Public
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// License as published by the Free Software Foundation; either
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// version 2 of the License, or (at your option) any later version.
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//
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// This library is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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// Lesser General Public License for more details.
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//
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// You should have received a copy of the GNU Lesser General Public
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// License along with this library; if not, write to the Free Software
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// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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//
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#ifndef BX_IODEV_CMOS_H
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#define BX_IODEV_CMOS_H
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#if BX_USE_CMOS_SMF
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# define BX_CMOS_SMF static
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# define BX_CMOS_THIS theCmosDevice->
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#else
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# define BX_CMOS_SMF
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# define BX_CMOS_THIS this->
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#endif
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class bx_cmos_c : public bx_cmos_stub_c {
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public:
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bx_cmos_c();
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virtual ~bx_cmos_c();
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virtual void init(void);
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virtual void checksum_cmos(void);
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virtual void reset(unsigned type);
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virtual void save_image(void);
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virtual void register_state(void);
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virtual void after_restore_state(void);
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#if BX_DEBUGGER
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virtual void debug_dump(int argc, char **argv);
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#endif
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virtual Bit32u get_reg(Bit8u reg) {
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return s.reg[reg];
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}
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virtual void set_reg(Bit8u reg, Bit32u val) {
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s.reg[reg] = val;
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}
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virtual time_t get_timeval() {
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return s.timeval;
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}
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virtual void enable_irq(bx_bool enabled) {
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s.irq_enabled = enabled;
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}
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struct {
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int periodic_timer_index;
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Bit32u periodic_interval_usec;
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int one_second_timer_index;
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int uip_timer_index;
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time_t timeval;
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Bit8u cmos_mem_address;
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Bit8u cmos_ext_mem_addr;
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bx_bool timeval_change;
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bx_bool rtc_mode_12hour;
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bx_bool rtc_mode_binary;
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bx_bool rtc_sync;
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bx_bool irq_enabled;
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Bit8u reg[256];
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Bit8u max_reg;
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} s; // state information
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private:
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static Bit32u read_handler(void *this_ptr, Bit32u address, unsigned io_len);
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static void write_handler(void *this_ptr, Bit32u address, Bit32u value, unsigned io_len);
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#if !BX_USE_CMOS_SMF
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Bit32u read(Bit32u address, unsigned io_len);
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void write(Bit32u address, Bit32u value, unsigned len);
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#endif
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public:
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static void periodic_timer_handler(void *);
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static void one_second_timer_handler(void *);
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static void uip_timer_handler(void *);
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BX_CMOS_SMF void periodic_timer(void);
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BX_CMOS_SMF void one_second_timer(void);
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BX_CMOS_SMF void uip_timer(void);
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private:
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BX_CMOS_SMF void update_clock(void);
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BX_CMOS_SMF void update_timeval(void);
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BX_CMOS_SMF void CRA_change(void);
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};
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#endif
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