263 lines
6.9 KiB
C++
263 lines
6.9 KiB
C++
/////////////////////////////////////////////////////////////////////////
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// $Id$
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001-2012 The Bochs Project
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//
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// This library is free software; you can redistribute it and/or
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// modify it under the terms of the GNU Lesser General Public
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// License as published by the Free Software Foundation; either
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// version 2 of the License, or (at your option) any later version.
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//
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// This library is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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// Lesser General Public License for more details.
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//
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// You should have received a copy of the GNU Lesser General Public
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// License along with this library; if not, write to the Free Software
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// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA B 02110-1301 USA
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/////////////////////////////////////////////////////////////////////////
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#define NEED_CPU_REG_SHORTCUTS 1
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#include "bochs.h"
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#include "cpu.h"
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#define LOG_THIS BX_CPU_THIS_PTR
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::PUSH_RX(bxInstruction_c *i)
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{
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push_16(BX_READ_16BIT_REG(i->rm()));
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BX_NEXT_INSTR(i);
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}
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::PUSH16_Sw(bxInstruction_c *i)
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{
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push_16(BX_CPU_THIS_PTR sregs[i->nnn()].selector.value);
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BX_NEXT_INSTR(i);
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}
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::POP16_Sw(bxInstruction_c *i)
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{
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RSP_SPECULATIVE;
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Bit16u selector = pop_16();
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load_seg_reg(&BX_CPU_THIS_PTR sregs[i->nnn()], selector);
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RSP_COMMIT;
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if (i->nnn() == BX_SEG_REG_SS) {
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// POP SS inhibits interrupts, debug exceptions and single-step
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// trap exceptions until the execution boundary following the
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// next instruction is reached.
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// Same code as MOV_SwEw()
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inhibit_interrupts(BX_INHIBIT_INTERRUPTS_BY_MOVSS);
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}
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BX_NEXT_INSTR(i);
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}
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::POP_RX(bxInstruction_c *i)
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{
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BX_WRITE_16BIT_REG(i->rm(), pop_16());
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BX_NEXT_INSTR(i);
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}
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::POP_EwM(bxInstruction_c *i)
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{
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RSP_SPECULATIVE;
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Bit16u val16 = pop_16();
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// Note: there is one little weirdism here. It is possible to use
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// SP in the modrm addressing. If used, the value of SP after the
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// pop is used to calculate the address.
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bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
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write_virtual_word(i->seg(), eaddr, val16);
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RSP_COMMIT;
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BX_NEXT_INSTR(i);
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}
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::PUSH_Iw(bxInstruction_c *i)
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{
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push_16(i->Iw());
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BX_NEXT_INSTR(i);
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}
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::PUSH_EwM(bxInstruction_c *i)
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{
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bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
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Bit16u op1_16 = read_virtual_word(i->seg(), eaddr);
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push_16(op1_16);
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BX_NEXT_INSTR(i);
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}
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::PUSHAD16(bxInstruction_c *i)
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{
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Bit32u temp_ESP = ESP;
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Bit16u temp_SP = SP;
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if (BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.d_b)
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{
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stack_write_word((Bit32u)(temp_ESP - 2), AX);
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stack_write_word((Bit32u)(temp_ESP - 4), CX);
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stack_write_word((Bit32u)(temp_ESP - 6), DX);
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stack_write_word((Bit32u)(temp_ESP - 8), BX);
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stack_write_word((Bit32u)(temp_ESP - 10), temp_SP);
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stack_write_word((Bit32u)(temp_ESP - 12), BP);
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stack_write_word((Bit32u)(temp_ESP - 14), SI);
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stack_write_word((Bit32u)(temp_ESP - 16), DI);
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ESP -= 16;
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}
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else
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{
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stack_write_word((Bit16u)(temp_SP - 2), AX);
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stack_write_word((Bit16u)(temp_SP - 4), CX);
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stack_write_word((Bit16u)(temp_SP - 6), DX);
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stack_write_word((Bit16u)(temp_SP - 8), BX);
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stack_write_word((Bit16u)(temp_SP - 10), temp_SP);
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stack_write_word((Bit16u)(temp_SP - 12), BP);
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stack_write_word((Bit16u)(temp_SP - 14), SI);
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stack_write_word((Bit16u)(temp_SP - 16), DI);
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SP -= 16;
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}
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BX_NEXT_INSTR(i);
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}
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::POPAD16(bxInstruction_c *i)
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{
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Bit16u di, si, bp, bx, dx, cx, ax;
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if (BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.d_b)
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{
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Bit32u temp_ESP = ESP;
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di = stack_read_word((Bit32u)(temp_ESP + 0));
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si = stack_read_word((Bit32u)(temp_ESP + 2));
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bp = stack_read_word((Bit32u)(temp_ESP + 4));
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stack_read_word((Bit32u)(temp_ESP + 6));
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bx = stack_read_word((Bit32u)(temp_ESP + 8));
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dx = stack_read_word((Bit32u)(temp_ESP + 10));
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cx = stack_read_word((Bit32u)(temp_ESP + 12));
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ax = stack_read_word((Bit32u)(temp_ESP + 14));
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ESP += 16;
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}
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else
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{
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Bit16u temp_SP = SP;
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di = stack_read_word((Bit16u)(temp_SP + 0));
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si = stack_read_word((Bit16u)(temp_SP + 2));
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bp = stack_read_word((Bit16u)(temp_SP + 4));
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stack_read_word((Bit16u)(temp_SP + 6));
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bx = stack_read_word((Bit16u)(temp_SP + 8));
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dx = stack_read_word((Bit16u)(temp_SP + 10));
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cx = stack_read_word((Bit16u)(temp_SP + 12));
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ax = stack_read_word((Bit16u)(temp_SP + 14));
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SP += 16;
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}
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DI = di;
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SI = si;
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BP = bp;
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BX = bx;
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DX = dx;
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CX = cx;
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AX = ax;
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BX_NEXT_INSTR(i);
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}
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::ENTER16_IwIb(bxInstruction_c *i)
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{
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Bit16u imm16 = i->Iw();
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Bit8u level = i->Ib2();
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level &= 0x1F;
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RSP_SPECULATIVE;
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push_16(BP);
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Bit16u frame_ptr16 = SP;
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if (BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.d_b) {
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Bit32u ebp = EBP; // Use temp copy for case of exception.
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if (level > 0) {
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/* do level-1 times */
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while (--level) {
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ebp -= 2;
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Bit16u temp16 = stack_read_word(ebp);
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push_16(temp16);
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}
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/* push(frame pointer) */
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push_16(frame_ptr16);
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}
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ESP -= imm16;
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// ENTER finishes with memory write check on the final stack pointer
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// the memory is touched but no write actually occurs
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// emulate it by doing RMW read access from SS:ESP
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read_RMW_virtual_word(BX_SEG_REG_SS, ESP);
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BP = frame_ptr16;
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}
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else {
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Bit16u bp = BP;
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if (level > 0) {
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/* do level-1 times */
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while (--level) {
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bp -= 2;
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Bit16u temp16 = stack_read_word(bp);
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push_16(temp16);
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}
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/* push(frame pointer) */
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push_16(frame_ptr16);
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}
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SP -= imm16;
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// ENTER finishes with memory write check on the final stack pointer
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// the memory is touched but no write actually occurs
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// emulate it by doing RMW read access from SS:SP
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read_RMW_virtual_word_32(BX_SEG_REG_SS, SP);
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}
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BP = frame_ptr16;
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RSP_COMMIT;
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BX_NEXT_INSTR(i);
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}
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::LEAVE16(bxInstruction_c *i)
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{
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BX_ASSERT(BX_CPU_THIS_PTR cpu_mode != BX_MODE_LONG_64);
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Bit16u value16;
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if (BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.d_b) {
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value16 = stack_read_word(EBP);
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ESP = EBP + 2;
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}
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else {
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value16 = stack_read_word(BP);
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SP = BP + 2;
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}
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BP = value16;
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BX_NEXT_INSTR(i);
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}
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