e61d00351f
in BRANCH-smp-bochs revisions. - The general task was to make multiple CPU's which communicate through their APICs. So instead of BX_CPU and BX_MEM, we now have BX_CPU(x) and BX_MEM(y). For an SMP simulation you have several processors in a shared memory space, so there might be processors BX_CPU(0..3) but only one memory space BX_MEM(0). For cosimulation, you could have BX_CPU(0) with BX_MEM(0), then BX_CPU(1) with BX_MEM(1). WARNING: Cosimulation is almost certainly broken by the SMP changes. - to simulate multiple CPUs, you have to give each CPU time to execute in turn. This is currently implemented using debugger guards. The cpu loop steps one CPU for a few instructions, then steps the next CPU for a few instructions, etc. - there is some limited support in the debugger for two CPUs, for example printing information from each CPU when single stepping.
183 lines
3.8 KiB
C++
183 lines
3.8 KiB
C++
// Copyright (C) 2001 MandrakeSoft S.A.
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//
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// MandrakeSoft S.A.
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// 43, rue d'Aboukir
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// 75002 Paris - France
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// http://www.linux-mandrake.com/
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// http://www.mandrakesoft.com/
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//
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// This library is free software; you can redistribute it and/or
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// modify it under the terms of the GNU Lesser General Public
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// License as published by the Free Software Foundation; either
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// version 2 of the License, or (at your option) any later version.
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//
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// This library is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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// Lesser General Public License for more details.
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//
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// You should have received a copy of the GNU Lesser General Public
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// License along with this library; if not, write to the Free Software
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// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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#include "bochs.h"
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#define LOG_THIS BX_CPU_THIS_PTR
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void
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BX_CPU_C::PUSH_RX(BxInstruction_t *i)
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{
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push_16( BX_CPU_THIS_PTR gen_reg[i->b1 & 0x07].word.rx );
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}
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void
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BX_CPU_C::POP_RX(BxInstruction_t *i)
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{
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Bit16u rx;
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pop_16(&rx);
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BX_CPU_THIS_PTR gen_reg[i->b1 & 0x07].word.rx = rx;
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}
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void
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BX_CPU_C::POP_Ew(BxInstruction_t *i)
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{
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Bit16u val16;
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pop_16(&val16);
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if (i->mod == 0xc0) {
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BX_WRITE_16BIT_REG(i->rm, val16);
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}
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else {
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// Note: there is one little weirdism here. When 32bit addressing
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// is used, it is possible to use ESP in the modrm addressing.
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// If used, the value of ESP after the pop is used to calculate
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// the address.
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if (i->as_32 && (i->mod!=0xc0) && (i->rm==4) && (i->base==4)) {
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BX_CPU_CALL_METHOD (i->ResolveModrm, (i));
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}
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write_virtual_word(i->seg, i->rm_addr, &val16);
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}
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}
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void
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BX_CPU_C::PUSHAD16(BxInstruction_t *i)
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{
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#if BX_CPU_LEVEL < 2
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BX_PANIC(("PUSHAD: not supported on an 8086\n"));
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#else
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Bit32u temp_ESP;
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Bit16u sp;
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if (BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.d_b)
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temp_ESP = ESP;
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else
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temp_ESP = SP;
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#if BX_CPU_LEVEL >= 2
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if (protected_mode()) {
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if ( !can_push(&BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache, temp_ESP, 16) ) {
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BX_PANIC(("PUSHA(): stack doesn't have enough room!\n"));
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exception(BX_SS_EXCEPTION, 0, 0);
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return;
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}
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}
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else
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#endif
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{
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if (temp_ESP < 16)
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BX_PANIC(("pushad: eSP < 16\n"));
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}
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sp = SP;
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/* ??? optimize this by using virtual write, all checks passed */
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push_16(AX);
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push_16(CX);
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push_16(DX);
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push_16(BX);
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push_16(sp);
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push_16(BP);
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push_16(SI);
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push_16(DI);
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#endif
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}
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void
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BX_CPU_C::POPAD16(BxInstruction_t *i)
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{
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#if BX_CPU_LEVEL < 2
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BX_PANIC(("POPAD not supported on an 8086\n"));
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#else /* 286+ */
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Bit16u di, si, bp, tmp, bx, dx, cx, ax;
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if (protected_mode()) {
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if ( !can_pop(16) ) {
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BX_PANIC(("pop_a: not enough bytes on stack\n"));
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exception(BX_SS_EXCEPTION, 0, 0);
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return;
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}
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}
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/* ??? optimize this */
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pop_16(&di);
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pop_16(&si);
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pop_16(&bp);
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pop_16(&tmp); /* value for SP discarded */
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pop_16(&bx);
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pop_16(&dx);
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pop_16(&cx);
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pop_16(&ax);
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DI = di;
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SI = si;
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BP = bp;
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BX = bx;
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DX = dx;
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CX = cx;
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AX = ax;
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#endif
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}
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void
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BX_CPU_C::PUSH_Iw(BxInstruction_t *i)
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{
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#if BX_CPU_LEVEL < 2
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BX_PANIC(("PUSH_Iv: not supported on 8086!\n"));
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#else
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Bit16u imm16;
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imm16 = i->Iw;
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push_16(imm16);
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#endif
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}
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void
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BX_CPU_C::PUSH_Ew(BxInstruction_t *i)
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{
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Bit16u op1_16;
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/* op1_16 is a register or memory reference */
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if (i->mod == 0xc0) {
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op1_16 = BX_READ_16BIT_REG(i->rm);
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}
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else {
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/* pointer, segment address pair */
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read_virtual_word(i->seg, i->rm_addr, &op1_16);
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}
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push_16(op1_16);
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}
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