268 lines
7.1 KiB
C
268 lines
7.1 KiB
C
/////////////////////////////////////////////////////////////////////////
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// $Id$
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (c) 2006-2009 Stanislav Shwartsman
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// Written by Stanislav Shwartsman [sshwarts at sourceforge net]
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//
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// This library is free software; you can redistribute it and/or
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// modify it under the terms of the GNU Lesser General Public
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// License as published by the Free Software Foundation; either
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// version 2 of the License, or (at your option) any later version.
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//
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// This library is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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// Lesser General Public License for more details.
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//
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// You should have received a copy of the GNU Lesser General Public
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// License along with this library; if not, write to the Free Software
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// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA B 02110-1301 USA
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/////////////////////////////////////////////////////////////////////////
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#ifndef BX_SMM_H
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#define BX_SMM_H
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/* SMM feature masks */
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#define SMM_IO_INSTRUCTION_RESTART (0x00010000)
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#define SMM_SMBASE_RELOCATION (0x00020000)
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#define SMM_SAVE_STATE_MAP_SIZE 128
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//
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// - For x86-64 configuration using AMD Athlon 64 512-byte SMM save state map
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// revision ID according to QEMU/Bochs BIOS
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//
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// - For x86-32 configuration using Intel P6 512-byte SMM save state map
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//
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#define SMM_REVISION_ID \
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((BX_SUPPORT_X86_64 ? 0x00000064 : 0) | SMM_SMBASE_RELOCATION)
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//
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// Some of the CPU field must be saved and restored in order to continue the
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// simulation correctly after the RSM instruction:
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//
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// ---------------------------------------------------------------
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//
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// 1. General purpose registers: EAX-EDI, R8-R15
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// 2. EIP, RFLAGS
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// 3. Segment registers CS, DS, SS, ES, FS, GS
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// fields: valid - not required, initialized according to selector value
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// p - must be saved/restored
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// dpl - must be saved/restored
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// segment - must be 1 for seg registers, not required to save
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// type - must be saved/restored
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// base - must be saved/restored
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// limit - must be saved/restored
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// g - must be saved/restored
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// d_b - must be saved/restored
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// l - must be saved/restored
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// avl - must be saved/restored
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// 4. GDTR, IDTR
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// fields: base, limit
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// 5. LDTR, TR
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// fields: base, limit, anything else ?
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// 6. Debug Registers DR0-DR7, only DR6 and DR7 are saved
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// 7. Control Registers: CR0, CR2 is NOT saved, CR3, CR4, EFER
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// 8. SMBASE
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// 9. MSR/FPU/XMM/APIC are NOT saved accoring to Intel docs
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//
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struct BX_SMM_State
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{
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Bit32u smbase;
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Bit32u smm_revision_id;
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bx_address gen_reg[BX_GENERAL_REGISTERS];
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bx_address rip;
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Bit32u eflags;
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Bit32u dr6;
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Bit32u dr7;
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bx_cr0_t cr0;
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bx_address cr3;
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#if BX_CPU_LEVEL >= 5
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bx_cr4_t cr4;
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bx_efer_t efer;
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#endif
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Bit32u io_insruction_restart;
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Bit32u autohalt_restart;
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Bit32u nmi_mask;
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bx_global_segment_reg_t gdtr;
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bx_global_segment_reg_t idtr;
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struct {
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bx_address base;
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Bit32u limit;
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Bit32u selector_ar;
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} segreg[6], tr, ldtr;
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};
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#if BX_SUPPORT_X86_64
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enum SMMRAM_Fields {
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SMRAM_FIELD_SMBASE_OFFSET = 0,
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SMRAM_FIELD_SMM_REVISION_ID,
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SMRAM_FIELD_RAX_HI32,
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SMRAM_FIELD_EAX,
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SMRAM_FIELD_RCX_HI32,
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SMRAM_FIELD_ECX,
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SMRAM_FIELD_RDX_HI32,
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SMRAM_FIELD_EDX,
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SMRAM_FIELD_RBX_HI32,
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SMRAM_FIELD_EBX,
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SMRAM_FIELD_RSP_HI32,
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SMRAM_FIELD_ESP,
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SMRAM_FIELD_RBP_HI32,
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SMRAM_FIELD_EBP,
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SMRAM_FIELD_RSI_HI32,
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SMRAM_FIELD_ESI,
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SMRAM_FIELD_RDI_HI32,
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SMRAM_FIELD_EDI,
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SMRAM_FIELD_R8_HI32,
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SMRAM_FIELD_R8,
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SMRAM_FIELD_R9_HI32,
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SMRAM_FIELD_R9,
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SMRAM_FIELD_R10_HI32,
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SMRAM_FIELD_R10,
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SMRAM_FIELD_R11_HI32,
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SMRAM_FIELD_R11,
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SMRAM_FIELD_R12_HI32,
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SMRAM_FIELD_R12,
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SMRAM_FIELD_R13_HI32,
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SMRAM_FIELD_R13,
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SMRAM_FIELD_R14_HI32,
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SMRAM_FIELD_R14,
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SMRAM_FIELD_R15_HI32,
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SMRAM_FIELD_R15,
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SMRAM_FIELD_RIP_HI32,
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SMRAM_FIELD_EIP,
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SMRAM_FIELD_RFLAGS_HI32, // always zero
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SMRAM_FIELD_EFLAGS,
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SMRAM_FIELD_DR6_HI32, // always zero
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SMRAM_FIELD_DR6,
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SMRAM_FIELD_DR7_HI32, // always zero
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SMRAM_FIELD_DR7,
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SMRAM_FIELD_CR0_HI32, // always zero
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SMRAM_FIELD_CR0,
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SMRAM_FIELD_CR3_HI32, // zero when physical address size 32-bit
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SMRAM_FIELD_CR3,
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SMRAM_FIELD_CR4_HI32, // always zero
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SMRAM_FIELD_CR4,
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SMRAM_FIELD_EFER_HI32, // always zero
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SMRAM_FIELD_EFER,
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SMRAM_FIELD_IO_INSTRUCTION_RESTART,
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SMRAM_FIELD_AUTOHALT_RESTART,
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SMRAM_FIELD_NMI_MASK,
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SMRAM_FIELD_TR_BASE_HI32,
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SMRAM_FIELD_TR_BASE,
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SMRAM_FIELD_TR_LIMIT,
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SMRAM_FIELD_TR_SELECTOR_AR,
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SMRAM_FIELD_LDTR_BASE_HI32,
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SMRAM_FIELD_LDTR_BASE,
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SMRAM_FIELD_LDTR_LIMIT,
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SMRAM_FIELD_LDTR_SELECTOR_AR,
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SMRAM_FIELD_IDTR_BASE_HI32,
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SMRAM_FIELD_IDTR_BASE,
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SMRAM_FIELD_IDTR_LIMIT,
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SMRAM_FIELD_GDTR_BASE_HI32,
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SMRAM_FIELD_GDTR_BASE,
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SMRAM_FIELD_GDTR_LIMIT,
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SMRAM_FIELD_ES_BASE_HI32,
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SMRAM_FIELD_ES_BASE,
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SMRAM_FIELD_ES_LIMIT,
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SMRAM_FIELD_ES_SELECTOR_AR,
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SMRAM_FIELD_CS_BASE_HI32,
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SMRAM_FIELD_CS_BASE,
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SMRAM_FIELD_CS_LIMIT,
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SMRAM_FIELD_CS_SELECTOR_AR,
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SMRAM_FIELD_SS_BASE_HI32,
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SMRAM_FIELD_SS_BASE,
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SMRAM_FIELD_SS_LIMIT,
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SMRAM_FIELD_SS_SELECTOR_AR,
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SMRAM_FIELD_DS_BASE_HI32,
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SMRAM_FIELD_DS_BASE,
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SMRAM_FIELD_DS_LIMIT,
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SMRAM_FIELD_DS_SELECTOR_AR,
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SMRAM_FIELD_FS_BASE_HI32,
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SMRAM_FIELD_FS_BASE,
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SMRAM_FIELD_FS_LIMIT,
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SMRAM_FIELD_FS_SELECTOR_AR,
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SMRAM_FIELD_GS_BASE_HI32,
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SMRAM_FIELD_GS_BASE,
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SMRAM_FIELD_GS_LIMIT,
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SMRAM_FIELD_GS_SELECTOR_AR,
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SMRAM_FIELD_LAST
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};
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#else
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enum SMMRAM_Fields {
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SMRAM_FIELD_SMBASE_OFFSET = 0,
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SMRAM_FIELD_SMM_REVISION_ID,
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SMRAM_FIELD_EAX,
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SMRAM_FIELD_ECX,
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SMRAM_FIELD_EDX,
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SMRAM_FIELD_EBX,
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SMRAM_FIELD_ESP,
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SMRAM_FIELD_EBP,
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SMRAM_FIELD_ESI,
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SMRAM_FIELD_EDI,
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SMRAM_FIELD_EIP,
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SMRAM_FIELD_EFLAGS,
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SMRAM_FIELD_DR6,
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SMRAM_FIELD_DR7,
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SMRAM_FIELD_CR0,
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SMRAM_FIELD_CR3,
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SMRAM_FIELD_CR4,
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SMRAM_FIELD_EFER,
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SMRAM_FIELD_IO_INSTRUCTION_RESTART,
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SMRAM_FIELD_AUTOHALT_RESTART,
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SMRAM_FIELD_NMI_MASK,
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SMRAM_FIELD_TR_SELECTOR,
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SMRAM_FIELD_TR_BASE,
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SMRAM_FIELD_TR_LIMIT,
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SMRAM_FIELD_TR_SELECTOR_AR,
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SMRAM_FIELD_LDTR_SELECTOR,
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SMRAM_FIELD_LDTR_BASE,
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SMRAM_FIELD_LDTR_LIMIT,
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SMRAM_FIELD_LDTR_SELECTOR_AR,
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SMRAM_FIELD_IDTR_BASE,
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SMRAM_FIELD_IDTR_LIMIT,
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SMRAM_FIELD_GDTR_BASE,
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SMRAM_FIELD_GDTR_LIMIT,
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SMRAM_FIELD_ES_SELECTOR,
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SMRAM_FIELD_ES_BASE,
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SMRAM_FIELD_ES_LIMIT,
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SMRAM_FIELD_ES_SELECTOR_AR,
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SMRAM_FIELD_CS_SELECTOR,
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SMRAM_FIELD_CS_BASE,
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SMRAM_FIELD_CS_LIMIT,
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SMRAM_FIELD_CS_SELECTOR_AR,
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SMRAM_FIELD_SS_SELECTOR,
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SMRAM_FIELD_SS_BASE,
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SMRAM_FIELD_SS_LIMIT,
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SMRAM_FIELD_SS_SELECTOR_AR,
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SMRAM_FIELD_DS_SELECTOR,
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SMRAM_FIELD_DS_BASE,
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SMRAM_FIELD_DS_LIMIT,
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SMRAM_FIELD_DS_SELECTOR_AR,
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SMRAM_FIELD_FS_SELECTOR,
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SMRAM_FIELD_FS_BASE,
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SMRAM_FIELD_FS_LIMIT,
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SMRAM_FIELD_FS_SELECTOR_AR,
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SMRAM_FIELD_GS_SELECTOR,
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SMRAM_FIELD_GS_BASE,
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SMRAM_FIELD_GS_LIMIT,
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SMRAM_FIELD_GS_SELECTOR_AR,
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SMRAM_FIELD_LAST
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};
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#endif // BX_SUPPORT_X86_64
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#endif
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